From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>, intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Date: Thu, 25 Jan 2018 15:40:02 -0200 [thread overview]
Message-ID: <1516902002.16643.39.camel@intel.com> (raw)
In-Reply-To: <20180120000524.4746-1-rodrigo.vivi@intel.com>
Em Sex, 2018-01-19 às 16:05 -0800, Rodrigo Vivi escreveu:
> The only difference is that this SKUs has the full
> Port A/E split named as Port F.
>
> But since SKUs differences don't matter on the platform
> definition group and ids, let's merge all off them together.
>
> v2: Really include the PCI IDs to the picidlist[];
> v3: Add the PCI Id for another SKU (Anusha).
> v4: Update IDs, really include to pciidlists again.
> v5: Unify all GT2 IDs.
> v6: Unify in a way that we don't break early-quirks.c
> v7: Remove GT reference since it doesn't matter here (Paulo)
> Also move IS_CNL_WITH_PORT_F macro to this patch to
> make it easier for review this part and also to get
> used sooner.
>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(although I still would have preferred the split)
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 5 ++---
> include/drm/i915_pciids.h | 18 +++++++-----------
> 3 files changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..3d3727829ac7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2647,6 +2647,8 @@ intel_info(const struct drm_i915_private
> *dev_priv)
> (dev_priv)->info.gt == 2)
> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> (dev_priv)->info.gt == 3)
> +#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> + (INTEL_DEVID(dev_priv) &
> 0x0004) == 0x0004)
>
> #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)-
> >is_alpha_support)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index f28c165fc49d..7eb3d5e4350e 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -571,7 +571,7 @@ static const struct intel_device_info
> intel_coffeelake_gt3_info __initconst = {
> .ddb_size = 1024, \
> GLK_COLORS
>
> -static const struct intel_device_info intel_cannonlake_gt2_info
> __initconst = {
> +static const struct intel_device_info intel_cannonlake_info
> __initconst = {
> GEN10_FEATURES,
> .is_alpha_support = 1,
> .platform = INTEL_CANNONLAKE,
> @@ -649,8 +649,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
> INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> - INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
> - INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
> + INTEL_CNL_IDS(&intel_cannonlake_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 5db0458dd832..9e1fe6634424 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -414,24 +414,20 @@
> INTEL_CFL_U_GT2_IDS(info), \
> INTEL_CFL_U_GT3_IDS(info)
>
> -/* CNL U 2+2 */
> -#define INTEL_CNL_U_GT2_IDS(info) \
> +/* CNL */
> +#define INTEL_CNL_IDS(info) \
> INTEL_VGA_DEVICE(0x5A52, info), \
> INTEL_VGA_DEVICE(0x5A5A, info), \
> INTEL_VGA_DEVICE(0x5A42, info), \
> - INTEL_VGA_DEVICE(0x5A4A, info)
> -
> -/* CNL Y 2+2 */
> -#define INTEL_CNL_Y_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x5A4A, info), \
> INTEL_VGA_DEVICE(0x5A51, info), \
> INTEL_VGA_DEVICE(0x5A59, info), \
> INTEL_VGA_DEVICE(0x5A41, info), \
> INTEL_VGA_DEVICE(0x5A49, info), \
> INTEL_VGA_DEVICE(0x5A71, info), \
> - INTEL_VGA_DEVICE(0x5A79, info)
> -
> -#define INTEL_CNL_IDS(info) \
> - INTEL_CNL_U_GT2_IDS(info), \
> - INTEL_CNL_Y_GT2_IDS(info)
> + INTEL_VGA_DEVICE(0x5A79, info), \
> + INTEL_VGA_DEVICE(0x5A54, info), \
> + INTEL_VGA_DEVICE(0x5A5C, info), \
> + INTEL_VGA_DEVICE(0x5A44, info)
>
> #endif /* _I915_PCIIDS_H */
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next prev parent reply other threads:[~2018-01-25 17:40 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 02/10] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2018-01-22 23:42 ` Pandiyan, Dhinakaran
2018-01-22 23:59 ` [PATCH] " Rodrigo Vivi
2018-01-23 2:43 ` Pandiyan, Dhinakaran
2018-01-23 4:53 ` Pandiyan, Dhinakaran
2018-01-23 16:12 ` Lucas De Marchi
2018-01-23 16:30 ` Rodrigo Vivi
2018-01-23 18:35 ` Runyan, Arthur J
2018-01-23 21:57 ` [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F Rodrigo Vivi
2018-01-23 23:21 ` Lucas De Marchi
2018-01-23 21:10 ` [PATCH] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 03/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
2018-01-22 21:44 ` Pandiyan, Dhinakaran
2018-01-22 23:08 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 05/10] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 06/10] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
2018-01-22 16:40 ` Ville Syrjälä
2018-01-22 23:05 ` [PATCH] " Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
2018-01-22 16:51 ` Ville Syrjälä
2018-01-22 23:20 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
2018-01-23 3:12 ` Pandiyan, Dhinakaran
2018-01-23 16:29 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 09/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
2018-01-22 16:46 ` Ville Syrjälä
2018-01-23 22:32 ` [PATCH] " Rodrigo Vivi
2018-01-23 22:45 ` Manasi Navare
2018-01-20 0:05 ` [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
2018-01-22 12:12 ` Imre Deak
2018-01-22 23:48 ` [PATCH] " Rodrigo Vivi
2018-01-23 3:03 ` Pandiyan, Dhinakaran
2018-01-23 16:27 ` Rodrigo Vivi
2018-01-23 23:11 ` Rodrigo Vivi
2018-01-20 0:30 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
2018-01-20 8:40 ` ✗ Fi.CI.IGT: warning " Patchwork
2018-01-22 16:56 ` [PATCH 01/10] " Ville Syrjälä
2018-01-22 23:00 ` Rodrigo Vivi
2018-01-23 0:11 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4) Patchwork
2018-01-23 0:32 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5) Patchwork
2018-01-23 6:54 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-01-23 22:16 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev6) Patchwork
2018-01-23 22:36 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev7) Patchwork
2018-01-23 23:15 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev8) Patchwork
2018-01-25 17:40 ` Paulo Zanoni [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-01-25 19:27 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2018-01-26 10:12 ` Jani Nikula
2018-01-26 17:26 ` Rodrigo Vivi
2018-01-27 9:05 ` Jani Nikula
2018-01-29 19:09 ` Pandiyan, Dhinakaran
2018-01-29 20:35 ` Jani Nikula
2018-01-30 10:48 ` Tvrtko Ursulin
2018-01-25 22:03 Rodrigo Vivi
2018-01-29 23:22 Rodrigo Vivi
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