diff for duplicates of <151912240616348@kroah.com> diff --git a/a/1.txt b/N1/1.txt index 231da3e..e2747e0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -12,3 +12,338 @@ and it can be found in the queue-4.15 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@vger.kernel.org> know about it. + + +>From 1299ef1d8870d2d9f09a5aadf2f8b2c887c2d033 Mon Sep 17 00:00:00 2001 +From: Andy Lutomirski <luto@kernel.org> +Date: Wed, 31 Jan 2018 08:03:10 -0800 +Subject: x86/mm: Rename flush_tlb_single() and flush_tlb_one() to __flush_tlb_one_[user|kernel]() + +From: Andy Lutomirski <luto@kernel.org> + +commit 1299ef1d8870d2d9f09a5aadf2f8b2c887c2d033 upstream. + +flush_tlb_single() and flush_tlb_one() sound almost identical, but +they really mean "flush one user translation" and "flush one kernel +translation". Rename them to flush_tlb_one_user() and +flush_tlb_one_kernel() to make the semantics more obvious. + +[ I was looking at some PTI-related code, and the flush-one-address code + is unnecessarily hard to understand because the names of the helpers are + uninformative. This came up during PTI review, but no one got around to + doing it. ] + +Signed-off-by: Andy Lutomirski <luto@kernel.org> +Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> +Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> +Cc: Borislav Petkov <bp@alien8.de> +Cc: Brian Gerst <brgerst@gmail.com> +Cc: Dave Hansen <dave.hansen@intel.com> +Cc: Eduardo Valentin <eduval@amazon.com> +Cc: Hugh Dickins <hughd@google.com> +Cc: Josh Poimboeuf <jpoimboe@redhat.com> +Cc: Juergen Gross <jgross@suse.com> +Cc: Kees Cook <keescook@google.com> +Cc: Linus Torvalds <torvalds@linux-foundation.org> +Cc: Linux-MM <linux-mm@kvack.org> +Cc: Rik van Riel <riel@redhat.com> +Cc: Thomas Gleixner <tglx@linutronix.de> +Cc: Will Deacon <will.deacon@arm.com> +Link: http://lkml.kernel.org/r/3303b02e3c3d049dc5235d5651e0ae6d29a34354.1517414378.git.luto@kernel.org +Signed-off-by: Ingo Molnar <mingo@kernel.org> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +--- + arch/x86/include/asm/paravirt.h | 4 ++-- + arch/x86/include/asm/paravirt_types.h | 2 +- + arch/x86/include/asm/pgtable_32.h | 2 +- + arch/x86/include/asm/tlbflush.h | 27 ++++++++++++++++++++------- + arch/x86/kernel/paravirt.c | 6 +++--- + arch/x86/mm/init_64.c | 2 +- + arch/x86/mm/ioremap.c | 2 +- + arch/x86/mm/kmmio.c | 2 +- + arch/x86/mm/pgtable_32.c | 2 +- + arch/x86/mm/tlb.c | 6 +++--- + arch/x86/platform/uv/tlb_uv.c | 2 +- + arch/x86/xen/mmu_pv.c | 6 +++--- + include/trace/events/xen.h | 2 +- + 13 files changed, 39 insertions(+), 26 deletions(-) + +--- a/arch/x86/include/asm/paravirt.h ++++ b/arch/x86/include/asm/paravirt.h +@@ -297,9 +297,9 @@ static inline void __flush_tlb_global(vo + { + PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); + } +-static inline void __flush_tlb_single(unsigned long addr) ++static inline void __flush_tlb_one_user(unsigned long addr) + { +- PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); ++ PVOP_VCALL1(pv_mmu_ops.flush_tlb_one_user, addr); + } + + static inline void flush_tlb_others(const struct cpumask *cpumask, +--- a/arch/x86/include/asm/paravirt_types.h ++++ b/arch/x86/include/asm/paravirt_types.h +@@ -217,7 +217,7 @@ struct pv_mmu_ops { + /* TLB operations */ + void (*flush_tlb_user)(void); + void (*flush_tlb_kernel)(void); +- void (*flush_tlb_single)(unsigned long addr); ++ void (*flush_tlb_one_user)(unsigned long addr); + void (*flush_tlb_others)(const struct cpumask *cpus, + const struct flush_tlb_info *info); + +--- a/arch/x86/include/asm/pgtable_32.h ++++ b/arch/x86/include/asm/pgtable_32.h +@@ -61,7 +61,7 @@ void paging_init(void); + #define kpte_clear_flush(ptep, vaddr) \ + do { \ + pte_clear(&init_mm, (vaddr), (ptep)); \ +- __flush_tlb_one((vaddr)); \ ++ __flush_tlb_one_kernel((vaddr)); \ + } while (0) + + #endif /* !__ASSEMBLY__ */ +--- a/arch/x86/include/asm/tlbflush.h ++++ b/arch/x86/include/asm/tlbflush.h +@@ -140,7 +140,7 @@ static inline unsigned long build_cr3_no + #else + #define __flush_tlb() __native_flush_tlb() + #define __flush_tlb_global() __native_flush_tlb_global() +-#define __flush_tlb_single(addr) __native_flush_tlb_single(addr) ++#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr) + #endif + + static inline bool tlb_defer_switch_to_init_mm(void) +@@ -400,7 +400,7 @@ static inline void __native_flush_tlb_gl + /* + * flush one page in the user mapping + */ +-static inline void __native_flush_tlb_single(unsigned long addr) ++static inline void __native_flush_tlb_one_user(unsigned long addr) + { + u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); + +@@ -437,18 +437,31 @@ static inline void __flush_tlb_all(void) + /* + * flush one page in the kernel mapping + */ +-static inline void __flush_tlb_one(unsigned long addr) ++static inline void __flush_tlb_one_kernel(unsigned long addr) + { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); +- __flush_tlb_single(addr); ++ ++ /* ++ * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its ++ * paravirt equivalent. Even with PCID, this is sufficient: we only ++ * use PCID if we also use global PTEs for the kernel mapping, and ++ * INVLPG flushes global translations across all address spaces. ++ * ++ * If PTI is on, then the kernel is mapped with non-global PTEs, and ++ * __flush_tlb_one_user() will flush the given address for the current ++ * kernel address space and for its usermode counterpart, but it does ++ * not flush it for other address spaces. ++ */ ++ __flush_tlb_one_user(addr); + + if (!static_cpu_has(X86_FEATURE_PTI)) + return; + + /* +- * __flush_tlb_single() will have cleared the TLB entry for this ASID, +- * but since kernel space is replicated across all, we must also +- * invalidate all others. ++ * See above. We need to propagate the flush to all other address ++ * spaces. In principle, we only need to propagate it to kernelmode ++ * address spaces, but the extra bookkeeping we would need is not ++ * worth it. + */ + invalidate_other_asid(); + } +--- a/arch/x86/kernel/paravirt.c ++++ b/arch/x86/kernel/paravirt.c +@@ -200,9 +200,9 @@ static void native_flush_tlb_global(void + __native_flush_tlb_global(); + } + +-static void native_flush_tlb_single(unsigned long addr) ++static void native_flush_tlb_one_user(unsigned long addr) + { +- __native_flush_tlb_single(addr); ++ __native_flush_tlb_one_user(addr); + } + + struct static_key paravirt_steal_enabled; +@@ -401,7 +401,7 @@ struct pv_mmu_ops pv_mmu_ops __ro_after_ + + .flush_tlb_user = native_flush_tlb, + .flush_tlb_kernel = native_flush_tlb_global, +- .flush_tlb_single = native_flush_tlb_single, ++ .flush_tlb_one_user = native_flush_tlb_one_user, + .flush_tlb_others = native_flush_tlb_others, + + .pgd_alloc = __paravirt_pgd_alloc, +--- a/arch/x86/mm/init_64.c ++++ b/arch/x86/mm/init_64.c +@@ -256,7 +256,7 @@ static void __set_pte_vaddr(pud_t *pud, + * It's enough to flush this one mapping. + * (PGE mappings get flushed as well) + */ +- __flush_tlb_one(vaddr); ++ __flush_tlb_one_kernel(vaddr); + } + + void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte) +--- a/arch/x86/mm/ioremap.c ++++ b/arch/x86/mm/ioremap.c +@@ -820,5 +820,5 @@ void __init __early_set_fixmap(enum fixe + set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags)); + else + pte_clear(&init_mm, addr, pte); +- __flush_tlb_one(addr); ++ __flush_tlb_one_kernel(addr); + } +--- a/arch/x86/mm/kmmio.c ++++ b/arch/x86/mm/kmmio.c +@@ -168,7 +168,7 @@ static int clear_page_presence(struct km + return -1; + } + +- __flush_tlb_one(f->addr); ++ __flush_tlb_one_kernel(f->addr); + return 0; + } + +--- a/arch/x86/mm/pgtable_32.c ++++ b/arch/x86/mm/pgtable_32.c +@@ -63,7 +63,7 @@ void set_pte_vaddr(unsigned long vaddr, + * It's enough to flush this one mapping. + * (PGE mappings get flushed as well) + */ +- __flush_tlb_one(vaddr); ++ __flush_tlb_one_kernel(vaddr); + } + + unsigned long __FIXADDR_TOP = 0xfffff000; +--- a/arch/x86/mm/tlb.c ++++ b/arch/x86/mm/tlb.c +@@ -492,7 +492,7 @@ static void flush_tlb_func_common(const + * flush that changes context.tlb_gen from 2 to 3. If they get + * processed on this CPU in reverse order, we'll see + * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL. +- * If we were to use __flush_tlb_single() and set local_tlb_gen to ++ * If we were to use __flush_tlb_one_user() and set local_tlb_gen to + * 3, we'd be break the invariant: we'd update local_tlb_gen above + * 1 without the full flush that's needed for tlb_gen 2. + * +@@ -513,7 +513,7 @@ static void flush_tlb_func_common(const + + addr = f->start; + while (addr < f->end) { +- __flush_tlb_single(addr); ++ __flush_tlb_one_user(addr); + addr += PAGE_SIZE; + } + if (local) +@@ -660,7 +660,7 @@ static void do_kernel_range_flush(void * + + /* flush range by one by one 'invlpg' */ + for (addr = f->start; addr < f->end; addr += PAGE_SIZE) +- __flush_tlb_one(addr); ++ __flush_tlb_one_kernel(addr); + } + + void flush_tlb_kernel_range(unsigned long start, unsigned long end) +--- a/arch/x86/platform/uv/tlb_uv.c ++++ b/arch/x86/platform/uv/tlb_uv.c +@@ -299,7 +299,7 @@ static void bau_process_message(struct m + local_flush_tlb(); + stat->d_alltlb++; + } else { +- __flush_tlb_single(msg->address); ++ __flush_tlb_one_user(msg->address); + stat->d_onetlb++; + } + stat->d_requestee++; +--- a/arch/x86/xen/mmu_pv.c ++++ b/arch/x86/xen/mmu_pv.c +@@ -1300,12 +1300,12 @@ static void xen_flush_tlb(void) + preempt_enable(); + } + +-static void xen_flush_tlb_single(unsigned long addr) ++static void xen_flush_tlb_one_user(unsigned long addr) + { + struct mmuext_op *op; + struct multicall_space mcs; + +- trace_xen_mmu_flush_tlb_single(addr); ++ trace_xen_mmu_flush_tlb_one_user(addr); + + preempt_disable(); + +@@ -2370,7 +2370,7 @@ static const struct pv_mmu_ops xen_mmu_o + + .flush_tlb_user = xen_flush_tlb, + .flush_tlb_kernel = xen_flush_tlb, +- .flush_tlb_single = xen_flush_tlb_single, ++ .flush_tlb_one_user = xen_flush_tlb_one_user, + .flush_tlb_others = xen_flush_tlb_others, + + .pgd_alloc = xen_pgd_alloc, +--- a/include/trace/events/xen.h ++++ b/include/trace/events/xen.h +@@ -368,7 +368,7 @@ TRACE_EVENT(xen_mmu_flush_tlb, + TP_printk("%s", "") + ); + +-TRACE_EVENT(xen_mmu_flush_tlb_single, ++TRACE_EVENT(xen_mmu_flush_tlb_one_user, + TP_PROTO(unsigned long addr), + TP_ARGS(addr), + TP_STRUCT__entry( + + +Patches currently in stable-queue which might be from luto@kernel.org are + +queue-4.15/x86-entry-64-interleave-xor-register-clearing-with-push-instructions.patch +queue-4.15/x86-spectre-fix-an-error-message.patch +queue-4.15/x86-entry-64-merge-the-pop_c_regs-and-pop_extra_regs-macros-into-a-single-pop_regs-macro.patch +queue-4.15/x86-entry-64-remove-the-unused-icebp-macro.patch +queue-4.15/kvm-nvmx-set-the-cpu_based_use_msr_bitmaps-if-we-have-a-valid-l02-msr-bitmap.patch +queue-4.15/x86-nvmx-properly-set-spec_ctrl-and-pred_cmd-before-merging-msrs.patch +queue-4.15/x86-speculation-add-asm-msr-index.h-dependency.patch +queue-4.15/x86-entry-64-use-push_and_clean_regs-in-more-cases.patch +queue-4.15/selftests-x86-disable-tests-requiring-32-bit-support-on-pure-64-bit-systems.patch +queue-4.15/x86-debug-use-ud2-for-warn.patch +queue-4.15/x86-speculation-update-speculation-control-microcode-blacklist.patch +queue-4.15/x86-entry-64-clear-registers-for-exceptions-interrupts-to-reduce-speculation-attack-surface.patch +queue-4.15/x86-speculation-correct-speculation-control-microcode-blacklist-again.patch +queue-4.15/x86-entry-64-merge-save_c_regs-and-save_extra_regs-remove-unused-extensions.patch +queue-4.15/selftests-x86-do-not-rely-on-int-0x80-in-single_step_syscall.c.patch +queue-4.15/selftests-x86-fix-vdso-selftest-segfault-for-vsyscall-none.patch +queue-4.15/x86-debug-objtool-annotate-warn-related-ud2-as-reachable.patch +queue-4.15/objtool-fix-segfault-in-ignore_unreachable_insn.patch +queue-4.15/x86-entry-64-indent-push_and_clear_regs-and-pop_regs-properly.patch +queue-4.15/selftests-x86-pkeys-remove-unused-functions.patch +queue-4.15/selftests-x86-clean-up-and-document-sscanf-usage.patch +queue-4.15/x86-speculation-fix-up-array_index_nospec_mask-asm-constraint.patch +queue-4.15/x86-entry-64-clear-extra-registers-beyond-syscall-arguments-to-reduce-speculation-attack-surface.patch +queue-4.15/kvm-x86-reduce-retpoline-performance-impact-in-slot_handle_level_range-by-always-inlining-iterator-helper-methods.patch +queue-4.15/selftests-x86-do-not-rely-on-int-0x80-in-test_mremap_vdso.c.patch +queue-4.15/x86-mm-pti-fix-pti-comment-in-entry_syscall_64.patch +queue-4.15/x86-entry-64-get-rid-of-the-alloc_pt_gpregs_on_stack-and-save_and_clear_regs-macros.patch +queue-4.15/x86-speculation-clean-up-various-spectre-related-details.patch +queue-4.15/x86-entry-64-introduce-the-push_and_clean_regs-macro.patch +queue-4.15/revert-x86-speculation-simplify-indirect_branch_prediction_barrier.patch +queue-4.15/x86-entry-64-compat-clear-registers-for-compat-syscalls-to-reduce-speculation-attack-surface.patch +queue-4.15/x86-mm-rename-flush_tlb_single-and-flush_tlb_one-to-__flush_tlb_one_.patch +queue-4.15/x86-entry-64-fix-cr3-restore-in-paranoid_exit.patch + +-- +To unsubscribe, send a message with 'unsubscribe linux-mm' in +the body to majordomo@kvack.org. For more info on Linux MM, +see: http://www.linux-mm.org/ . +Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a> diff --git a/a/content_digest b/N1/content_digest index ad14f2d..6b6975b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,25 +2,25 @@ "Subject\0Patch \"x86/mm: Rename flush_tlb_single() and flush_tlb_one() to __flush_tlb_one_[user|kernel]()\" has been added to the 4.15-stable tree\0" "Date\0Tue, 20 Feb 2018 11:26:46 +0100\0" "To\0luto@kernel.org" - boris.ostrovsky@oracle.com - bp@alien8.de - brgerst@gmail.com - dave.hansen@intel.com - eduval@amazon.com - gregkh@linuxfoundation.org - hughd@google.com - jgross@suse.com - jpoimboe@redhat.com - keescook@google.com - linux-mm@kvack.org - mingo@kernel.org - peterz@infradead.org - riel@redhat.com - tglx@linutronix.de - torvalds@linux-foundation.org - " will.deacon@arm.com\0" - "Cc\0stable@vger.kernel.org" - " stable-commits@vger.kernel.org\0" + boris.ostrovsky@oracle.com + bp@alien8.de + brgerst@gmail.com + dave.hansen@intel.com + eduval@amazon.com + gregkh@linuxfoundation.org + hughd@google.com + jgross@suse.com + jpoimboe@redhat.com + keescook@google.com + linux-mm@kvack.org + mingo@kernel.org + peterz@infradead.org + riel@redhat.com + tglx@linutronix.de + torvalds@linux-foundation.org + "will.deacon@arm.com\0" + "Cc\0<stable@vger.kernel.org>" + " <stable-commits@vger.kernel.org>\0" "\00:1\0" "b\0" "\n" @@ -36,6 +36,341 @@ "and it can be found in the queue-4.15 subdirectory.\n" "\n" "If you, or anyone else, feels it should not be added to the stable tree,\n" - please let <stable@vger.kernel.org> know about it. + "please let <stable@vger.kernel.org> know about it.\n" + "\n" + "\n" + ">From 1299ef1d8870d2d9f09a5aadf2f8b2c887c2d033 Mon Sep 17 00:00:00 2001\n" + "From: Andy Lutomirski <luto@kernel.org>\n" + "Date: Wed, 31 Jan 2018 08:03:10 -0800\n" + "Subject: x86/mm: Rename flush_tlb_single() and flush_tlb_one() to __flush_tlb_one_[user|kernel]()\n" + "\n" + "From: Andy Lutomirski <luto@kernel.org>\n" + "\n" + "commit 1299ef1d8870d2d9f09a5aadf2f8b2c887c2d033 upstream.\n" + "\n" + "flush_tlb_single() and flush_tlb_one() sound almost identical, but\n" + "they really mean \"flush one user translation\" and \"flush one kernel\n" + "translation\". Rename them to flush_tlb_one_user() and\n" + "flush_tlb_one_kernel() to make the semantics more obvious.\n" + "\n" + "[ I was looking at some PTI-related code, and the flush-one-address code\n" + " is unnecessarily hard to understand because the names of the helpers are\n" + " uninformative. This came up during PTI review, but no one got around to\n" + " doing it. ]\n" + "\n" + "Signed-off-by: Andy Lutomirski <luto@kernel.org>\n" + "Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>\n" + "Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>\n" + "Cc: Borislav Petkov <bp@alien8.de>\n" + "Cc: Brian Gerst <brgerst@gmail.com>\n" + "Cc: Dave Hansen <dave.hansen@intel.com>\n" + "Cc: Eduardo Valentin <eduval@amazon.com>\n" + "Cc: Hugh Dickins <hughd@google.com>\n" + "Cc: Josh Poimboeuf <jpoimboe@redhat.com>\n" + "Cc: Juergen Gross <jgross@suse.com>\n" + "Cc: Kees Cook <keescook@google.com>\n" + "Cc: Linus Torvalds <torvalds@linux-foundation.org>\n" + "Cc: Linux-MM <linux-mm@kvack.org>\n" + "Cc: Rik van Riel <riel@redhat.com>\n" + "Cc: Thomas Gleixner <tglx@linutronix.de>\n" + "Cc: Will Deacon <will.deacon@arm.com>\n" + "Link: http://lkml.kernel.org/r/3303b02e3c3d049dc5235d5651e0ae6d29a34354.1517414378.git.luto@kernel.org\n" + "Signed-off-by: Ingo Molnar <mingo@kernel.org>\n" + "Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n" + "\n" + "---\n" + " arch/x86/include/asm/paravirt.h | 4 ++--\n" + " arch/x86/include/asm/paravirt_types.h | 2 +-\n" + " arch/x86/include/asm/pgtable_32.h | 2 +-\n" + " arch/x86/include/asm/tlbflush.h | 27 ++++++++++++++++++++-------\n" + " arch/x86/kernel/paravirt.c | 6 +++---\n" + " arch/x86/mm/init_64.c | 2 +-\n" + " arch/x86/mm/ioremap.c | 2 +-\n" + " arch/x86/mm/kmmio.c | 2 +-\n" + " arch/x86/mm/pgtable_32.c | 2 +-\n" + " arch/x86/mm/tlb.c | 6 +++---\n" + " arch/x86/platform/uv/tlb_uv.c | 2 +-\n" + " arch/x86/xen/mmu_pv.c | 6 +++---\n" + " include/trace/events/xen.h | 2 +-\n" + " 13 files changed, 39 insertions(+), 26 deletions(-)\n" + "\n" + "--- a/arch/x86/include/asm/paravirt.h\n" + "+++ b/arch/x86/include/asm/paravirt.h\n" + "@@ -297,9 +297,9 @@ static inline void __flush_tlb_global(vo\n" + " {\n" + " \tPVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);\n" + " }\n" + "-static inline void __flush_tlb_single(unsigned long addr)\n" + "+static inline void __flush_tlb_one_user(unsigned long addr)\n" + " {\n" + "-\tPVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);\n" + "+\tPVOP_VCALL1(pv_mmu_ops.flush_tlb_one_user, addr);\n" + " }\n" + " \n" + " static inline void flush_tlb_others(const struct cpumask *cpumask,\n" + "--- a/arch/x86/include/asm/paravirt_types.h\n" + "+++ b/arch/x86/include/asm/paravirt_types.h\n" + "@@ -217,7 +217,7 @@ struct pv_mmu_ops {\n" + " \t/* TLB operations */\n" + " \tvoid (*flush_tlb_user)(void);\n" + " \tvoid (*flush_tlb_kernel)(void);\n" + "-\tvoid (*flush_tlb_single)(unsigned long addr);\n" + "+\tvoid (*flush_tlb_one_user)(unsigned long addr);\n" + " \tvoid (*flush_tlb_others)(const struct cpumask *cpus,\n" + " \t\t\t\t const struct flush_tlb_info *info);\n" + " \n" + "--- a/arch/x86/include/asm/pgtable_32.h\n" + "+++ b/arch/x86/include/asm/pgtable_32.h\n" + "@@ -61,7 +61,7 @@ void paging_init(void);\n" + " #define kpte_clear_flush(ptep, vaddr)\t\t\\\n" + " do {\t\t\t\t\t\t\\\n" + " \tpte_clear(&init_mm, (vaddr), (ptep));\t\\\n" + "-\t__flush_tlb_one((vaddr));\t\t\\\n" + "+\t__flush_tlb_one_kernel((vaddr));\t\t\\\n" + " } while (0)\n" + " \n" + " #endif /* !__ASSEMBLY__ */\n" + "--- a/arch/x86/include/asm/tlbflush.h\n" + "+++ b/arch/x86/include/asm/tlbflush.h\n" + "@@ -140,7 +140,7 @@ static inline unsigned long build_cr3_no\n" + " #else\n" + " #define __flush_tlb() __native_flush_tlb()\n" + " #define __flush_tlb_global() __native_flush_tlb_global()\n" + "-#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)\n" + "+#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)\n" + " #endif\n" + " \n" + " static inline bool tlb_defer_switch_to_init_mm(void)\n" + "@@ -400,7 +400,7 @@ static inline void __native_flush_tlb_gl\n" + " /*\n" + " * flush one page in the user mapping\n" + " */\n" + "-static inline void __native_flush_tlb_single(unsigned long addr)\n" + "+static inline void __native_flush_tlb_one_user(unsigned long addr)\n" + " {\n" + " \tu32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);\n" + " \n" + "@@ -437,18 +437,31 @@ static inline void __flush_tlb_all(void)\n" + " /*\n" + " * flush one page in the kernel mapping\n" + " */\n" + "-static inline void __flush_tlb_one(unsigned long addr)\n" + "+static inline void __flush_tlb_one_kernel(unsigned long addr)\n" + " {\n" + " \tcount_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);\n" + "-\t__flush_tlb_single(addr);\n" + "+\n" + "+\t/*\n" + "+\t * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its\n" + "+\t * paravirt equivalent. Even with PCID, this is sufficient: we only\n" + "+\t * use PCID if we also use global PTEs for the kernel mapping, and\n" + "+\t * INVLPG flushes global translations across all address spaces.\n" + "+\t *\n" + "+\t * If PTI is on, then the kernel is mapped with non-global PTEs, and\n" + "+\t * __flush_tlb_one_user() will flush the given address for the current\n" + "+\t * kernel address space and for its usermode counterpart, but it does\n" + "+\t * not flush it for other address spaces.\n" + "+\t */\n" + "+\t__flush_tlb_one_user(addr);\n" + " \n" + " \tif (!static_cpu_has(X86_FEATURE_PTI))\n" + " \t\treturn;\n" + " \n" + " \t/*\n" + "-\t * __flush_tlb_single() will have cleared the TLB entry for this ASID,\n" + "-\t * but since kernel space is replicated across all, we must also\n" + "-\t * invalidate all others.\n" + "+\t * See above. We need to propagate the flush to all other address\n" + "+\t * spaces. In principle, we only need to propagate it to kernelmode\n" + "+\t * address spaces, but the extra bookkeeping we would need is not\n" + "+\t * worth it.\n" + " \t */\n" + " \tinvalidate_other_asid();\n" + " }\n" + "--- a/arch/x86/kernel/paravirt.c\n" + "+++ b/arch/x86/kernel/paravirt.c\n" + "@@ -200,9 +200,9 @@ static void native_flush_tlb_global(void\n" + " \t__native_flush_tlb_global();\n" + " }\n" + " \n" + "-static void native_flush_tlb_single(unsigned long addr)\n" + "+static void native_flush_tlb_one_user(unsigned long addr)\n" + " {\n" + "-\t__native_flush_tlb_single(addr);\n" + "+\t__native_flush_tlb_one_user(addr);\n" + " }\n" + " \n" + " struct static_key paravirt_steal_enabled;\n" + "@@ -401,7 +401,7 @@ struct pv_mmu_ops pv_mmu_ops __ro_after_\n" + " \n" + " \t.flush_tlb_user = native_flush_tlb,\n" + " \t.flush_tlb_kernel = native_flush_tlb_global,\n" + "-\t.flush_tlb_single = native_flush_tlb_single,\n" + "+\t.flush_tlb_one_user = native_flush_tlb_one_user,\n" + " \t.flush_tlb_others = native_flush_tlb_others,\n" + " \n" + " \t.pgd_alloc = __paravirt_pgd_alloc,\n" + "--- a/arch/x86/mm/init_64.c\n" + "+++ b/arch/x86/mm/init_64.c\n" + "@@ -256,7 +256,7 @@ static void __set_pte_vaddr(pud_t *pud,\n" + " \t * It's enough to flush this one mapping.\n" + " \t * (PGE mappings get flushed as well)\n" + " \t */\n" + "-\t__flush_tlb_one(vaddr);\n" + "+\t__flush_tlb_one_kernel(vaddr);\n" + " }\n" + " \n" + " void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte)\n" + "--- a/arch/x86/mm/ioremap.c\n" + "+++ b/arch/x86/mm/ioremap.c\n" + "@@ -820,5 +820,5 @@ void __init __early_set_fixmap(enum fixe\n" + " \t\tset_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));\n" + " \telse\n" + " \t\tpte_clear(&init_mm, addr, pte);\n" + "-\t__flush_tlb_one(addr);\n" + "+\t__flush_tlb_one_kernel(addr);\n" + " }\n" + "--- a/arch/x86/mm/kmmio.c\n" + "+++ b/arch/x86/mm/kmmio.c\n" + "@@ -168,7 +168,7 @@ static int clear_page_presence(struct km\n" + " \t\treturn -1;\n" + " \t}\n" + " \n" + "-\t__flush_tlb_one(f->addr);\n" + "+\t__flush_tlb_one_kernel(f->addr);\n" + " \treturn 0;\n" + " }\n" + " \n" + "--- a/arch/x86/mm/pgtable_32.c\n" + "+++ b/arch/x86/mm/pgtable_32.c\n" + "@@ -63,7 +63,7 @@ void set_pte_vaddr(unsigned long vaddr,\n" + " \t * It's enough to flush this one mapping.\n" + " \t * (PGE mappings get flushed as well)\n" + " \t */\n" + "-\t__flush_tlb_one(vaddr);\n" + "+\t__flush_tlb_one_kernel(vaddr);\n" + " }\n" + " \n" + " unsigned long __FIXADDR_TOP = 0xfffff000;\n" + "--- a/arch/x86/mm/tlb.c\n" + "+++ b/arch/x86/mm/tlb.c\n" + "@@ -492,7 +492,7 @@ static void flush_tlb_func_common(const\n" + " \t * flush that changes context.tlb_gen from 2 to 3. If they get\n" + " \t * processed on this CPU in reverse order, we'll see\n" + " \t * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.\n" + "-\t * If we were to use __flush_tlb_single() and set local_tlb_gen to\n" + "+\t * If we were to use __flush_tlb_one_user() and set local_tlb_gen to\n" + " \t * 3, we'd be break the invariant: we'd update local_tlb_gen above\n" + " \t * 1 without the full flush that's needed for tlb_gen 2.\n" + " \t *\n" + "@@ -513,7 +513,7 @@ static void flush_tlb_func_common(const\n" + " \n" + " \t\taddr = f->start;\n" + " \t\twhile (addr < f->end) {\n" + "-\t\t\t__flush_tlb_single(addr);\n" + "+\t\t\t__flush_tlb_one_user(addr);\n" + " \t\t\taddr += PAGE_SIZE;\n" + " \t\t}\n" + " \t\tif (local)\n" + "@@ -660,7 +660,7 @@ static void do_kernel_range_flush(void *\n" + " \n" + " \t/* flush range by one by one 'invlpg' */\n" + " \tfor (addr = f->start; addr < f->end; addr += PAGE_SIZE)\n" + "-\t\t__flush_tlb_one(addr);\n" + "+\t\t__flush_tlb_one_kernel(addr);\n" + " }\n" + " \n" + " void flush_tlb_kernel_range(unsigned long start, unsigned long end)\n" + "--- a/arch/x86/platform/uv/tlb_uv.c\n" + "+++ b/arch/x86/platform/uv/tlb_uv.c\n" + "@@ -299,7 +299,7 @@ static void bau_process_message(struct m\n" + " \t\tlocal_flush_tlb();\n" + " \t\tstat->d_alltlb++;\n" + " \t} else {\n" + "-\t\t__flush_tlb_single(msg->address);\n" + "+\t\t__flush_tlb_one_user(msg->address);\n" + " \t\tstat->d_onetlb++;\n" + " \t}\n" + " \tstat->d_requestee++;\n" + "--- a/arch/x86/xen/mmu_pv.c\n" + "+++ b/arch/x86/xen/mmu_pv.c\n" + "@@ -1300,12 +1300,12 @@ static void xen_flush_tlb(void)\n" + " \tpreempt_enable();\n" + " }\n" + " \n" + "-static void xen_flush_tlb_single(unsigned long addr)\n" + "+static void xen_flush_tlb_one_user(unsigned long addr)\n" + " {\n" + " \tstruct mmuext_op *op;\n" + " \tstruct multicall_space mcs;\n" + " \n" + "-\ttrace_xen_mmu_flush_tlb_single(addr);\n" + "+\ttrace_xen_mmu_flush_tlb_one_user(addr);\n" + " \n" + " \tpreempt_disable();\n" + " \n" + "@@ -2370,7 +2370,7 @@ static const struct pv_mmu_ops xen_mmu_o\n" + " \n" + " \t.flush_tlb_user = xen_flush_tlb,\n" + " \t.flush_tlb_kernel = xen_flush_tlb,\n" + "-\t.flush_tlb_single = xen_flush_tlb_single,\n" + "+\t.flush_tlb_one_user = xen_flush_tlb_one_user,\n" + " \t.flush_tlb_others = xen_flush_tlb_others,\n" + " \n" + " \t.pgd_alloc = xen_pgd_alloc,\n" + "--- a/include/trace/events/xen.h\n" + "+++ b/include/trace/events/xen.h\n" + "@@ -368,7 +368,7 @@ TRACE_EVENT(xen_mmu_flush_tlb,\n" + " \t TP_printk(\"%s\", \"\")\n" + " \t);\n" + " \n" + "-TRACE_EVENT(xen_mmu_flush_tlb_single,\n" + "+TRACE_EVENT(xen_mmu_flush_tlb_one_user,\n" + " \t TP_PROTO(unsigned long addr),\n" + " \t TP_ARGS(addr),\n" + " \t TP_STRUCT__entry(\n" + "\n" + "\n" + "Patches currently in stable-queue which might be from luto@kernel.org are\n" + "\n" + "queue-4.15/x86-entry-64-interleave-xor-register-clearing-with-push-instructions.patch\n" + "queue-4.15/x86-spectre-fix-an-error-message.patch\n" + "queue-4.15/x86-entry-64-merge-the-pop_c_regs-and-pop_extra_regs-macros-into-a-single-pop_regs-macro.patch\n" + "queue-4.15/x86-entry-64-remove-the-unused-icebp-macro.patch\n" + "queue-4.15/kvm-nvmx-set-the-cpu_based_use_msr_bitmaps-if-we-have-a-valid-l02-msr-bitmap.patch\n" + "queue-4.15/x86-nvmx-properly-set-spec_ctrl-and-pred_cmd-before-merging-msrs.patch\n" + "queue-4.15/x86-speculation-add-asm-msr-index.h-dependency.patch\n" + "queue-4.15/x86-entry-64-use-push_and_clean_regs-in-more-cases.patch\n" + "queue-4.15/selftests-x86-disable-tests-requiring-32-bit-support-on-pure-64-bit-systems.patch\n" + "queue-4.15/x86-debug-use-ud2-for-warn.patch\n" + "queue-4.15/x86-speculation-update-speculation-control-microcode-blacklist.patch\n" + "queue-4.15/x86-entry-64-clear-registers-for-exceptions-interrupts-to-reduce-speculation-attack-surface.patch\n" + "queue-4.15/x86-speculation-correct-speculation-control-microcode-blacklist-again.patch\n" + "queue-4.15/x86-entry-64-merge-save_c_regs-and-save_extra_regs-remove-unused-extensions.patch\n" + "queue-4.15/selftests-x86-do-not-rely-on-int-0x80-in-single_step_syscall.c.patch\n" + "queue-4.15/selftests-x86-fix-vdso-selftest-segfault-for-vsyscall-none.patch\n" + "queue-4.15/x86-debug-objtool-annotate-warn-related-ud2-as-reachable.patch\n" + "queue-4.15/objtool-fix-segfault-in-ignore_unreachable_insn.patch\n" + "queue-4.15/x86-entry-64-indent-push_and_clear_regs-and-pop_regs-properly.patch\n" + "queue-4.15/selftests-x86-pkeys-remove-unused-functions.patch\n" + "queue-4.15/selftests-x86-clean-up-and-document-sscanf-usage.patch\n" + "queue-4.15/x86-speculation-fix-up-array_index_nospec_mask-asm-constraint.patch\n" + "queue-4.15/x86-entry-64-clear-extra-registers-beyond-syscall-arguments-to-reduce-speculation-attack-surface.patch\n" + "queue-4.15/kvm-x86-reduce-retpoline-performance-impact-in-slot_handle_level_range-by-always-inlining-iterator-helper-methods.patch\n" + "queue-4.15/selftests-x86-do-not-rely-on-int-0x80-in-test_mremap_vdso.c.patch\n" + "queue-4.15/x86-mm-pti-fix-pti-comment-in-entry_syscall_64.patch\n" + "queue-4.15/x86-entry-64-get-rid-of-the-alloc_pt_gpregs_on_stack-and-save_and_clear_regs-macros.patch\n" + "queue-4.15/x86-speculation-clean-up-various-spectre-related-details.patch\n" + "queue-4.15/x86-entry-64-introduce-the-push_and_clean_regs-macro.patch\n" + "queue-4.15/revert-x86-speculation-simplify-indirect_branch_prediction_barrier.patch\n" + "queue-4.15/x86-entry-64-compat-clear-registers-for-compat-syscalls-to-reduce-speculation-attack-surface.patch\n" + "queue-4.15/x86-mm-rename-flush_tlb_single-and-flush_tlb_one-to-__flush_tlb_one_.patch\n" + "queue-4.15/x86-entry-64-fix-cr3-restore-in-paranoid_exit.patch\n" + "\n" + "--\n" + "To unsubscribe, send a message with 'unsubscribe linux-mm' in\n" + "the body to majordomo@kvack.org. For more info on Linux MM,\n" + "see: http://www.linux-mm.org/ .\n" + "Don't email: <a href=mailto:\"dont@kvack.org\"> email@kvack.org </a>" -0c2aed28f24d4a52b37210250788d996fc8720c7edd855732cb3d736207e59cf +179b61c3f329bfde3ea95733fe0f0ac7000e9607be308bc25bb1c6dc02246f35
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.