diff for duplicates of <1519943658.4592.34.camel@kernel.crashing.org> diff --git a/a/1.txt b/N1/1.txt index 39a2c80..1b8c939 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -43,3 +43,7 @@ things fit with a bit of wrangling. > So you can disable caching for memory, but I'm pretty sure you can't > enable caching for PCIe at least in the common case. At best you can > affect how the store buffer works for PCIe. +_______________________________________________ +Linux-nvdimm mailing list +Linux-nvdimm@lists.01.org +https://lists.01.org/mailman/listinfo/linux-nvdimm diff --git a/a/content_digest b/N1/content_digest index d59492e..d5b28eb 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -11,25 +11,21 @@ "Subject\0Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory\0" "Date\0Fri, 02 Mar 2018 09:34:18 +1100\0" "To\0Linus Torvalds <torvalds@linux-foundation.org>\0" - "Cc\0Jason Gunthorpe <jgg@ziepe.ca>" - Dan Williams <dan.j.williams@intel.com> - Logan Gunthorpe <logang@deltatee.com> - Linux Kernel Mailing List <linux-kernel@vger.kernel.org> + "Cc\0Jens Axboe <axboe@kernel.dk>" + Keith Busch <keith.busch@intel.com> + Oliver OHalloran <oliveroh@au1.ibm.com> + Alex Williamson <alex.williamson@redhat.com> + linux-nvdimm <linux-nvdimm@lists.01.org> + linux-rdma <linux-rdma@vger.kernel.org> linux-pci@vger.kernel.org + Linux Kernel Mailing List <linux-kernel@vger.kernel.org> linux-nvme <linux-nvme@lists.infradead.org> - linux-rdma <linux-rdma@vger.kernel.org> - linux-nvdimm <linux-nvdimm@lists.01.org> linux-block <linux-block@vger.kernel.org> - Stephen Bates <sbates@raithlin.com> - Christoph Hellwig <hch@lst.de> - Jens Axboe <axboe@kernel.dk> - Keith Busch <keith.busch@intel.com> - Sagi Grimberg <sagi@grimberg.me> + Jason Gunthorpe <jgg@ziepe.ca> + " J\303\251r\303\264me Glisse <jglisse@redhat.com>" Bjorn Helgaas <bhelgaas@google.com> Max Gurtovoy <maxg@mellanox.com> - " J\303\251r\303\264me Glisse <jglisse@redhat.com>" - Alex Williamson <alex.williamson@redhat.com> - " Oliver OHalloran <oliveroh@au1.ibm.com>\0" + " Christoph Hellwig <hch@lst.de>\0" "\00:1\0" "b\0" "On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote:\n" @@ -76,6 +72,10 @@ "> \n" "> So you can disable caching for memory, but I'm pretty sure you can't\n" "> enable caching for PCIe at least in the common case. At best you can\n" - > affect how the store buffer works for PCIe. + "> affect how the store buffer works for PCIe.\n" + "_______________________________________________\n" + "Linux-nvdimm mailing list\n" + "Linux-nvdimm@lists.01.org\n" + https://lists.01.org/mailman/listinfo/linux-nvdimm -22dd78bd1a3577de1fba45d70cf1b135c335fc12b108910da2f656105bfc4e6b +a5f0ebca8b9ff8ef9055a49a6cf35888bfd0a94d58031ff9135307a4d3d2f9c8
diff --git a/a/1.txt b/N2/1.txt index 39a2c80..6da8dba 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,5 +1,5 @@ -On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote: -> On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote: +On Thu, 2018-03-01@14:31 -0800, Linus Torvalds wrote: +> On Thu, Mar 1, 2018@2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote: > > > > Could be that x86 has the smarts to do the right thing, still trying to > > untangle the code :-) diff --git a/a/content_digest b/N2/content_digest index d59492e..cc701a6 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -7,33 +7,13 @@ "ref\020180301205315.GJ19007@ziepe.ca\0" "ref\01519942012.4592.31.camel@au1.ibm.com\0" "ref\0CA+55aFy-oAiFJ3WDx4giR1enj65y-YJnZZhY6geFw0ygFyKXfQ@mail.gmail.com\0" - "From\0Benjamin Herrenschmidt <benh@kernel.crashing.org>\0" - "Subject\0Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory\0" + "From\0benh@kernel.crashing.org (Benjamin Herrenschmidt)\0" + "Subject\0[PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory\0" "Date\0Fri, 02 Mar 2018 09:34:18 +1100\0" - "To\0Linus Torvalds <torvalds@linux-foundation.org>\0" - "Cc\0Jason Gunthorpe <jgg@ziepe.ca>" - Dan Williams <dan.j.williams@intel.com> - Logan Gunthorpe <logang@deltatee.com> - Linux Kernel Mailing List <linux-kernel@vger.kernel.org> - linux-pci@vger.kernel.org - linux-nvme <linux-nvme@lists.infradead.org> - linux-rdma <linux-rdma@vger.kernel.org> - linux-nvdimm <linux-nvdimm@lists.01.org> - linux-block <linux-block@vger.kernel.org> - Stephen Bates <sbates@raithlin.com> - Christoph Hellwig <hch@lst.de> - Jens Axboe <axboe@kernel.dk> - Keith Busch <keith.busch@intel.com> - Sagi Grimberg <sagi@grimberg.me> - Bjorn Helgaas <bhelgaas@google.com> - Max Gurtovoy <maxg@mellanox.com> - " J\303\251r\303\264me Glisse <jglisse@redhat.com>" - Alex Williamson <alex.williamson@redhat.com> - " Oliver OHalloran <oliveroh@au1.ibm.com>\0" "\00:1\0" "b\0" - "On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote:\n" - "> On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote:\n" + "On Thu, 2018-03-01@14:31 -0800, Linus Torvalds wrote:\n" + "> On Thu, Mar 1, 2018@2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote:\n" "> > \n" "> > Could be that x86 has the smarts to do the right thing, still trying to\n" "> > untangle the code :-)\n" @@ -78,4 +58,4 @@ "> enable caching for PCIe at least in the common case. At best you can\n" > affect how the store buffer works for PCIe. -22dd78bd1a3577de1fba45d70cf1b135c335fc12b108910da2f656105bfc4e6b +dd231c4af6866069d5d65973de5a3afc63b67303bdbc812e18ca1bb493338ee7
diff --git a/a/1.txt b/N3/1.txt index 39a2c80..f6d6e23 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,5 +1,5 @@ On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote: -> On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote: +> On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org> wrote: > > > > Could be that x86 has the smarts to do the right thing, still trying to > > untangle the code :-) diff --git a/a/content_digest b/N3/content_digest index d59492e..5a0de94 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -7,33 +7,30 @@ "ref\020180301205315.GJ19007@ziepe.ca\0" "ref\01519942012.4592.31.camel@au1.ibm.com\0" "ref\0CA+55aFy-oAiFJ3WDx4giR1enj65y-YJnZZhY6geFw0ygFyKXfQ@mail.gmail.com\0" - "From\0Benjamin Herrenschmidt <benh@kernel.crashing.org>\0" + "ref\0CA+55aFy-oAiFJ3WDx4giR1enj65y-YJnZZhY6geFw0ygFyKXfQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>\0" "Subject\0Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory\0" "Date\0Fri, 02 Mar 2018 09:34:18 +1100\0" - "To\0Linus Torvalds <torvalds@linux-foundation.org>\0" - "Cc\0Jason Gunthorpe <jgg@ziepe.ca>" - Dan Williams <dan.j.williams@intel.com> - Logan Gunthorpe <logang@deltatee.com> - Linux Kernel Mailing List <linux-kernel@vger.kernel.org> - linux-pci@vger.kernel.org - linux-nvme <linux-nvme@lists.infradead.org> - linux-rdma <linux-rdma@vger.kernel.org> - linux-nvdimm <linux-nvdimm@lists.01.org> - linux-block <linux-block@vger.kernel.org> - Stephen Bates <sbates@raithlin.com> - Christoph Hellwig <hch@lst.de> - Jens Axboe <axboe@kernel.dk> - Keith Busch <keith.busch@intel.com> - Sagi Grimberg <sagi@grimberg.me> - Bjorn Helgaas <bhelgaas@google.com> - Max Gurtovoy <maxg@mellanox.com> - " J\303\251r\303\264me Glisse <jglisse@redhat.com>" - Alex Williamson <alex.williamson@redhat.com> - " Oliver OHalloran <oliveroh@au1.ibm.com>\0" + "To\0Linus Torvalds <torvalds-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org>\0" + "Cc\0Jens Axboe <axboe-tSWWG44O7X1aa/9Udqfwiw@public.gmane.org>" + Keith Busch <keith.busch-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> + Oliver OHalloran <oliveroh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org> + Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> + linux-nvdimm <linux-nvdimm-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org> + linux-rdma <linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Linux Kernel Mailing List <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-nvme <linux-nvme-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + linux-block <linux-block-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + Jason Gunthorpe <jgg-uk2M96/98Pc@public.gmane.org> + " J\303\251r\303\264me Glisse <jglisse-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>" + Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> + Max Gurtovoy <maxg-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org> + " Christoph Hellwig <hch-jcswGhMUV9g@public.gmane.org>\0" "\00:1\0" "b\0" "On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote:\n" - "> On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote:\n" + "> On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org> wrote:\n" "> > \n" "> > Could be that x86 has the smarts to do the right thing, still trying to\n" "> > untangle the code :-)\n" @@ -78,4 +75,4 @@ "> enable caching for PCIe at least in the common case. At best you can\n" > affect how the store buffer works for PCIe. -22dd78bd1a3577de1fba45d70cf1b135c335fc12b108910da2f656105bfc4e6b +f290d7f5468684e3368ef8d3c7b2ab4c8ba9955567f80d5e1232a94122e4d58a
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