Re: [PATCH v7 04/10] cxl: Defer dport allocation for switch ports

[Dave Jiang <dave.jiang@intel.com>]

On 7/22/25 8:50 AM, dan.j.williams@intel.com wrote:

<--snip-->

>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index 3f1695c96abc..de7883747555 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -403,6 +403,7 @@ struct cxl_endpoint_decoder {
>>   * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
>>   * @cxld: base cxl_decoder object
>>   * @nr_targets: number of elements in @target
>> + * @target_map: map of target dport ids to interleave positions
>>   * @target: active ordered target list in current decoder configuration
>>   *
>>   * The 'switch' decoder type represents the decoder instances of cxl_port's that
>> @@ -414,6 +415,7 @@ struct cxl_endpoint_decoder {
>>  struct cxl_switch_decoder {
>>  	struct cxl_decoder cxld;
>>  	int nr_targets;
>> +	int target_map[CXL_DECODER_MAX_INTERLEAVE];
> 
> This can save space by being a u8 since hardware port ids are 8-bits.
> 
> I would do a lead-in patch to introduce this and drop the @target_map
> argument to cxl_decoder_add() and its helpers.
> 
> It might help to clarify somewhere that this is a cached copy of the
> hardware port-id list and that it is available at init even before all
> @dport objects have been discovered / instantiated.
> 

This actually needs to be u32 and cannot be u8. Mainly because CFMWS interleave targets is 4 bytes. And if we set this to u8, it'll break things later on when we do region decoder matching for the root port (took couple days for me to chase that on hardware).