From mboxrd@z Thu Jan 1 00:00:00 1970 From: yannick fertre Subject: [PATCH v2 04/10] video: add support of panel OTM8009A Date: Fri, 2 Mar 2018 16:44:05 +0100 Message-ID: <1520005451-23217-5-git-send-email-yannick.fertre@st.com> References: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 09A316E181 for ; Fri, 2 Mar 2018 15:44:36 +0000 (UTC) In-Reply-To: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Vikas Manocha , Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Patrice Chotard , Patrick DELAUNAY , Christophe KERELLO , Archit Taneja , Andrzej Hajda , Laurent Pinchart , David Airlie , Brian Norris , Bhumika Goyal , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Albert Aribaud , Simon Glass , Anatolij Gustschin , Thierry Reding Cc: u-boot@lists.denx.de, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org U3VwcG9ydCBmb3IgT3Jpc2UgVGVjaCBvdG04MDA5YSA0ODBwIGRzaSAyZGwgdmlkZW8gbW9kZSBw YW5lbC4KClNpZ25lZC1vZmYtYnk6IHlhbm5pY2sgZmVydHJlIDx5YW5uaWNrLmZlcnRyZUBzdC5j b20+Ci0tLQogZHJpdmVycy92aWRlby9LY29uZmlnICAgICAgICAgICAgICB8ICAgOCArCiBkcml2 ZXJzL3ZpZGVvL01ha2VmaWxlICAgICAgICAgICAgIHwgICAxICsKIGRyaXZlcnMvdmlkZW8vb3Jp c2V0ZWNoX290bTgwMDlhLmMgfCAzMjkgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKwogMyBmaWxlcyBjaGFuZ2VkLCAzMzggaW5zZXJ0aW9ucygrKQogY3JlYXRlIG1vZGUgMTAw NjQ0IGRyaXZlcnMvdmlkZW8vb3Jpc2V0ZWNoX290bTgwMDlhLmMKCmRpZmYgLS1naXQgYS9kcml2 ZXJzL3ZpZGVvL0tjb25maWcgYi9kcml2ZXJzL3ZpZGVvL0tjb25maWcKaW5kZXggMTk4MTI5OC4u YjVmYzUzNSAxMDA2NDQKLS0tIGEvZHJpdmVycy92aWRlby9LY29uZmlnCisrKyBiL2RyaXZlcnMv dmlkZW8vS2NvbmZpZwpAQCAtMzIwLDYgKzMyMCwxNCBAQCBjb25maWcgVklERU9fTENEX0FOWDk4 MDQKIAlmcm9tIGEgcGFyYWxsZWwgTENEIGludGVyZmFjZSBhbmQgdHJhbnNsYXRlIGl0IG9uIHRo ZSBmeSBpbnRvIGEgRFAKIAlpbnRlcmZhY2UgZm9yIGRyaXZpbmcgZURQIFRGVCBkaXNwbGF5cy4g SXQgdXNlcyBJMkMgZm9yIGNvbmZpZ3VyYXRpb24uCiAKK2NvbmZpZyBWSURFT19MQ0RfT1JJU0VU RUNIX09UTTgwMDlBCisJYm9vbCAiT1RNODAwOUEgRFNJIExDRCBwYW5lbCBzdXBwb3J0IgorCWRl cGVuZHMgb24gRE1fVklERU8KKwlzZWxlY3QgVklERU9fTUlQSV9EU0kKKwlkZWZhdWx0IG4KKwkt LS1oZWxwLS0tCisJU3VwcG9ydCBmb3IgT3Jpc2UgVGVjaCBvdG04MDA5YSA0ODBwIGRzaSAyZGwg dmlkZW8gbW9kZSBwYW5lbC4KKwogY29uZmlnIFZJREVPX0xDRF9TU0QyODI4CiAJYm9vbCAiU1NE MjgyOCBicmlkZ2UgY2hpcCIKIAlkZWZhdWx0IG4KZGlmZiAtLWdpdCBhL2RyaXZlcnMvdmlkZW8v TWFrZWZpbGUgYi9kcml2ZXJzL3ZpZGVvL01ha2VmaWxlCmluZGV4IDZmNDJjY2EuLjY1MDAyYWYg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvdmlkZW8vTWFrZWZpbGUKKysrIGIvZHJpdmVycy92aWRlby9N YWtlZmlsZQpAQCAtMzcsNiArMzcsNyBAQCBvYmotJChDT05GSUdfVklERU9fQ09SRUJPT1QpICs9 IGNvcmVib290Lm8KIG9iai0kKENPTkZJR19WSURFT19EQThYWCkgKz0gZGE4eHgtZmIubyB2aWRl b21vZGVzLm8KIG9iai0kKENPTkZJR19WSURFT19MQ0RfQU5YOTgwNCkgKz0gYW54OTgwNC5vCiBv YmotJChDT05GSUdfVklERU9fTENEX0hJVEFDSElfVFgxOEQ0MlZNKSArPSBoaXRhY2hpX3R4MThk NDJ2bV9sY2Qubworb2JqLSQoQ09ORklHX1ZJREVPX0xDRF9PUklTRVRFQ0hfT1RNODAwOUEpICs9 IG9yaXNldGVjaF9vdG04MDA5YS5vCiBvYmotJChDT05GSUdfVklERU9fTENEX1NTRDI4MjgpICs9 IHNzZDI4Mjgubwogb2JqLSQoQ09ORklHX1ZJREVPX01CODYyeHgpICs9IG1iODYyeHgubyB2aWRl b21vZGVzLm8KIG9iai0kKENPTkZJR19WSURFT19NWDMpICs9IG14M2ZiLm8gdmlkZW9tb2Rlcy5v CmRpZmYgLS1naXQgYS9kcml2ZXJzL3ZpZGVvL29yaXNldGVjaF9vdG04MDA5YS5jIGIvZHJpdmVy cy92aWRlby9vcmlzZXRlY2hfb3RtODAwOWEuYwpuZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAw MDAwMDAwLi43OWYyZGE4Ci0tLSAvZGV2L251bGwKKysrIGIvZHJpdmVycy92aWRlby9vcmlzZXRl Y2hfb3RtODAwOWEuYwpAQCAtMCwwICsxLDMyOSBAQAorLyoKKyAqIENvcHlyaWdodCAoQykgMjAx OCBTVE1pY3JvZWxlY3Ryb25pY3MgLSBBbGwgUmlnaHRzIFJlc2VydmVkCisgKiBBdXRob3Iocyk6 IFlhbm5pY2sgRmVydHJlIDx5YW5uaWNrLmZlcnRyZUBzdC5jb20+IGZvciBTVE1pY3JvZWxlY3Ry b25pY3MuCisgKgkgICAgICBQaGlsaXBwZSBDb3JudSA8cGhpbGlwcGUuY29ybnVAc3QuY29tPiBm b3IgU1RNaWNyb2VsZWN0cm9uaWNzLgorICoKKyAqIFRoaXMgb3RtODAwOWEgcGFuZWwgZHJpdmVy IGlzIGJhc2VkIG9uIHRoZSBwYW5lbCBkcml2ZXIgZnJvbQorICogZHJpdmVycy9ncHUvZHJtL3Bh bmVsL3BhbmVsLW9yaXNldGVjaC1vdG04MDA5YS5jIChrZXJuZWwgbGludXgpCisgKgorICogU1BE WC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAKKyAqLworI2luY2x1ZGUgPGFzbS9ncGlvLmg+ CisjaW5jbHVkZSA8YmFja2xpZ2h0Lmg+CisjaW5jbHVkZSA8Y29tbW9uLmg+CisjaW5jbHVkZSA8 ZG0uaD4KKyNpbmNsdWRlIDxwYW5lbC5oPgorI2luY2x1ZGUgPHBvd2VyL3JlZ3VsYXRvci5oPgor I2luY2x1ZGUgPG1pcGlfZGlzcGxheS5oPgorCitERUNMQVJFX0dMT0JBTF9EQVRBX1BUUjsKKwor I2RlZmluZSBEUlZfTkFNRSAib3Jpc2V0ZWNoX290bTgwMDlhIgorCisjZGVmaW5lIE9UTTgwMDlB X0JBQ0tMSUdIVF9ERUZBVUxUCTI0MAorI2RlZmluZSBPVE04MDA5QV9CQUNLTElHSFRfTUFYCQky NTUKKworLyogTWFudWZhY3R1cmVyIENvbW1hbmQgU2V0ICovCisjZGVmaW5lIE1DU19BRFJTRlQJ MHgwMDAwCS8qIEFkZHJlc3MgU2hpZnQgRnVuY3Rpb24gKi8KKyNkZWZpbmUgTUNTX1BBTlNFVAkw eEIzQTYJLyogUGFuZWwgVHlwZSBTZXR0aW5nICovCisjZGVmaW5lIE1DU19TRF9DVFJMCTB4QzBB MgkvKiBTb3VyY2UgRHJpdmVyIFRpbWluZyBTZXR0aW5nICovCisjZGVmaW5lIE1DU19QX0RSVl9N CTB4QzBCNAkvKiBQYW5lbCBEcml2aW5nIE1vZGUgKi8KKyNkZWZpbmUgTUNTX09TQ19BREoJMHhD MTgxCS8qIE9zY2lsbGF0b3IgQWRqdXN0bWVudCBmb3IgSWRsZS9Ob3JtYWwgbW9kZSAqLworI2Rl ZmluZSBNQ1NfUkdCX1ZJRF9TRVQJMHhDMUExCS8qIFJHQiBWaWRlbyBNb2RlIFNldHRpbmcgKi8K KyNkZWZpbmUgTUNTX1NEX1BDSF9DVFJMCTB4QzQ4MAkvKiBTb3VyY2UgRHJpdmVyIFByZWNoYXJn ZSBDb250cm9sICovCisjZGVmaW5lIE1DU19OT19ET0MxCTB4QzQ4QQkvKiBDb21tYW5kIG5vdCBk b2N1bWVudGVkICovCisjZGVmaW5lIE1DU19QV1JfQ1RSTDEJMHhDNTgwCS8qIFBvd2VyIENvbnRy b2wgU2V0dGluZyAxICovCisjZGVmaW5lIE1DU19QV1JfQ1RSTDIJMHhDNTkwCS8qIFBvd2VyIENv bnRyb2wgU2V0dGluZyAyIGZvciBOb3JtYWwgTW9kZSAqLworI2RlZmluZSBNQ1NfUFdSX0NUUkw0 CTB4QzVCMAkvKiBQb3dlciBDb250cm9sIFNldHRpbmcgNCBmb3IgREMgVm9sdGFnZSAqLworI2Rl ZmluZSBNQ1NfUEFOQ1RSTFNFVDEJMHhDQjgwCS8qIFBhbmVsIENvbnRyb2wgU2V0dGluZyAxICov CisjZGVmaW5lIE1DU19QQU5DVFJMU0VUMgkweENCOTAJLyogUGFuZWwgQ29udHJvbCBTZXR0aW5n IDIgKi8KKyNkZWZpbmUgTUNTX1BBTkNUUkxTRVQzCTB4Q0JBMAkvKiBQYW5lbCBDb250cm9sIFNl dHRpbmcgMyAqLworI2RlZmluZSBNQ1NfUEFOQ1RSTFNFVDQJMHhDQkIwCS8qIFBhbmVsIENvbnRy b2wgU2V0dGluZyA0ICovCisjZGVmaW5lIE1DU19QQU5DVFJMU0VUNQkweENCQzAJLyogUGFuZWwg Q29udHJvbCBTZXR0aW5nIDUgKi8KKyNkZWZpbmUgTUNTX1BBTkNUUkxTRVQ2CTB4Q0JEMAkvKiBQ YW5lbCBDb250cm9sIFNldHRpbmcgNiAqLworI2RlZmluZSBNQ1NfUEFOQ1RSTFNFVDcJMHhDQkUw CS8qIFBhbmVsIENvbnRyb2wgU2V0dGluZyA3ICovCisjZGVmaW5lIE1DU19QQU5DVFJMU0VUOAkw eENCRjAJLyogUGFuZWwgQ29udHJvbCBTZXR0aW5nIDggKi8KKyNkZWZpbmUgTUNTX1BBTlUyRDEJ MHhDQzgwCS8qIFBhbmVsIFUyRCBTZXR0aW5nIDEgKi8KKyNkZWZpbmUgTUNTX1BBTlUyRDIJMHhD QzkwCS8qIFBhbmVsIFUyRCBTZXR0aW5nIDIgKi8KKyNkZWZpbmUgTUNTX1BBTlUyRDMJMHhDQ0Ew CS8qIFBhbmVsIFUyRCBTZXR0aW5nIDMgKi8KKyNkZWZpbmUgTUNTX1BBTkQyVTEJMHhDQ0IwCS8q IFBhbmVsIEQyVSBTZXR0aW5nIDEgKi8KKyNkZWZpbmUgTUNTX1BBTkQyVTIJMHhDQ0MwCS8qIFBh bmVsIEQyVSBTZXR0aW5nIDIgKi8KKyNkZWZpbmUgTUNTX1BBTkQyVTMJMHhDQ0QwCS8qIFBhbmVs IEQyVSBTZXR0aW5nIDMgKi8KKyNkZWZpbmUgTUNTX0dPQVZTVAkweENFODAJLyogR09BIFZTVCBT ZXR0aW5nICovCisjZGVmaW5lIE1DU19HT0FDTEtBMQkweENFQTAJLyogR09BIENMS0ExIFNldHRp bmcgKi8KKyNkZWZpbmUgTUNTX0dPQUNMS0EzCTB4Q0VCMAkvKiBHT0EgQ0xLQTMgU2V0dGluZyAq LworI2RlZmluZSBNQ1NfR09BRUNMSwkweENGQzAJLyogR09BIEVDTEsgU2V0dGluZyAqLworI2Rl ZmluZSBNQ1NfTk9fRE9DMgkweENGRDAJLyogQ29tbWFuZCBub3QgZG9jdW1lbnRlZCAqLworI2Rl ZmluZSBNQ1NfR1ZERFNFVAkweEQ4MDAJLyogR1ZERC9OR1ZERCAqLworI2RlZmluZSBNQ1NfVkNP TURDCTB4RDkwMAkvKiBWQ09NIFZvbHRhZ2UgU2V0dGluZyAqLworI2RlZmluZSBNQ1NfR01DVDJf MlAJMHhFMTAwCS8qIEdhbW1hIENvcnJlY3Rpb24gMi4yKyBTZXR0aW5nICovCisjZGVmaW5lIE1D U19HTUNUMl8yTgkweEUyMDAJLyogR2FtbWEgQ29ycmVjdGlvbiAyLjItIFNldHRpbmcgKi8KKyNk ZWZpbmUgTUNTX05PX0RPQzMJMHhGNUI2CS8qIENvbW1hbmQgbm90IGRvY3VtZW50ZWQgKi8KKyNk ZWZpbmUgTUNTX0NNRDJfRU5BMQkweEZGMDAJLyogRW5hYmxlIEFjY2VzcyBDb21tYW5kMiAiQ01E MiIgKi8KKyNkZWZpbmUgTUNTX0NNRDJfRU5BMgkweEZGODAJLyogRW5hYmxlIEFjY2VzcyBPcmlz ZSBDb21tYW5kMiAqLworCitzdHJ1Y3Qgb3RtODAwOWFfcGFuZWxfcHJpdiB7CisJc3RydWN0IHVk ZXZpY2UgKnJlZzsKKwlzdHJ1Y3QgZ3Bpb19kZXNjIHJlc2V0OworfTsKKworc3RhdGljIHZvaWQg b3RtODAwOWFfZGNzX3dyaXRlX2J1ZihzdHJ1Y3QgdWRldmljZSAqZGV2LCBjb25zdCB2b2lkICpk YXRhLAorCQkJCSAgIHNpemVfdCBsZW4pCit7CisJc3RydWN0IG1pcGlfZHNpX3BhbmVsX3BsYXQg KnBsYXQgPSBkZXZfZ2V0X3BsYXRkYXRhKGRldik7CisJc3RydWN0IG1pcGlfZHNpX2RldmljZSAq ZGV2aWNlID0gcGxhdC0+ZGV2aWNlOworCisJaWYgKG1pcGlfZHNpX2Rjc193cml0ZV9idWZmZXIo ZGV2aWNlLCBkYXRhLCBsZW4pIDwgMCkKKwkJcHJfZXJyKCJtaXBpIGRzaSBkY3Mgd3JpdGUgYnVm ZmVyIGZhaWxlZFxuIik7Cit9CisKKyNkZWZpbmUgZGNzX3dyaXRlX3NlcShkZXYsIHNlcS4uLikJ CQkJXAorKHsJCQkJCQkJCVwKKwlzdGF0aWMgY29uc3QgdTggZFtdID0geyBzZXEgfTsJCQkJXAor CW90bTgwMDlhX2Rjc193cml0ZV9idWYoZGV2LCBkLCBBUlJBWV9TSVpFKGQpKTsJCVwKK30pCisK KyNkZWZpbmUgZGNzX3dyaXRlX2NtZF9hdChkZXYsIGNtZCwgc2VxLi4uKQkJXAorKHsJCQkJCQkJ XAorCXN0YXRpYyBjb25zdCB1MTYgYyA9IGNtZDsJCQlcCisJc3RydWN0IHVkZXZpY2UgKmRldmlj ZSA9IGRldjsJCQlcCisJZGNzX3dyaXRlX3NlcShkZXZpY2UsIE1DU19BRFJTRlQsIChjKSAmIDB4 RkYpOwlcCisJZGNzX3dyaXRlX3NlcShkZXZpY2UsIChjKSA+PiA4LCBzZXEpOwkJXAorfSkKKwor c3RhdGljIGludCBvdG04MDA5YV9pbml0X3NlcXVlbmNlKHN0cnVjdCB1ZGV2aWNlICpkZXYpCit7 CisJc3RydWN0IG1pcGlfZHNpX3BhbmVsX3BsYXQgKnBsYXQgPSBkZXZfZ2V0X3BsYXRkYXRhKGRl dik7CisJc3RydWN0IG1pcGlfZHNpX2RldmljZSAqZGV2aWNlID0gcGxhdC0+ZGV2aWNlOworCWlu dCByZXQ7CisKKwkvKiBFbnRlciBDTUQyICovCisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19D TUQyX0VOQTEsIDB4ODAsIDB4MDksIDB4MDEpOworCisJLyogRW50ZXIgT3Jpc2UgQ29tbWFuZDIg Ki8KKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX0NNRDJfRU5BMiwgMHg4MCwgMHgwOSk7CisK KwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX1NEX1BDSF9DVFJMLCAweDMwKTsKKwltZGVsYXko MTApOworCisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19OT19ET0MxLCAweDQwKTsKKwltZGVs YXkoMTApOworCisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19QV1JfQ1RSTDQgKyAxLCAweEE5 KTsKKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX1BXUl9DVFJMMiArIDEsIDB4MzQpOworCWRj c193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfUF9EUlZfTSwgMHg1MCk7CisJZGNzX3dyaXRlX2NtZF9h dChkZXYsIE1DU19WQ09NREMsIDB4NEUpOworCWRjc193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfT1ND X0FESiwgMHg2Nik7IC8qIDY1SHogKi8KKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX1BXUl9D VFJMMiArIDIsIDB4MDEpOworCWRjc193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfUFdSX0NUUkwyICsg NSwgMHgzNCk7CisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19QV1JfQ1RSTDIgKyA0LCAweDMz KTsKKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX0dWRERTRVQsIDB4NzksIDB4NzkpOworCWRj c193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfU0RfQ1RSTCArIDEsIDB4MUIpOworCWRjc193cml0ZV9j bWRfYXQoZGV2LCBNQ1NfUFdSX0NUUkwxICsgMiwgMHg4Myk7CisJZGNzX3dyaXRlX2NtZF9hdChk ZXYsIE1DU19TRF9QQ0hfQ1RSTCArIDEsIDB4ODMpOworCWRjc193cml0ZV9jbWRfYXQoZGV2LCBN Q1NfUkdCX1ZJRF9TRVQsIDB4MEUpOworCWRjc193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfUEFOU0VU LCAweDAwLCAweDAxKTsKKworCWRjc193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfR09BVlNULCAweDg1 LCAweDAxLCAweDAwLCAweDg0LCAweDAxLCAweDAwKTsKKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwg TUNTX0dPQUNMS0ExLCAweDE4LCAweDA0LCAweDAzLCAweDM5LCAweDAwLCAweDAwLAorCQkJIDB4 MDAsIDB4MTgsIDB4MDMsIDB4MDMsIDB4M0EsIDB4MDAsIDB4MDAsIDB4MDApOworCWRjc193cml0 ZV9jbWRfYXQoZGV2LCBNQ1NfR09BQ0xLQTMsIDB4MTgsIDB4MDIsIDB4MDMsIDB4M0IsIDB4MDAs IDB4MDAsCisJCQkgMHgwMCwgMHgxOCwgMHgwMSwgMHgwMywgMHgzQywgMHgwMCwgMHgwMCwgMHgw MCk7CisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19HT0FFQ0xLLCAweDAxLCAweDAxLCAweDIw LCAweDIwLCAweDAwLCAweDAwLAorCQkJIDB4MDEsIDB4MDIsIDB4MDAsIDB4MDApOworCisJZGNz X3dyaXRlX2NtZF9hdChkZXYsIE1DU19OT19ET0MyLCAweDAwKTsKKworCWRjc193cml0ZV9jbWRf YXQoZGV2LCBNQ1NfUEFOQ1RSTFNFVDEsIDAsIDAsIDAsIDAsIDAsIDAsIDAsIDAsIDAsIDApOwor CWRjc193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfUEFOQ1RSTFNFVDIsIDAsIDAsIDAsIDAsIDAsIDAs IDAsIDAsIDAsIDAsCisJCQkgMCwgMCwgMCwgMCwgMCk7CisJZGNzX3dyaXRlX2NtZF9hdChkZXYs IE1DU19QQU5DVFJMU0VUMywgMCwgMCwgMCwgMCwgMCwgMCwgMCwgMCwgMCwgMCwKKwkJCSAwLCAw LCAwLCAwLCAwKTsKKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX1BBTkNUUkxTRVQ0LCAwLCAw LCAwLCAwLCAwLCAwLCAwLCAwLCAwLCAwKTsKKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX1BB TkNUUkxTRVQ1LCAwLCA0LCA0LCA0LCA0LCA0LCAwLCAwLCAwLCAwLAorCQkJIDAsIDAsIDAsIDAs IDApOworCWRjc193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfUEFOQ1RSTFNFVDYsIDAsIDAsIDAsIDAs IDAsIDAsIDQsIDQsIDQsIDQsCisJCQkgNCwgMCwgMCwgMCwgMCk7CisJZGNzX3dyaXRlX2NtZF9h dChkZXYsIE1DU19QQU5DVFJMU0VUNywgMCwgMCwgMCwgMCwgMCwgMCwgMCwgMCwgMCwgMCk7CisJ ZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19QQU5DVFJMU0VUOCwgMHhGRiwgMHhGRiwgMHhGRiwg MHhGRiwgMHhGRiwKKwkJCSAweEZGLCAweEZGLCAweEZGLCAweEZGLCAweEZGKTsKKworCWRjc193 cml0ZV9jbWRfYXQoZGV2LCBNQ1NfUEFOVTJEMSwgMHgwMCwgMHgyNiwgMHgwOSwgMHgwQiwgMHgw MSwgMHgyNSwKKwkJCSAweDAwLCAweDAwLCAweDAwLCAweDAwKTsKKwlkY3Nfd3JpdGVfY21kX2F0 KGRldiwgTUNTX1BBTlUyRDIsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsCisJ CQkgMHgwMCwgMHgwMCwgMHgwMCwgMHgwMCwgMHgwMCwgMHgyNiwgMHgwQSwgMHgwQywgMHgwMik7 CisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19QQU5VMkQzLCAweDI1LCAweDAwLCAweDAwLCAw eDAwLCAweDAwLCAweDAwLAorCQkJIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAs IDB4MDAsIDB4MDAsIDB4MDApOworCWRjc193cml0ZV9jbWRfYXQoZGV2LCBNQ1NfUEFORDJVMSwg MHgwMCwgMHgyNSwgMHgwQywgMHgwQSwgMHgwMiwgMHgyNiwKKwkJCSAweDAwLCAweDAwLCAweDAw LCAweDAwKTsKKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwgTUNTX1BBTkQyVTIsIDB4MDAsIDB4MDAs IDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsCisJCQkgMHgwMCwgMHgwMCwgMHgwMCwgMHgwMCwgMHgw MCwgMHgyNSwgMHgwQiwgMHgwOSwgMHgwMSk7CisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19Q QU5EMlUzLCAweDI2LCAweDAwLCAweDAwLCAweDAwLCAweDAwLCAweDAwLAorCQkJIDB4MDAsIDB4 MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDAsIDB4MDApOworCisJZGNzX3dy aXRlX2NtZF9hdChkZXYsIE1DU19QV1JfQ1RSTDEgKyAxLCAweDY2KTsKKworCWRjc193cml0ZV9j bWRfYXQoZGV2LCBNQ1NfTk9fRE9DMywgMHgwNik7CisKKwlkY3Nfd3JpdGVfY21kX2F0KGRldiwg TUNTX0dNQ1QyXzJQLCAweDAwLCAweDA5LCAweDBGLCAweDBFLCAweDA3LCAweDEwLAorCQkJIDB4 MEIsIDB4MEEsIDB4MDQsIDB4MDcsIDB4MEIsIDB4MDgsIDB4MEYsIDB4MTAsIDB4MEEsCisJCQkg MHgwMSk7CisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19HTUNUMl8yTiwgMHgwMCwgMHgwOSwg MHgwRiwgMHgwRSwgMHgwNywgMHgxMCwKKwkJCSAweDBCLCAweDBBLCAweDA0LCAweDA3LCAweDBC LCAweDA4LCAweDBGLCAweDEwLCAweDBBLAorCQkJIDB4MDEpOworCisJLyogRXhpdCBDTUQyICov CisJZGNzX3dyaXRlX2NtZF9hdChkZXYsIE1DU19DTUQyX0VOQTEsIDB4RkYsIDB4RkYsIDB4RkYp OworCisJcmV0ID0gIG1pcGlfZHNpX2Rjc19ub3AoZGV2aWNlKTsKKwlpZiAocmV0KQorCQlyZXR1 cm4gcmV0OworCisJcmV0ID0gbWlwaV9kc2lfZGNzX2V4aXRfc2xlZXBfbW9kZShkZXZpY2UpOwor CWlmIChyZXQpCisJCXJldHVybiByZXQ7CisKKwkvKiBXYWl0IGZvciBzbGVlcCBvdXQgZXhpdCAq LworCW1kZWxheSgxMjApOworCisJLyogRGVmYXVsdCBwb3J0cmFpdCA0ODB4ODAwIHJnYjI0ICov CisJZGNzX3dyaXRlX3NlcShkZXYsIE1JUElfRENTX1NFVF9BRERSRVNTX01PREUsIDB4MDApOwor CisJcmV0ID0gIG1pcGlfZHNpX2Rjc19zZXRfY29sdW1uX2FkZHJlc3MoZGV2aWNlLCAwLCA0Nzkp OworCWlmIChyZXQpCisJCXJldHVybiByZXQ7CisKKwlyZXQgPSAgbWlwaV9kc2lfZGNzX3NldF9w YWdlX2FkZHJlc3MoZGV2aWNlLCAwLCA3OTkpOworCWlmIChyZXQpCisJCXJldHVybiByZXQ7CisK KwkvKiBTZWUgb3RtODAwOWEgZHJpdmVyIGRvY3VtZW50YXRpb24gZm9yIHBpeGVsIGZvcm1hdCBk ZXNjcmlwdGlvbnMgKi8KKwlyZXQgPSAgbWlwaV9kc2lfZGNzX3NldF9waXhlbF9mb3JtYXQoZGV2 aWNlLCBNSVBJX0RDU19QSVhFTF9GTVRfMjRCSVQgfAorCQkJCQkgICAgIE1JUElfRENTX1BJWEVM X0ZNVF8yNEJJVCA8PCA0KTsKKwlpZiAocmV0KQorCQlyZXR1cm4gcmV0OworCisJLyogRGlzYWJs ZSBDQUJDIGZlYXR1cmUgKi8KKwlkY3Nfd3JpdGVfc2VxKGRldiwgTUlQSV9EQ1NfV1JJVEVfUE9X RVJfU0FWRSwgMHgwMCk7CisKKwlyZXQgPSBtaXBpX2RzaV9kY3Nfc2V0X2Rpc3BsYXlfb24oZGV2 aWNlKTsKKwlpZiAocmV0KQorCQlyZXR1cm4gcmV0OworCisJcmV0ID0gbWlwaV9kc2lfZGNzX25v cChkZXZpY2UpOworCWlmIChyZXQpCisJCXJldHVybiByZXQ7CisKKwkvKiBTZW5kIENvbW1hbmQg R1JBTSBtZW1vcnkgd3JpdGUgKG5vIHBhcmFtZXRlcnMpICovCisJZGNzX3dyaXRlX3NlcShkZXYs IE1JUElfRENTX1dSSVRFX01FTU9SWV9TVEFSVCk7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGlj IGludCBvdG04MDA5YV9wYW5lbF9lbmFibGVfYmFja2xpZ2h0KHN0cnVjdCB1ZGV2aWNlICpkZXYp Cit7CisJc3RydWN0IG1pcGlfZHNpX3BhbmVsX3BsYXQgKnBsYXQgPSBkZXZfZ2V0X3BsYXRkYXRh KGRldik7CisJc3RydWN0IG1pcGlfZHNpX2RldmljZSAqZGV2aWNlID0gcGxhdC0+ZGV2aWNlOwor CWludCByZXQ7CisKKwlkZXZpY2UtPmxhbmVzID0gMjsKKwlkZXZpY2UtPmZvcm1hdCA9IE1JUElf RFNJX0ZNVF9SR0I4ODg7CisJZGV2aWNlLT5tb2RlX2ZsYWdzID0gTUlQSV9EU0lfTU9ERV9WSURF TyB8CisJCQkgICAgIE1JUElfRFNJX01PREVfVklERU9fQlVSU1QgfAorCQkJICAgICBNSVBJX0RT SV9NT0RFX0xQTTsKKworCXJldCA9IG1pcGlfZHNpX2F0dGFjaChkZXZpY2UpOworCWlmIChyZXQg PCAwKQorCQlyZXR1cm4gcmV0OworCisJcHJfaW5mbygiJXM6IGluaXRpYWxpemUgcGFuZWxcbiIs IF9fZnVuY19fKTsKKwlyZXQgPSBvdG04MDA5YV9pbml0X3NlcXVlbmNlKGRldik7CisJaWYgKHJl dCkKKwkJcmV0dXJuIHJldDsKKworCS8qCisJICogUG93ZXIgb24gdGhlIGJhY2tsaWdodCB3aXRo IHRoZSByZXF1ZXN0ZWQgYnJpZ2h0bmVzcworCSAqIE5vdGUgV2UgY2FuIG5vdCB1c2UgbWlwaV9k c2lfZGNzX3NldF9kaXNwbGF5X2JyaWdodG5lc3MoKQorCSAqIGFzIG90bTgwMDlhIGRyaXZlciBz dXBwb3J0IG9ubHkgOC1iaXQgYnJpZ2h0bmVzcyAoMSBwYXJhbSkuCisJICovCisJcHJfaW5mbygi JXM6IHN0YXJ0LCBiYWNrbGlnaHRcbiIsIF9fZnVuY19fKTsKKworCWRjc193cml0ZV9zZXEoZGV2 LCBNSVBJX0RDU19TRVRfRElTUExBWV9CUklHSFRORVNTLAorCQkgICAgICBPVE04MDA5QV9CQUNL TElHSFRfREVGQVVMVCk7CisKKwkvKiBVcGRhdGUgQnJpZ2h0bmVzcyBDb250cm9sICYgQmFja2xp Z2h0ICovCisJZGNzX3dyaXRlX3NlcShkZXYsIE1JUElfRENTX1dSSVRFX0NPTlRST0xfRElTUExB WSwgMHgyNCk7CisKKwkvKiAgbmVlZCB0byB3YWl0IGEgZmV3IHRpbWUgYmVmb3JlIHNldCB0aGUg RFNJIGJyaWRnZSBpbiB2aWRlbyBtb2RlICovCisJbWRlbGF5KDEwKTsKKworCXJldHVybiAwOwor fQorCitzdGF0aWMgaW50IG90bTgwMDlhX3BhbmVsX29mZGF0YV90b19wbGF0ZGF0YShzdHJ1Y3Qg dWRldmljZSAqZGV2KQoreworCXN0cnVjdCBvdG04MDA5YV9wYW5lbF9wcml2ICpwcml2ID0gZGV2 X2dldF9wcml2KGRldik7CisJaW50IHJldDsKKworCWlmIChJU19FTkFCTEVEKENPTkZJR19ETV9S RUdVTEFUT1IpKSB7CisJCXJldCA9IHVjbGFzc19nZXRfZGV2aWNlX2J5X3BoYW5kbGUoVUNMQVNT X1JFR1VMQVRPUiwgZGV2LAorCQkJCQkJICAgInBvd2VyLXN1cHBseSIsICZwcml2LT5yZWcpOwor CQlpZiAocmV0KSB7CisJCQlwcl9lcnIoIiVzOiBXYXJuaW5nOiBjYW5ub3QgZ2V0IHBvd2VyIHN1 cHBseVxuIiwKKwkJCSAgICAgICBfX2Z1bmNfXyk7CisJCQlpZiAocmV0ICE9IC1FTk9FTlQpCisJ CQkJcmV0dXJuIHJldDsKKwkJfQorCX0KKworCXJldCA9IGdwaW9fcmVxdWVzdF9ieV9uYW1lKGRl diwgInJlc2V0LWdwaW9zIiwgMCwgJnByaXYtPnJlc2V0LAorCQkJCSAgIEdQSU9EX0lTX09VVCk7 CisJaWYgKHJldCkgeworCQlwcl9lcnIoIiVzOiBXYXJuaW5nOiBjYW5ub3QgZ2V0IHJlc2V0IEdQ SU9cbiIsIF9fZnVuY19fKTsKKwkJaWYgKHJldCAhPSAtRU5PRU5UKQorCQkJcmV0dXJuIHJldDsK Kwl9CisKKwkvKiByZXNldCBwYW5lbCBtdXN0IGJlIGRvbmUgYmVmb3JlIHByb2JlICovCisJZG1f Z3Bpb19zZXRfdmFsdWUoJnByaXYtPnJlc2V0LCB0cnVlKTsKKworCXJldHVybiAwOworfQorCitz dGF0aWMgaW50IG90bTgwMDlhX3BhbmVsX3Byb2JlKHN0cnVjdCB1ZGV2aWNlICpkZXYpCit7CisJ c3RydWN0IG90bTgwMDlhX3BhbmVsX3ByaXYgKnByaXYgPSBkZXZfZ2V0X3ByaXYoZGV2KTsKKwlp bnQgcmV0OworCisJaWYgKElTX0VOQUJMRUQoQ09ORklHX0RNX1JFR1VMQVRPUikgJiYgcHJpdi0+ cmVnKSB7CisJCXByX2VycigiJXM6IEVuYWJsZSByZWd1bGF0b3IgJyVzJ1xuIiwgX19mdW5jX18s CisJCSAgICAgICBwcml2LT5yZWctPm5hbWUpOworCQlyZXQgPSByZWd1bGF0b3Jfc2V0X2VuYWJs ZShwcml2LT5yZWcsIHRydWUpOworCQlpZiAocmV0KQorCQkJcmV0dXJuIHJldDsKKwl9CisKKwlk bV9ncGlvX3NldF92YWx1ZSgmcHJpdi0+cmVzZXQsIGZhbHNlKTsKKworCXJldHVybiAwOworfQor CitzdGF0aWMgY29uc3Qgc3RydWN0IHBhbmVsX29wcyBvdG04MDA5YV9wYW5lbF9vcHMgPSB7CisJ LmVuYWJsZV9iYWNrbGlnaHQgPSBvdG04MDA5YV9wYW5lbF9lbmFibGVfYmFja2xpZ2h0LAorfTsK Kworc3RhdGljIGNvbnN0IHN0cnVjdCB1ZGV2aWNlX2lkIG90bTgwMDlhX3BhbmVsX2lkc1tdID0g eworCXsgLmNvbXBhdGlibGUgPSAib3Jpc2V0ZWNoLG90bTgwMDlhIiB9LAorCXsgfQorfTsKKwor VV9CT09UX0RSSVZFUihvdG04MDA5YV9wYW5lbCkgPSB7CisJLm5hbWUJCQkgID0gIm90bTgwMDlh X3BhbmVsIiwKKwkuaWQJCQkgID0gVUNMQVNTX1BBTkVMLAorCS5vZl9tYXRjaAkJICA9IG90bTgw MDlhX3BhbmVsX2lkcywKKwkub3BzCQkJICA9ICZvdG04MDA5YV9wYW5lbF9vcHMsCisJLm9mZGF0 YV90b19wbGF0ZGF0YQkgID0gb3RtODAwOWFfcGFuZWxfb2ZkYXRhX3RvX3BsYXRkYXRhLAorCS5w cm9iZQkJCSAgPSBvdG04MDA5YV9wYW5lbF9wcm9iZSwKKwkucGxhdGRhdGFfYXV0b19hbGxvY19z aXplID0gc2l6ZW9mKHN0cnVjdCBtaXBpX2RzaV9wYW5lbF9wbGF0KSwKKwkucHJpdl9hdXRvX2Fs bG9jX3NpemUJPSBzaXplb2Yoc3RydWN0IG90bTgwMDlhX3BhbmVsX3ByaXYpLAorfTsKLS0gCjEu OS4xCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmkt ZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6 Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1427884AbeCBPtm (ORCPT ); Fri, 2 Mar 2018 10:49:42 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:15790 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S936276AbeCBPom (ORCPT ); Fri, 2 Mar 2018 10:44:42 -0500 From: yannick fertre To: Vikas Manocha , Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Patrice Chotard , Patrick DELAUNAY , Christophe KERELLO , Archit Taneja , Andrzej Hajda , "Laurent Pinchart" , David Airlie , Brian Norris , Bhumika Goyal , Gustavo Padovan , "Maarten Lankhorst" , Sean Paul , Albert Aribaud , "Simon Glass" , Anatolij Gustschin , Thierry Reding CC: , , Subject: [PATCH v2 04/10] video: add support of panel OTM8009A Date: Fri, 2 Mar 2018 16:44:05 +0100 Message-ID: <1520005451-23217-5-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> References: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.68] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-03-02_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Support for Orise Tech otm8009a 480p dsi 2dl video mode panel. Signed-off-by: yannick fertre --- drivers/video/Kconfig | 8 + drivers/video/Makefile | 1 + drivers/video/orisetech_otm8009a.c | 329 +++++++++++++++++++++++++++++++++++++ 3 files changed, 338 insertions(+) create mode 100644 drivers/video/orisetech_otm8009a.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 1981298..b5fc535 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804 from a parallel LCD interface and translate it on the fy into a DP interface for driving eDP TFT displays. It uses I2C for configuration. +config VIDEO_LCD_ORISETECH_OTM8009A + bool "OTM8009A DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + default n + ---help--- + Support for Orise Tech otm8009a 480p dsi 2dl video mode panel. + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" default n diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 6f42cca..65002af 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o +obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o diff --git a/drivers/video/orisetech_otm8009a.c b/drivers/video/orisetech_otm8009a.c new file mode 100644 index 0000000..79f2da8 --- /dev/null +++ b/drivers/video/orisetech_otm8009a.c @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2018 STMicroelectronics - All Rights Reserved + * Author(s): Yannick Fertre for STMicroelectronics. + * Philippe Cornu for STMicroelectronics. + * + * This otm8009a panel driver is based on the panel driver from + * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux) + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DRV_NAME "orisetech_otm8009a" + +#define OTM8009A_BACKLIGHT_DEFAULT 240 +#define OTM8009A_BACKLIGHT_MAX 255 + +/* Manufacturer Command Set */ +#define MCS_ADRSFT 0x0000 /* Address Shift Function */ +#define MCS_PANSET 0xB3A6 /* Panel Type Setting */ +#define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */ +#define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */ +#define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */ +#define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */ +#define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */ +#define MCS_NO_DOC1 0xC48A /* Command not documented */ +#define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */ +#define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */ +#define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */ +#define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */ +#define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */ +#define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */ +#define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */ +#define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */ +#define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */ +#define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */ +#define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */ +#define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */ +#define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */ +#define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */ +#define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */ +#define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */ +#define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */ +#define MCS_GOAVST 0xCE80 /* GOA VST Setting */ +#define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */ +#define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */ +#define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */ +#define MCS_NO_DOC2 0xCFD0 /* Command not documented */ +#define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */ +#define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */ +#define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */ +#define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */ +#define MCS_NO_DOC3 0xF5B6 /* Command not documented */ +#define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */ +#define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */ + +struct otm8009a_panel_priv { + struct udevice *reg; + struct gpio_desc reset; +}; + +static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data, + size_t len) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + + if (mipi_dsi_dcs_write_buffer(device, data, len) < 0) + pr_err("mipi dsi dcs write buffer failed\n"); +} + +#define dcs_write_seq(dev, seq...) \ +({ \ + static const u8 d[] = { seq }; \ + otm8009a_dcs_write_buf(dev, d, ARRAY_SIZE(d)); \ +}) + +#define dcs_write_cmd_at(dev, cmd, seq...) \ +({ \ + static const u16 c = cmd; \ + struct udevice *device = dev; \ + dcs_write_seq(device, MCS_ADRSFT, (c) & 0xFF); \ + dcs_write_seq(device, (c) >> 8, seq); \ +}) + +static int otm8009a_init_sequence(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + /* Enter CMD2 */ + dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); + + /* Enter Orise Command2 */ + dcs_write_cmd_at(dev, MCS_CMD2_ENA2, 0x80, 0x09); + + dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL, 0x30); + mdelay(10); + + dcs_write_cmd_at(dev, MCS_NO_DOC1, 0x40); + mdelay(10); + + dcs_write_cmd_at(dev, MCS_PWR_CTRL4 + 1, 0xA9); + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 1, 0x34); + dcs_write_cmd_at(dev, MCS_P_DRV_M, 0x50); + dcs_write_cmd_at(dev, MCS_VCOMDC, 0x4E); + dcs_write_cmd_at(dev, MCS_OSC_ADJ, 0x66); /* 65Hz */ + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 2, 0x01); + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 5, 0x34); + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 4, 0x33); + dcs_write_cmd_at(dev, MCS_GVDDSET, 0x79, 0x79); + dcs_write_cmd_at(dev, MCS_SD_CTRL + 1, 0x1B); + dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 2, 0x83); + dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL + 1, 0x83); + dcs_write_cmd_at(dev, MCS_RGB_VID_SET, 0x0E); + dcs_write_cmd_at(dev, MCS_PANSET, 0x00, 0x01); + + dcs_write_cmd_at(dev, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); + dcs_write_cmd_at(dev, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, + 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, + 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, + 0x01, 0x02, 0x00, 0x00); + + dcs_write_cmd_at(dev, MCS_NO_DOC2, 0x00); + + dcs_write_cmd_at(dev, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, + 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, + 4, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); + + dcs_write_cmd_at(dev, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, + 0x00, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); + dcs_write_cmd_at(dev, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, + 0x00, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); + dcs_write_cmd_at(dev, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + + dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 1, 0x66); + + dcs_write_cmd_at(dev, MCS_NO_DOC3, 0x06); + + dcs_write_cmd_at(dev, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, + 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, + 0x01); + dcs_write_cmd_at(dev, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, + 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, + 0x01); + + /* Exit CMD2 */ + dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); + + ret = mipi_dsi_dcs_nop(device); + if (ret) + return ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(device); + if (ret) + return ret; + + /* Wait for sleep out exit */ + mdelay(120); + + /* Default portrait 480x800 rgb24 */ + dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00); + + ret = mipi_dsi_dcs_set_column_address(device, 0, 479); + if (ret) + return ret; + + ret = mipi_dsi_dcs_set_page_address(device, 0, 799); + if (ret) + return ret; + + /* See otm8009a driver documentation for pixel format descriptions */ + ret = mipi_dsi_dcs_set_pixel_format(device, MIPI_DCS_PIXEL_FMT_24BIT | + MIPI_DCS_PIXEL_FMT_24BIT << 4); + if (ret) + return ret; + + /* Disable CABC feature */ + dcs_write_seq(dev, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + + ret = mipi_dsi_dcs_set_display_on(device); + if (ret) + return ret; + + ret = mipi_dsi_dcs_nop(device); + if (ret) + return ret; + + /* Send Command GRAM memory write (no parameters) */ + dcs_write_seq(dev, MIPI_DCS_WRITE_MEMORY_START); + + return 0; +} + +static int otm8009a_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + device->lanes = 2; + device->format = MIPI_DSI_FMT_RGB888; + device->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + pr_info("%s: initialize panel\n", __func__); + ret = otm8009a_init_sequence(dev); + if (ret) + return ret; + + /* + * Power on the backlight with the requested brightness + * Note We can not use mipi_dsi_dcs_set_display_brightness() + * as otm8009a driver support only 8-bit brightness (1 param). + */ + pr_info("%s: start, backlight\n", __func__); + + dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + OTM8009A_BACKLIGHT_DEFAULT); + + /* Update Brightness Control & Backlight */ + dcs_write_seq(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); + + /* need to wait a few time before set the DSI bridge in video mode */ + mdelay(10); + + return 0; +} + +static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev) +{ + struct otm8009a_panel_priv *priv = dev_get_priv(dev); + int ret; + + if (IS_ENABLED(CONFIG_DM_REGULATOR)) { + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "power-supply", &priv->reg); + if (ret) { + pr_err("%s: Warning: cannot get power supply\n", + __func__); + if (ret != -ENOENT) + return ret; + } + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, + GPIOD_IS_OUT); + if (ret) { + pr_err("%s: Warning: cannot get reset GPIO\n", __func__); + if (ret != -ENOENT) + return ret; + } + + /* reset panel must be done before probe */ + dm_gpio_set_value(&priv->reset, true); + + return 0; +} + +static int otm8009a_panel_probe(struct udevice *dev) +{ + struct otm8009a_panel_priv *priv = dev_get_priv(dev); + int ret; + + if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) { + pr_err("%s: Enable regulator '%s'\n", __func__, + priv->reg->name); + ret = regulator_set_enable(priv->reg, true); + if (ret) + return ret; + } + + dm_gpio_set_value(&priv->reset, false); + + return 0; +} + +static const struct panel_ops otm8009a_panel_ops = { + .enable_backlight = otm8009a_panel_enable_backlight, +}; + +static const struct udevice_id otm8009a_panel_ids[] = { + { .compatible = "orisetech,otm8009a" }, + { } +}; + +U_BOOT_DRIVER(otm8009a_panel) = { + .name = "otm8009a_panel", + .id = UCLASS_PANEL, + .of_match = otm8009a_panel_ids, + .ops = &otm8009a_panel_ops, + .ofdata_to_platdata = otm8009a_panel_ofdata_to_platdata, + .probe = otm8009a_panel_probe, + .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat), + .priv_auto_alloc_size = sizeof(struct otm8009a_panel_priv), +}; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: yannick fertre Date: Fri, 2 Mar 2018 16:44:05 +0100 Subject: [U-Boot] [PATCH v2 04/10] video: add support of panel OTM8009A In-Reply-To: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> References: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> Message-ID: <1520005451-23217-5-git-send-email-yannick.fertre@st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Support for Orise Tech otm8009a 480p dsi 2dl video mode panel. Signed-off-by: yannick fertre --- drivers/video/Kconfig | 8 + drivers/video/Makefile | 1 + drivers/video/orisetech_otm8009a.c | 329 +++++++++++++++++++++++++++++++++++++ 3 files changed, 338 insertions(+) create mode 100644 drivers/video/orisetech_otm8009a.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 1981298..b5fc535 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804 from a parallel LCD interface and translate it on the fy into a DP interface for driving eDP TFT displays. It uses I2C for configuration. +config VIDEO_LCD_ORISETECH_OTM8009A + bool "OTM8009A DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + default n + ---help--- + Support for Orise Tech otm8009a 480p dsi 2dl video mode panel. + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" default n diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 6f42cca..65002af 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o +obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o diff --git a/drivers/video/orisetech_otm8009a.c b/drivers/video/orisetech_otm8009a.c new file mode 100644 index 0000000..79f2da8 --- /dev/null +++ b/drivers/video/orisetech_otm8009a.c @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2018 STMicroelectronics - All Rights Reserved + * Author(s): Yannick Fertre for STMicroelectronics. + * Philippe Cornu for STMicroelectronics. + * + * This otm8009a panel driver is based on the panel driver from + * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux) + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DRV_NAME "orisetech_otm8009a" + +#define OTM8009A_BACKLIGHT_DEFAULT 240 +#define OTM8009A_BACKLIGHT_MAX 255 + +/* Manufacturer Command Set */ +#define MCS_ADRSFT 0x0000 /* Address Shift Function */ +#define MCS_PANSET 0xB3A6 /* Panel Type Setting */ +#define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */ +#define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */ +#define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */ +#define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */ +#define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */ +#define MCS_NO_DOC1 0xC48A /* Command not documented */ +#define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */ +#define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */ +#define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */ +#define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */ +#define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */ +#define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */ +#define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */ +#define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */ +#define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */ +#define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */ +#define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */ +#define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */ +#define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */ +#define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */ +#define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */ +#define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */ +#define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */ +#define MCS_GOAVST 0xCE80 /* GOA VST Setting */ +#define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */ +#define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */ +#define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */ +#define MCS_NO_DOC2 0xCFD0 /* Command not documented */ +#define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */ +#define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */ +#define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */ +#define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */ +#define MCS_NO_DOC3 0xF5B6 /* Command not documented */ +#define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */ +#define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */ + +struct otm8009a_panel_priv { + struct udevice *reg; + struct gpio_desc reset; +}; + +static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data, + size_t len) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + + if (mipi_dsi_dcs_write_buffer(device, data, len) < 0) + pr_err("mipi dsi dcs write buffer failed\n"); +} + +#define dcs_write_seq(dev, seq...) \ +({ \ + static const u8 d[] = { seq }; \ + otm8009a_dcs_write_buf(dev, d, ARRAY_SIZE(d)); \ +}) + +#define dcs_write_cmd_at(dev, cmd, seq...) \ +({ \ + static const u16 c = cmd; \ + struct udevice *device = dev; \ + dcs_write_seq(device, MCS_ADRSFT, (c) & 0xFF); \ + dcs_write_seq(device, (c) >> 8, seq); \ +}) + +static int otm8009a_init_sequence(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + /* Enter CMD2 */ + dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); + + /* Enter Orise Command2 */ + dcs_write_cmd_at(dev, MCS_CMD2_ENA2, 0x80, 0x09); + + dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL, 0x30); + mdelay(10); + + dcs_write_cmd_at(dev, MCS_NO_DOC1, 0x40); + mdelay(10); + + dcs_write_cmd_at(dev, MCS_PWR_CTRL4 + 1, 0xA9); + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 1, 0x34); + dcs_write_cmd_at(dev, MCS_P_DRV_M, 0x50); + dcs_write_cmd_at(dev, MCS_VCOMDC, 0x4E); + dcs_write_cmd_at(dev, MCS_OSC_ADJ, 0x66); /* 65Hz */ + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 2, 0x01); + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 5, 0x34); + dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 4, 0x33); + dcs_write_cmd_at(dev, MCS_GVDDSET, 0x79, 0x79); + dcs_write_cmd_at(dev, MCS_SD_CTRL + 1, 0x1B); + dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 2, 0x83); + dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL + 1, 0x83); + dcs_write_cmd_at(dev, MCS_RGB_VID_SET, 0x0E); + dcs_write_cmd_at(dev, MCS_PANSET, 0x00, 0x01); + + dcs_write_cmd_at(dev, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); + dcs_write_cmd_at(dev, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, + 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, + 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, + 0x01, 0x02, 0x00, 0x00); + + dcs_write_cmd_at(dev, MCS_NO_DOC2, 0x00); + + dcs_write_cmd_at(dev, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, + 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, + 4, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(dev, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); + + dcs_write_cmd_at(dev, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, + 0x00, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); + dcs_write_cmd_at(dev, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, + 0x00, 0x00, 0x00, 0x00); + dcs_write_cmd_at(dev, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); + dcs_write_cmd_at(dev, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + + dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 1, 0x66); + + dcs_write_cmd_at(dev, MCS_NO_DOC3, 0x06); + + dcs_write_cmd_at(dev, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, + 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, + 0x01); + dcs_write_cmd_at(dev, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, + 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, + 0x01); + + /* Exit CMD2 */ + dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); + + ret = mipi_dsi_dcs_nop(device); + if (ret) + return ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(device); + if (ret) + return ret; + + /* Wait for sleep out exit */ + mdelay(120); + + /* Default portrait 480x800 rgb24 */ + dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00); + + ret = mipi_dsi_dcs_set_column_address(device, 0, 479); + if (ret) + return ret; + + ret = mipi_dsi_dcs_set_page_address(device, 0, 799); + if (ret) + return ret; + + /* See otm8009a driver documentation for pixel format descriptions */ + ret = mipi_dsi_dcs_set_pixel_format(device, MIPI_DCS_PIXEL_FMT_24BIT | + MIPI_DCS_PIXEL_FMT_24BIT << 4); + if (ret) + return ret; + + /* Disable CABC feature */ + dcs_write_seq(dev, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + + ret = mipi_dsi_dcs_set_display_on(device); + if (ret) + return ret; + + ret = mipi_dsi_dcs_nop(device); + if (ret) + return ret; + + /* Send Command GRAM memory write (no parameters) */ + dcs_write_seq(dev, MIPI_DCS_WRITE_MEMORY_START); + + return 0; +} + +static int otm8009a_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + device->lanes = 2; + device->format = MIPI_DSI_FMT_RGB888; + device->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + pr_info("%s: initialize panel\n", __func__); + ret = otm8009a_init_sequence(dev); + if (ret) + return ret; + + /* + * Power on the backlight with the requested brightness + * Note We can not use mipi_dsi_dcs_set_display_brightness() + * as otm8009a driver support only 8-bit brightness (1 param). + */ + pr_info("%s: start, backlight\n", __func__); + + dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + OTM8009A_BACKLIGHT_DEFAULT); + + /* Update Brightness Control & Backlight */ + dcs_write_seq(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); + + /* need to wait a few time before set the DSI bridge in video mode */ + mdelay(10); + + return 0; +} + +static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev) +{ + struct otm8009a_panel_priv *priv = dev_get_priv(dev); + int ret; + + if (IS_ENABLED(CONFIG_DM_REGULATOR)) { + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "power-supply", &priv->reg); + if (ret) { + pr_err("%s: Warning: cannot get power supply\n", + __func__); + if (ret != -ENOENT) + return ret; + } + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, + GPIOD_IS_OUT); + if (ret) { + pr_err("%s: Warning: cannot get reset GPIO\n", __func__); + if (ret != -ENOENT) + return ret; + } + + /* reset panel must be done before probe */ + dm_gpio_set_value(&priv->reset, true); + + return 0; +} + +static int otm8009a_panel_probe(struct udevice *dev) +{ + struct otm8009a_panel_priv *priv = dev_get_priv(dev); + int ret; + + if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) { + pr_err("%s: Enable regulator '%s'\n", __func__, + priv->reg->name); + ret = regulator_set_enable(priv->reg, true); + if (ret) + return ret; + } + + dm_gpio_set_value(&priv->reset, false); + + return 0; +} + +static const struct panel_ops otm8009a_panel_ops = { + .enable_backlight = otm8009a_panel_enable_backlight, +}; + +static const struct udevice_id otm8009a_panel_ids[] = { + { .compatible = "orisetech,otm8009a" }, + { } +}; + +U_BOOT_DRIVER(otm8009a_panel) = { + .name = "otm8009a_panel", + .id = UCLASS_PANEL, + .of_match = otm8009a_panel_ids, + .ops = &otm8009a_panel_ops, + .ofdata_to_platdata = otm8009a_panel_ofdata_to_platdata, + .probe = otm8009a_panel_probe, + .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat), + .priv_auto_alloc_size = sizeof(struct otm8009a_panel_priv), +}; -- 1.9.1