From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lyude Paul Subject: Re: [PATCH v3 5/5] drm/i915: Implement proper fallback training for MST Date: Mon, 12 Mar 2018 18:16:25 -0400 Message-ID: <1520892985.12372.14.camel@redhat.com> References: <20180308232421.14049-1-lyude@redhat.com> <20180309213232.19855-1-lyude@redhat.com> <20180309213232.19855-5-lyude@redhat.com> <20180312220522.GC3022@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180312220522.GC3022@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Manasi Navare Cc: David Airlie , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi List-Id: dri-devel@lists.freedesktop.org T24gTW9uLCAyMDE4LTAzLTEyIGF0IDE1OjA1IC0wNzAwLCBNYW5hc2kgTmF2YXJlIHdyb3RlOgo+ IE9uIEZyaSwgTWFyIDA5LCAyMDE4IGF0IDA0OjMyOjMxUE0gLTA1MDAsIEx5dWRlIFBhdWwgd3Jv dGU6Cj4gPiBGb3IgYSB3aGlsZSB3ZSBhY3R1YWxseSBoYXZlbid0IGhhZCBhbnkgd2F5IG9mIHJl dHJhaW5pbmcgTVNUIGxpbmtzIHdpdGgKPiA+IGZhbGxiYWNrIGxpbmsgcGFyYW1ldGVycyBsaWtl IHdlIGRvIHdpdGggU1NULiBXaGlsZSB1bmNvbW1vbiwgY2VydGFpbgo+ID4gc2V0dXBzIHN1Y2gg YXMgbXkgQ2FsZGlnaXQgVFMzICsgRVZHQSBNU1QgaHViIHJlcXVpcmUgdGhpcyBzaW5jZQo+ID4g b3RoZXJ3aXNlLCB0aGV5IGVuZCB1cCBnZXR0aW5nIHN0dWNrIGluIGFuIGluZmluaXRlIE1TVCBy ZXRyYWluaW5nIGxvb3AuCj4gPiAKPiA+IE1TVCByZXRyYWluaW5nIGlzIHNvbWV3aGF0IGRpZmZl cmVudCB0aGVuIFNTVCByZXRyYWluaW5nLiBXaGlsZSBpdCdzCj4gPiBwb3NzaWJsZSBkdXJpbmcg dGhlIG5vcm1hbCBsaW5rIHJldHJhaW5pbmcgc2VxdWVuY2UgZm9yIGEgaHViIHRvIGluZGljYXRl Cj4gPiBiYWQgbGluayBzdGF0dXMsIGl0J3MgYWxzbyBwb3NzaWJsZSBmb3IgYSBodWIgdG8gb25s eSBpbmRpY2F0ZSB0aGlzCj4gPiBzdGF0dXMgdGhyb3VnaCBFU0kgbWVzc2FnZXMgYW5kIGl0J3Mg cG9zc2libGUgZm9yIHRoaXMgdG8gaGFwcGVuIGFmdGVyCj4gPiB0aGUgaW5pdGlhbCBsaW5rIHRy YWluaW5nIHN1Y2NlZWRzLiBUaGlzIGNhbiBsZWFkIHRvIGEgcGF0dGVybiB0aGF0Cj4gPiBsb29r cyBsaWtlIHRoaXM6Cj4gPiAKPiA+IC0gVHJhaW4gTVNUIGxpbmsKPiA+IC0gVHJhaW5pbmcgY29t cGxldGVzIHN1Y2Nlc3NmdWxseQo+ID4gLSBNU1QgaHViIHNldHMgQ2hhbm5lbCBFUSBmYWlsZWQg Yml0IGluIEVTSQo+ID4gLSBSZXRyYWluaW5nIHN0YXJ0cwo+ID4gLSBSZXRyYWluaW5nIGNvbXBs ZXRlcyBzdWNjZXNzZnVsbHkKPiA+IC0gTVNUIGh1YiBzZXRzIENoYW5uZWwgRVEgZmFpbGVkIGJp dCBpbiBFU0kgYWdhaW4KPiA+IC0gUmluc2UgYW5kIHJlcGVhdAo+ID4gCj4gPiBJbiB0aGVzZSBz aXR1YXRpb25zLCB3ZSBuZWVkIHRvIGJlIGFibGUgdG8gYWN0dWFsbHkgdHJpZ2dlciBmYWxsYmFj awo+ID4gbGluayB0cmFpbmluZyBmcm9tIHRoZSBFU0kgaGFuZGxlciBhcyB3ZWxsLCBhbG9uZyB3 aXRoIHVzaW5nIHRoZSBFU0kKPiA+IGhhbmRsZXIgZHVyaW5nIHJldHJhaW5pbmcgdG8gZmlndXJl IG91dCB3aGV0aGVyIG9yIG5vdCBvdXIgcmV0cmFpbmluZwo+ID4gYWN0dWFsbHkgc3VjY2VlZGVk Lgo+ID4gCj4gPiBUaGlzIGdldHMgYSBiaXQgbW9yZSBjb21wbGljYXRlZCBzaW5jZSB3ZSBoYXZl IHRvIGVuc3VyZSB0aGF0IHdlIGRvbid0Cj4gPiBibG9jayB0aGUgRVNJIGhhbmRsZXIgYXQgYWxs IHdoaWxlIGRvaW5nIHJldHJhaW5pbmcuIElmIHdlIGRvLCBkdWUgdG8KPiA+IERpc3BsYXlQb3J0 J3MgZ2VuZXJhbCBpc3N1ZXMgd2l0aCBiZWluZyBzZW5zaXRpdmUgdG8gSVJRIGxhdGVuY3kgbW9z dAo+ID4gTVNUIGh1YnMgd2lsbCBqdXN0IHN0b3AgcmVzcG9uZGluZyB0byB1cyBpZiB0aGVpciBp bnRlcnJ1cHRzIGFyZW4ndAo+ID4gaGFuZGxlZCBpbiBhIHRpbWVseSBtYW5uZXIuCj4gPiAKPiA+ IFNvOiBtb3ZlIHJldHJhaW5pbmcgaW50byBpdCdzIG93biBzZXBlcmF0ZSBoYW5kbGVyLiBSdW5u aW5nIGluIGEKPiA+IHNlcGVyYXRlIGhhbmRsZXIgYWxsb3dzIHVzIHRvIGF2b2lkIHN0YWxsaW5n IHRoZSBFU0kgZHVyaW5nIGxpbmsKPiA+IHJldHJhaW5pbmcsIGFuZCB3ZSBjYW4gaGF2ZSB0aGUg RVNJIHNpZ25hbCB0aGF0IHRoZSBjaGFubmVsIEVRIGJpdCB3YXMKPiA+IGNsZWFyZWQgdGhyb3Vn aCBhIHNpbXBsZSBjb21wbGV0aW9uIHN0cnVjdC4gQWRkaXRpb25hbGx5LCB3ZSB0YWtlIGNhcmUK PiA+IHRvIHN0aWNrIGFzIG11Y2ggb2YgdGhpcyBpbnRvIHRoZSBTU1QgcmV0cmFpbmluZyBwYXRo IGFzIHBvc3NpYmxlIHNpbmNlCj4gPiBzaGFyaW5nIGlzIGNhcmluZy4KPiA+IAo+IAo+IFRoYW5r cyBmb3IgdGhlIHBhdGNoIGZvciBNU1QgcmV0cmFpbmluZy4gU28ganVzdCB0byBjb25maXJtIG15 IHVuZGVyc3RhbmRpbmcKPiBvZiB0aGUKPiBjYXNlcyB3aGVyZSBNUyByZXRyYWluaW5nIGlzIGhh bmRsZWQ6Cj4gMS4gT24gbGluayB0aGUgZmlyc3QgbGluayB0cmFpbmluZyBmYWlsdXJlIGR1cmlu ZyB0aGUgbW9kZXNldCwgdGhpcyB3b3VsZAo+IGp1c3QKPiB1c2UgU1NUIG1vZGVzZXQgcmV0cnkg ZnVuY3Rpb24gYW5kIHNldCB0aGUgbGluayBzdGF0dXMgdG8gQkFEIHRocm91Z2gKPiBkcm1fZHBf bXN0X3RvcG9sb2d5X21ncl9sb3dlcl9saW5rX3JhdGUoKQpUaGlzIHNob3l1bGQgYmUgdGhlICB0 aGUgY2FzZSBmb3IgaHVicyB0aGF0IGFyZSBhIGJpdCBsZXNzIGF3a3dhcmQgdGhlbiBtaW5lLgpJ IGhhdmVuJ3QgYWN0dWFsbHkgc2VlbiB0aGUgbGluayB0cmFpbmluZyBmYWlsIGR1cmluZyB0aGUg aW5pdGlhbCBtb2Rlc2V0IG9uY2UKb24gbXkgc2V0dXAgaGVyZSwgb25seSB0aGUgY2hhbm5lbCBF USBiaXQgaW4gdGhlIEVTSSBoYW5kbGVyIGV2ZXIgc2VlbXMgdG8gZ2V0CnNldC4KPiAKPiAyLiBJ biBjYXNlIHRoYXQgaXQgc3VjZWVkcyBoZXJlIGJ1dCB0aGVuIGxvc2VzIHN5bmNocm9uaXphdGlv biBpbiBiZXR3ZWVuLAo+IHRoYXQgdGltZSBpdCB3aWxsIHNlbmQgSVJRX0hQRCBhbmQKPiBpbmRp Y2F0ZSB0aGlzIHRocm91Z2ggRVNJIGFuZCB0aGUgd2F5IGl0cyBoYW5kbGVkIGlzIHRocm91Z2gK PiBpbnRlbF9kcF9tc3RfY2hlY2tfbGlua19zdGF0dXMoKSBhbmQgdGhlbiB0aHJvdWdoCj4gdGhl IHNlcGFyYXRlIG1zdF9yZXRyYWluX2xpbmsgd29yay4gQW5kIHRoaXMgdGltZSB3ZSBmaXJzdCB0 cnkgdG8gcmV0cmFpbiBhdAo+IHRoZSBjdXJyZW50IHZhbHVlcyBmb3IgNSB0aW1lcyBhbmQKPiB0 aGVuIGZhbGxiYWNrIGFuZCByZXRyeSBieSBzZW5kaW5nIGhvdHBsdWcgdWV2ZW50LgpZZXMuIEFz IHdlbGwsIHRoZXJlJ3MgdHdvIHdheXMgd2UgY291bGQgcnVuIGludG8gYSBzaXR1YXRpb24gdGhh dCB3b3VsZCBjb3VudAphcyBhIGZhaWx1cmU6CgogKiAoTm90ZSwgdGhpcyBkb2Vzbid0IGhhcHBl biBiZWNhdXNlIEkgZm9yZ290IHRvIGluY2x1ZGUgaXQgaW4gdGhpcyBwYXRjaAogICBzZXJpZXMs IGJ1dCBpdCdsbCBiZSBmaXhlZCBpbiB0aGUgbmV4dCByZXZpc2lvbikgSWYgdGhlIGh1YiBkb2Vz IGV2ZXJ5dGhpbmcKICAgaXQncyBzdXBwb3NlZCB0byBhbmQgYWN0dWFsbHkgcmVwb3J0cyB0aGUg bGluayB0cmFpbmluZyBzdGF0dXMgYXMgZmFpbGluZwogICB0aHJvdWdoIHRoZSByZWdpc3RlcnMg dGhhdCBpbnRlbF9kcF9zdGFydF9saW5rX3RyYWluKCkgcmVsaWVzIG9uLCB0aGVuCiAgIGludGVs X2RwX3N0YXJ0X2xpbmtfdHJhaW4oKSB3aWxsIHRyeSBmaXZlIHRpbWVzOyBmYWlsOyBhbmQgdGhl biB3ZSdsbCBza2lwCiAgIGFueSBhZGRpdGlvbmFsIGF0dGVtcHRzIGluIGludGVsX2RwX3JldHJh aW5fbGluaygpIGFuZCBzdGFydCB0aGUgbW9kZXNldAogICByZXRyeSB3b3JrLgogKiBJZiB0aGUg aHViIGRvZXNuJ3QgZG8gZXZlcnl0aGluZyB0aGF0IGl0J3Mgc3VwcG9zZWQgdG8gbGlrZSBtaW5l IGRvZXMgYW5kCiAgIG9ubHkgcmVwb3J0cyBjaGFubmVsIEVRIGZhaWx1cmVzIHRocm91Z2ggdGhl IEVTSSBoYW5kbGVyLCB3ZSdsbCBlbmQgdXAKICAgc3VjY2Vzc2Z1bGx5IGxpbmsgdHJhaW5pbmc7 IHRpbWUgb3V0IHdhaXRpbmcgZm9yIHRoZSBFU0kgaGFuZGxlciB0byBzaWduYWwKICAgdGhyb3Vn aCBtc3RfcmV0cmFpbl9jb21wbGV0aW9uIHRoYXQgdGhlIGNoYW5uZWwgRVEgYml0IGhhcyBiZWVu IGNsZWFyZWQsCiAgIGFuZCByZXBlYXQgZml2ZSB0aW1lcyB1bnRpbCB3ZSBnaXZlIHVwIGFuZCBm YWxsIGJhY2sgdG8gYSBsb3dlciBsaW5rIHJhdGUKICAgd2l0aCB0aGUgbW9kZXNldCByZXRyeSB3 b3JrLgoKPiAKPiBJcyB0aGlzIGNvcnJlY3Q/Cj4gCj4gTWFuYXNpCj4gCj4gPiBTaWduZWQtb2Zm LWJ5OiBMeXVkZSBQYXVsIDxseXVkZUByZWRoYXQuY29tPgo+ID4gQ2M6IE1hbmFzaSBOYXZhcmUg PG1hbmFzaS5kLm5hdmFyZUBpbnRlbC5jb20+Cj4gPiBDYzogVmlsbGUgU3lyasOkbMOkIDx2aWxs ZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPiA+IC0tLQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9p OTE1L2ludGVsX2RwLmMgICAgIHwgMzQyICsrKysrKysrKysrKysrKysrKysrKysrKysrKy0tCj4g PiAtLS0tLS0tCj4gPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHBfbXN0LmMgfCAgNDIg KysrKy0KPiA+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaCAgICB8ICAgOCArCj4g PiAgMyBmaWxlcyBjaGFuZ2VkLCAzMDIgaW5zZXJ0aW9ucygrKSwgOTAgZGVsZXRpb25zKC0pCj4g PiAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcC5jCj4gPiBi L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2RwLmMKPiA+IGluZGV4IDU2NDVhMTk0ZGU5Mi4u NzYyNjY1MjczMmI2IDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxf ZHAuYwo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYwo+ID4gQEAgLTQ1 LDYgKzQ1LDggQEAKPiA+ICAKPiA+ICAjZGVmaW5lIERQX0RQUlhfRVNJX0xFTiAxNAo+ID4gIAo+ ID4gKyNkZWZpbmUgRFBfTVNUX1JFVFJBSU5fVElNRU9VVCAobXNlY3NfdG9famlmZmllcygxMDAp KQo+ID4gKwo+ID4gIC8qIENvbXBsaWFuY2UgdGVzdCBzdGF0dXMgYml0cyAgKi8KPiA+ICAjZGVm aW5lIElOVEVMX0RQX1JFU09MVVRJT05fU0hJRlRfTUFTSwkwCj4gPiAgI2RlZmluZSBJTlRFTF9E UF9SRVNPTFVUSU9OX1BSRUZFUlJFRAkoMSA8PAo+ID4gSU5URUxfRFBfUkVTT0xVVElPTl9TSElG VF9NQVNLKQo+ID4gQEAgLTQyMjQsNiArNDIyNiwxMTggQEAgc3RhdGljIHZvaWQgaW50ZWxfZHBf aGFuZGxlX3Rlc3RfcmVxdWVzdChzdHJ1Y3QKPiA+IGludGVsX2RwICppbnRlbF9kcCkKPiA+ICAJ CURSTV9ERUJVR19LTVMoIkNvdWxkIG5vdCB3cml0ZSB0ZXN0IHJlc3BvbnNlIHRvIHNpbmtcbiIp Owo+ID4gIH0KPiA+ICAKPiA+ICsvKiBHZXQgYSBtYXNrIG9mIHRoZSBDUlRDcyB0aGF0IGFyZSBy dW5uaW5nIG9uIHRoZSBnaXZlbiBpbnRlbF9kcCBzdHJ1Y3QuCj4gPiBGb3IKPiA+ICsgKiBNU1Qs IHRoaXMgcmV0dXJucyBhIGNydGMgbWFzayBjb250YWluaW5nIGFsbCBvZiB0aGUgQ1JUQ3MgZHJp dmluZwo+ID4gKyAqIGRvd25zdHJlYW0gc2lua3MsIGZvciBTU1QgaXQganVzdCByZXR1cm5zIGEg bWFzayBvZiB0aGUgYXR0YWNoZWQKPiA+ICsgKiBjb25uZWN0b3IncyBDUlRDLgo+ID4gKyAqLwo+ ID4gK2ludAo+ID4gK2ludGVsX2RwX2dldF9jcnRjX21hc2soc3RydWN0IGludGVsX2RwICppbnRl bF9kcCkKPiA+ICt7Cj4gPiArCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBkcF90b19kaWdfcG9y dChpbnRlbF9kcCktPmJhc2UuYmFzZS5kZXY7Cj4gPiArCXN0cnVjdCBkcm1fY29ubmVjdG9yICpj b25uZWN0b3I7Cj4gPiArCXN0cnVjdCBkcm1fY29ubmVjdG9yX3N0YXRlICpjb25uX3N0YXRlOwo+ ID4gKwlzdHJ1Y3QgaW50ZWxfY29ubmVjdG9yICppbnRlbF9jb25uZWN0b3I7Cj4gPiArCXN0cnVj dCBkcm1fY3J0YyAqY3J0YzsKPiA+ICsJaW50IGNydGNfbWFzayA9IDA7Cj4gPiArCj4gPiArCVdB Uk5fT04oIWRybV9tb2Rlc2V0X2lzX2xvY2tlZCgmZGV2LQo+ID4gPm1vZGVfY29uZmlnLmNvbm5l Y3Rpb25fbXV0ZXgpKTsKPiA+ICsKPiA+ICsJaWYgKGludGVsX2RwLT5pc19tc3QpIHsKPiA+ICsJ CXN0cnVjdCBkcm1fY29ubmVjdG9yX2xpc3RfaXRlciBjb25uX2l0ZXI7Cj4gPiArCj4gPiArCQlk cm1fY29ubmVjdG9yX2xpc3RfaXRlcl9iZWdpbihkZXYsICZjb25uX2l0ZXIpOwo+ID4gKwkJZm9y X2VhY2hfaW50ZWxfY29ubmVjdG9yX2l0ZXIoaW50ZWxfY29ubmVjdG9yLAo+ID4gJmNvbm5faXRl cikgewo+ID4gKwkJCWlmIChpbnRlbF9jb25uZWN0b3ItPm1zdF9wb3J0ICE9IGludGVsX2RwKQo+ ID4gKwkJCQljb250aW51ZTsKPiA+ICsKPiA+ICsJCQljb25uX3N0YXRlID0gaW50ZWxfY29ubmVj dG9yLT5iYXNlLnN0YXRlOwo+ID4gKwkJCWlmICghY29ubl9zdGF0ZS0+Y3J0YykKPiA+ICsJCQkJ Y29udGludWU7Cj4gPiArCj4gPiArCQkJY3J0Y19tYXNrIHw9IGRybV9jcnRjX21hc2soY29ubl9z dGF0ZS0+Y3J0Yyk7Cj4gPiArCQl9Cj4gPiArCQlkcm1fY29ubmVjdG9yX2xpc3RfaXRlcl9lbmQo JmNvbm5faXRlcik7Cj4gPiArCX0gZWxzZSB7Cj4gPiArCQljb25uZWN0b3IgPSAmaW50ZWxfZHAt PmF0dGFjaGVkX2Nvbm5lY3Rvci0+YmFzZTsKPiA+ICsJCWNydGMgPSBjb25uZWN0b3ItPnN0YXRl LT5jcnRjOwo+ID4gKwo+ID4gKwkJaWYgKGNydGMpCj4gPiArCQkJY3J0Y19tYXNrIHw9IGRybV9j cnRjX21hc2soY3J0Yyk7Cj4gPiArCX0KPiA+ICsKPiA+ICsJcmV0dXJuIGNydGNfbWFzazsKPiA+ ICt9Cj4gPiArCj4gPiArc3RhdGljIGJvb2wKPiA+ICtpbnRlbF9kcF9uZWVkc19saW5rX3JldHJh aW4oc3RydWN0IGludGVsX2RwICppbnRlbF9kcCwKPiA+ICsJCQkgICAgY29uc3QgdTggZXNpW0RQ X0RQUlhfRVNJX0xFTl0pCj4gPiArewo+ID4gKwl1OCBidWZbbWF4KERQX0xJTktfU1RBVFVTX1NJ WkUsIERQX0RQUlhfRVNJX0xFTildOwo+ID4gKwljb25zdCB1OCAqbGlua19zdGF0dXMgPSBOVUxM Owo+ID4gKwo+ID4gKwlpZiAoaW50ZWxfZHAtPmlzX21zdCkgewo+ID4gKwkJaWYgKCFpbnRlbF9k cC0+YWN0aXZlX21zdF9saW5rcykKPiA+ICsJCQlyZXR1cm4gZmFsc2U7Cj4gPiArCQlpZiAoaW50 ZWxfZHAtPm1zdF9saW5rX2lzX2JhZCkKPiA+ICsJCQlyZXR1cm4gZmFsc2U7Cj4gPiArCj4gPiAr CQlpZiAoZXNpKSB7Cj4gPiArCQkJbGlua19zdGF0dXMgPSAmZXNpWzEwXTsKPiA+ICsJCX0gZWxz ZSB7Cj4gPiArCQkJLyogV2UncmUgbm90IHJ1bm5pbmcgZnJvbSB0aGUgRVNJIGhhbmRsZXIsIHNv Cj4gPiB3YWl0IGEKPiA+ICsJCQkgKiBsaXR0bGUgYml0IHRvIHNlZSBpZiB0aGUgRVNJIGhhbmRs ZXIgbGV0cyB1cwo+ID4ga25vdwo+ID4gKwkJCSAqIHRoYXQgdGhlIGxpbmsgc3RhdHVzIGlzIE9L Cj4gPiArCQkJICovCj4gPiArCQkJaWYgKHdhaXRfZm9yX2NvbXBsZXRpb25fdGltZW91dCgKPiA+ ICsJCQkJJmludGVsX2RwLT5tc3RfcmV0cmFpbl9jb21wbGV0aW9uLAo+ID4gKwkJCQlEUF9NU1Rf UkVUUkFJTl9USU1FT1VUKSkKPiA+ICsJCQkJcmV0dXJuIGZhbHNlOwo+ID4gKwkJfQo+ID4gKwl9 IGVsc2Ugewo+ID4gKwkJaWYgKGludGVsX2RwLT5saW5rX3RyYWluZWQpCj4gPiArCQkJcmV0dXJu IGZhbHNlOwo+ID4gKwkJaWYgKCFpbnRlbF9kcF9nZXRfbGlua19zdGF0dXMoaW50ZWxfZHAsIGJ1 ZikpCj4gPiArCQkJcmV0dXJuIGZhbHNlOwo+ID4gKwo+ID4gKwkJbGlua19zdGF0dXMgPSBidWY7 Cj4gPiArCX0KPiA+ICsKPiA+ICsJLyoKPiA+ICsJICogVmFsaWRhdGUgdGhlIGNhY2hlZCB2YWx1 ZXMgb2YgaW50ZWxfZHAtPmxpbmtfcmF0ZSBhbmQKPiA+ICsJICogaW50ZWxfZHAtPmxhbmVfY291 bnQgYmVmb3JlIGF0dGVtcHRpbmcgdG8gcmV0cmFpbi4KPiA+ICsJICovCj4gPiArCWlmICghaW50 ZWxfZHBfbGlua19wYXJhbXNfdmFsaWQoaW50ZWxfZHAsIGludGVsX2RwLT5saW5rX3JhdGUsCj4g PiArCQkJCQlpbnRlbF9kcC0+bGFuZV9jb3VudCkpCj4gPiArCQlyZXR1cm4gZmFsc2U7Cj4gPiAr Cj4gPiArCWlmIChsaW5rX3N0YXR1cykgewo+ID4gKwkJcmV0dXJuICFkcm1fZHBfY2hhbm5lbF9l cV9vayhsaW5rX3N0YXR1cywKPiA+ICsJCQkJCSAgICAgaW50ZWxfZHAtPmxhbmVfY291bnQpOwo+ ID4gKwl9IGVsc2Ugewo+ID4gKwkJcmV0dXJuIHRydWU7Cj4gPiArCX0KPiA+ICt9Cj4gPiArCj4g PiArc3RhdGljIGlubGluZSB2b2lkCj4gPiAraW50ZWxfZHBfbXN0X2NoZWNrX2xpbmtfc3RhdHVz KHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAsCj4gPiArCQkJICAgICAgIGNvbnN0IHU4IGVzaVtE UF9EUFJYX0VTSV9MRU5dKQo+ID4gK3sKPiA+ICsJaWYgKGludGVsX2RwX25lZWRzX2xpbmtfcmV0 cmFpbihpbnRlbF9kcCwgZXNpKSkgewo+ID4gKwkJRFJNX0RFQlVHX0tNUygiQ2hhbm5lbCBFUSBm YWlsaW5nXG4iKTsKPiA+ICsKPiA+ICsJCWlmICghd29ya19idXN5KCZpbnRlbF9kcC0+bXN0X3Jl dHJhaW5fd29yaykpIHsKPiA+ICsJCQlyZWluaXRfY29tcGxldGlvbigmaW50ZWxfZHAtCj4gPiA+ bXN0X3JldHJhaW5fY29tcGxldGlvbik7Cj4gPiArCQkJc2NoZWR1bGVfd29yaygmaW50ZWxfZHAt Pm1zdF9yZXRyYWluX3dvcmspOwo+ID4gKwkJCURSTV9ERUJVR19LTVMoIlJldHJhaW5pbmcgc3Rh cnRlZFxuIik7Cj4gPiArCQl9Cj4gPiArCX0gZWxzZSBpZiAod29ya19idXN5KCZpbnRlbF9kcC0+ bXN0X3JldHJhaW5fd29yaykgJiYKPiA+ICsJCSAgICFjb21wbGV0aW9uX2RvbmUoJmludGVsX2Rw LT5tc3RfcmV0cmFpbl9jb21wbGV0aW9uKSkgewo+ID4gKwkJRFJNX0RFQlVHX0tNUygiQ2hhbm5l bCBFUSBzdGFibGVcbiIpOwo+ID4gKwkJY29tcGxldGVfYWxsKCZpbnRlbF9kcC0+bXN0X3JldHJh aW5fY29tcGxldGlvbik7Cj4gPiArCX0KPiA+ICt9Cj4gPiArCj4gPiAgc3RhdGljIGludAo+ID4g IGludGVsX2RwX2NoZWNrX21zdF9zdGF0dXMoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCkKPiA+ ICB7Cj4gPiBAQCAtNDIzNywxNCArNDM1MSw3IEBAIGludGVsX2RwX2NoZWNrX21zdF9zdGF0dXMo c3RydWN0IGludGVsX2RwCj4gPiAqaW50ZWxfZHApCj4gPiAgCQlicmV0ID0gaW50ZWxfZHBfZ2V0 X3NpbmtfaXJxX2VzaShpbnRlbF9kcCwgZXNpKTsKPiA+ICBnb19hZ2FpbjoKPiA+ICAJCWlmIChi cmV0ID09IHRydWUpIHsKPiA+IC0KPiA+IC0JCQkvKiBjaGVjayBsaW5rIHN0YXR1cyAtIGVzaVsx MF0gPSAweDIwMGMgKi8KPiA+IC0JCQlpZiAoaW50ZWxfZHAtPmFjdGl2ZV9tc3RfbGlua3MgJiYK PiA+IC0JCQkgICAgIWRybV9kcF9jaGFubmVsX2VxX29rKCZlc2lbMTBdLCBpbnRlbF9kcC0KPiA+ ID5sYW5lX2NvdW50KSkgewo+ID4gLQkJCQlEUk1fREVCVUdfS01TKCJjaGFubmVsIEVRIG5vdCBv aywKPiA+IHJldHJhaW5pbmdcbiIpOwo+ID4gLQkJCQlpbnRlbF9kcF9zdGFydF9saW5rX3RyYWlu KGludGVsX2RwKTsKPiA+IC0JCQkJaW50ZWxfZHBfc3RvcF9saW5rX3RyYWluKGludGVsX2RwKTsK PiA+IC0JCQl9Cj4gPiArCQkJaW50ZWxfZHBfbXN0X2NoZWNrX2xpbmtfc3RhdHVzKGludGVsX2Rw LCBlc2kpOwo+ID4gIAo+ID4gIAkJCURSTV9ERUJVR19LTVMoImdvdCBlc2kgJTNwaFxuIiwgZXNp KTsKPiA+ICAJCQlyZXQgPSBkcm1fZHBfbXN0X2hwZF9pcnEoJmludGVsX2RwLT5tc3RfbWdyLCBl c2ksCj4gPiAmaGFuZGxlZCk7Cj4gPiBAQCAtNDI4MSwyOSArNDM4OCw2IEBAIGludGVsX2RwX2No ZWNrX21zdF9zdGF0dXMoc3RydWN0IGludGVsX2RwCj4gPiAqaW50ZWxfZHApCj4gPiAgCXJldHVy biAtRUlOVkFMOwo+ID4gIH0KPiA+ICAKPiA+IC1zdGF0aWMgYm9vbAo+ID4gLWludGVsX2RwX25l ZWRzX2xpbmtfcmV0cmFpbihzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwKQo+ID4gLXsKPiA+IC0J dTggbGlua19zdGF0dXNbRFBfTElOS19TVEFUVVNfU0laRV07Cj4gPiAtCj4gPiAtCWlmICghaW50 ZWxfZHAtPmxpbmtfdHJhaW5lZCkKPiA+IC0JCXJldHVybiBmYWxzZTsKPiA+IC0KPiA+IC0JaWYg KCFpbnRlbF9kcF9nZXRfbGlua19zdGF0dXMoaW50ZWxfZHAsIGxpbmtfc3RhdHVzKSkKPiA+IC0J CXJldHVybiBmYWxzZTsKPiA+IC0KPiA+IC0JLyoKPiA+IC0JICogVmFsaWRhdGUgdGhlIGNhY2hl ZCB2YWx1ZXMgb2YgaW50ZWxfZHAtPmxpbmtfcmF0ZSBhbmQKPiA+IC0JICogaW50ZWxfZHAtPmxh bmVfY291bnQgYmVmb3JlIGF0dGVtcHRpbmcgdG8gcmV0cmFpbi4KPiA+IC0JICovCj4gPiAtCWlm ICghaW50ZWxfZHBfbGlua19wYXJhbXNfdmFsaWQoaW50ZWxfZHAsIGludGVsX2RwLT5saW5rX3Jh dGUsCj4gPiAtCQkJCQlpbnRlbF9kcC0+bGFuZV9jb3VudCkpCj4gPiAtCQlyZXR1cm4gZmFsc2U7 Cj4gPiAtCj4gPiAtCS8qIFJldHJhaW4gaWYgQ2hhbm5lbCBFUSBvciBDUiBub3Qgb2sgKi8KPiA+ IC0JcmV0dXJuICFkcm1fZHBfY2hhbm5lbF9lcV9vayhsaW5rX3N0YXR1cywgaW50ZWxfZHAtPmxh bmVfY291bnQpOwo+ID4gLX0KPiA+IC0KPiA+ICAvKgo+ID4gICAqIElmIGRpc3BsYXkgaXMgbm93 IGNvbm5lY3RlZCBjaGVjayBsaW5rcyBzdGF0dXMsCj4gPiAgICogdGhlcmUgaGFzIGJlZW4ga25v d24gaXNzdWVzIG9mIGxpbmsgbG9zcyB0cmlnZ2VyaW5nCj4gPiBAQCAtNDMxOSw2NCArNDQwMyw3 OCBAQCBpbnRlbF9kcF9uZWVkc19saW5rX3JldHJhaW4oc3RydWN0IGludGVsX2RwCj4gPiAqaW50 ZWxfZHApCj4gPiAgaW50IGludGVsX2RwX3JldHJhaW5fbGluayhzdHJ1Y3QgaW50ZWxfZW5jb2Rl ciAqZW5jb2RlciwKPiA+ICAJCQkgIHN0cnVjdCBkcm1fbW9kZXNldF9hY3F1aXJlX2N0eCAqY3R4 KQo+ID4gIHsKPiA+IC0Jc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gdG9faTkx NShlbmNvZGVyLT5iYXNlLmRldik7Cj4gPiArCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBlbmNv ZGVyLT5iYXNlLmRldjsKPiA+ICsJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0g dG9faTkxNShkZXYpOwo+ID4gIAlzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwID0gZW5jX3RvX2lu dGVsX2RwKCZlbmNvZGVyLT5iYXNlKTsKPiA+IC0Jc3RydWN0IGludGVsX2Nvbm5lY3RvciAqY29u bmVjdG9yID0gaW50ZWxfZHAtPmF0dGFjaGVkX2Nvbm5lY3RvcjsKPiA+IC0Jc3RydWN0IGRybV9j b25uZWN0b3Jfc3RhdGUgKmNvbm5fc3RhdGU7Cj4gPiAtCXN0cnVjdCBpbnRlbF9jcnRjX3N0YXRl ICpjcnRjX3N0YXRlOwo+ID4gLQlzdHJ1Y3QgaW50ZWxfY3J0YyAqY3J0YzsKPiA+ICsJc3RydWN0 IGRybV9jcnRjICpjcnRjOwo+ID4gKwlzdHJ1Y3QgaW50ZWxfY3J0YyAqaW50ZWxfY3J0YzsKPiA+ ICsJaW50IGNydGNfbWFzaywgcmV0cnlfY291bnQgPSAwOwo+ID4gIAlpbnQgcmV0Owo+ID4gIAo+ ID4gLQkvKiBGSVhNRSBoYW5kbGUgdGhlIE1TVCBjb25uZWN0b3JzIGFzIHdlbGwgKi8KPiA+IC0K PiA+IC0JaWYgKCFjb25uZWN0b3IgfHwgY29ubmVjdG9yLT5iYXNlLnN0YXR1cyAhPQo+ID4gY29u bmVjdG9yX3N0YXR1c19jb25uZWN0ZWQpCj4gPiAtCQlyZXR1cm4gMDsKPiA+IC0KPiA+ICAJcmV0 ID0gZHJtX21vZGVzZXRfbG9jaygmZGV2X3ByaXYtCj4gPiA+ZHJtLm1vZGVfY29uZmlnLmNvbm5l Y3Rpb25fbXV0ZXgsCj4gPiAgCQkJICAgICAgIGN0eCk7Cj4gPiAgCWlmIChyZXQpCj4gPiAgCQly ZXR1cm4gcmV0Owo+ID4gIAo+ID4gLQljb25uX3N0YXRlID0gY29ubmVjdG9yLT5iYXNlLnN0YXRl Owo+ID4gLQo+ID4gLQljcnRjID0gdG9faW50ZWxfY3J0Yyhjb25uX3N0YXRlLT5jcnRjKTsKPiA+ IC0JaWYgKCFjcnRjKQo+ID4gLQkJcmV0dXJuIDA7Cj4gPiArCWNydGNfbWFzayA9IGludGVsX2Rw X2dldF9jcnRjX21hc2soaW50ZWxfZHApOwo+ID4gKwlmb3JfZWFjaF9pbnRlbF9jcnRjX21hc2so ZGV2LCBpbnRlbF9jcnRjLCBjcnRjX21hc2spIHsKPiA+ICsJCXN0cnVjdCBkcm1fY3J0Y19zdGF0 ZSAqY3J0Y19zdGF0ZTsKPiA+ICsJCXN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICppbnRlbF9jcnRj X3N0YXRlOwo+ID4gIAo+ID4gLQlyZXQgPSBkcm1fbW9kZXNldF9sb2NrKCZjcnRjLT5iYXNlLm11 dGV4LCBjdHgpOwo+ID4gLQlpZiAocmV0KQo+ID4gLQkJcmV0dXJuIHJldDsKPiA+ICsJCWNydGMg PSAmaW50ZWxfY3J0Yy0+YmFzZTsKPiA+ICsJCXJldCA9IGRybV9tb2Rlc2V0X2xvY2soJmNydGMt Pm11dGV4LCBjdHgpOwo+ID4gKwkJaWYgKHJldCkKPiA+ICsJCQlyZXR1cm4gcmV0Owo+ID4gIAo+ ID4gLQljcnRjX3N0YXRlID0gdG9faW50ZWxfY3J0Y19zdGF0ZShjcnRjLT5iYXNlLnN0YXRlKTsK PiA+ICsJCWNydGNfc3RhdGUgPSBjcnRjLT5zdGF0ZTsKPiA+ICsJCWludGVsX2NydGNfc3RhdGUg PSB0b19pbnRlbF9jcnRjX3N0YXRlKGNydGNfc3RhdGUpOwo+ID4gKwkJV0FSTl9PTighaW50ZWxf Y3J0Y19oYXNfZHBfZW5jb2RlcihpbnRlbF9jcnRjX3N0YXRlKSk7Cj4gPiAgCj4gPiAtCVdBUk5f T04oIWludGVsX2NydGNfaGFzX2RwX2VuY29kZXIoY3J0Y19zdGF0ZSkpOwo+ID4gKwkJaWYgKGNy dGNfc3RhdGUtPmNvbW1pdCAmJgo+ID4gKwkJICAgICF0cnlfd2FpdF9mb3JfY29tcGxldGlvbigm Y3J0Y19zdGF0ZS0+Y29tbWl0LQo+ID4gPmh3X2RvbmUpKQo+ID4gKwkJCXJldHVybiAwOwo+ID4g Kwl9Cj4gPiAgCj4gPiAtCWlmICghY3J0Y19zdGF0ZS0+YmFzZS5hY3RpdmUpCj4gPiArCWlmICgh aW50ZWxfZHBfbmVlZHNfbGlua19yZXRyYWluKGludGVsX2RwLCBOVUxMKSkKPiA+ICAJCXJldHVy biAwOwo+ID4gIAo+ID4gLQlpZiAoY29ubl9zdGF0ZS0+Y29tbWl0ICYmCj4gPiAtCSAgICAhdHJ5 X3dhaXRfZm9yX2NvbXBsZXRpb24oJmNvbm5fc3RhdGUtPmNvbW1pdC0+aHdfZG9uZSkpCj4gPiAt CQlyZXR1cm4gMDsKPiA+ICsJZm9yX2VhY2hfaW50ZWxfY3J0Y19tYXNrKGRldiwgaW50ZWxfY3J0 YywgY3J0Y19tYXNrKSB7Cj4gPiArCQlpbnRlbF9zZXRfY3B1X2ZpZm9fdW5kZXJydW5fcmVwb3J0 aW5nKAo+ID4gKwkJICAgIGRldl9wcml2LCBpbnRlbF9jcnRjLT5waXBlLCBmYWxzZSk7Cj4gPiAg Cj4gPiAtCWlmICghaW50ZWxfZHBfbmVlZHNfbGlua19yZXRyYWluKGludGVsX2RwKSkKPiA+IC0J CXJldHVybiAwOwo+ID4gKwkJaWYgKGludGVsX2NydGMtPmNvbmZpZy0+aGFzX3BjaF9lbmNvZGVy KSB7Cj4gPiArCQkJaW50ZWxfc2V0X3BjaF9maWZvX3VuZGVycnVuX3JlcG9ydGluZygKPiA+ICsJ CQkgICAgZGV2X3ByaXYsCj4gPiBpbnRlbF9jcnRjX3BjaF90cmFuc2NvZGVyKGludGVsX2NydGMp LAo+ID4gKwkJCSAgICBmYWxzZSk7Cj4gPiArCQl9Cj4gPiArCX0KPiA+ICAKPiA+IC0JLyogU3Vw cHJlc3MgdW5kZXJydW5zIGNhdXNlZCBieSByZS10cmFpbmluZyAqLwo+ID4gLQlpbnRlbF9zZXRf Y3B1X2ZpZm9fdW5kZXJydW5fcmVwb3J0aW5nKGRldl9wcml2LCBjcnRjLT5waXBlLAo+ID4gZmFs c2UpOwo+ID4gLQlpZiAoY3J0Yy0+Y29uZmlnLT5oYXNfcGNoX2VuY29kZXIpCj4gPiAtCQlpbnRl bF9zZXRfcGNoX2ZpZm9fdW5kZXJydW5fcmVwb3J0aW5nKGRldl9wcml2LAo+ID4gLQkJCQkJCSAg ICAgIGludGVsX2NydGNfcGNoX3RyYW4KPiA+IHNjb2RlcihjcnRjKSwgZmFsc2UpOwo+ID4gKwlk byB7Cj4gPiArCQlpZiAoKytyZXRyeV9jb3VudCA+IDUpIHsKPiA+ICsJCQlEUk1fREVCVUdfS01T KCJUb28gbWFueSByZXRyaWVzLCBjYW4ndAo+ID4gcmV0cmFpblxuIik7Cj4gPiArCQkJcmV0dXJu IC1FSU5WQUw7Cj4gPiArCQl9Cj4gPiAgCj4gPiAtCWludGVsX2RwX3N0YXJ0X2xpbmtfdHJhaW4o aW50ZWxfZHApOwo+ID4gLQlpbnRlbF9kcF9zdG9wX2xpbmtfdHJhaW4oaW50ZWxfZHApOwo+ID4g KwkJaW50ZWxfZHBfc3RhcnRfbGlua190cmFpbihpbnRlbF9kcCk7Cj4gPiArCQlpbnRlbF9kcF9z dG9wX2xpbmtfdHJhaW4oaW50ZWxfZHApOwo+ID4gKwl9IHdoaWxlIChpbnRlbF9kcF9uZWVkc19s aW5rX3JldHJhaW4oaW50ZWxfZHAsIE5VTEwpKTsKPiA+ICsKPiA+ICsJLyogV2FpdCBmb3IgdGhp bmdzIHRvIGJlY29tZSBzdGFibGUgKi8KPiA+ICsJZm9yX2VhY2hfaW50ZWxfY3J0Y19tYXNrKGRl diwgaW50ZWxfY3J0YywgY3J0Y19tYXNrKQo+ID4gKwkJaW50ZWxfd2FpdF9mb3JfdmJsYW5rKGRl dl9wcml2LCBpbnRlbF9jcnRjLT5waXBlKTsKPiA+ICAKPiA+IC0JLyogS2VlcCB1bmRlcnJ1biBy ZXBvcnRpbmcgZGlzYWJsZWQgdW50aWwgdGhpbmdzIGFyZSBzdGFibGUgKi8KPiA+IC0JaW50ZWxf d2FpdF9mb3JfdmJsYW5rKGRldl9wcml2LCBjcnRjLT5waXBlKTsKPiA+ICsJLyogTm93IHRoYXQg d2Uga25vdyBldmVyeXRoaW5nIGlzIE9LLCBmaW5hbGx5IHJlLWVuYWJsZSB1bmRlcnJ1bgo+ID4g KwkgKiByZXBvcnRpbmcgKi8KPiA+ICsJZm9yX2VhY2hfaW50ZWxfY3J0Y19tYXNrKGRldiwgaW50 ZWxfY3J0YywgY3J0Y19tYXNrKSB7Cj4gPiArCQlpbnRlbF9zZXRfY3B1X2ZpZm9fdW5kZXJydW5f cmVwb3J0aW5nKAo+ID4gKwkJICAgIGRldl9wcml2LCBpbnRlbF9jcnRjLT5waXBlLCB0cnVlKTsK PiA+ICAKPiA+IC0JaW50ZWxfc2V0X2NwdV9maWZvX3VuZGVycnVuX3JlcG9ydGluZyhkZXZfcHJp diwgY3J0Yy0+cGlwZSwKPiA+IHRydWUpOwo+ID4gLQlpZiAoY3J0Yy0+Y29uZmlnLT5oYXNfcGNo X2VuY29kZXIpCj4gPiAtCQlpbnRlbF9zZXRfcGNoX2ZpZm9fdW5kZXJydW5fcmVwb3J0aW5nKGRl dl9wcml2LAo+ID4gLQkJCQkJCSAgICAgIGludGVsX2NydGNfcGNoX3RyYW4KPiA+IHNjb2Rlcihj cnRjKSwgdHJ1ZSk7Cj4gPiArCQlpZiAoaW50ZWxfY3J0Yy0+Y29uZmlnLT5oYXNfcGNoX2VuY29k ZXIpIHsKPiA+ICsJCQlpbnRlbF9zZXRfcGNoX2ZpZm9fdW5kZXJydW5fcmVwb3J0aW5nKAo+ID4g KwkJCSAgICBkZXZfcHJpdiwKPiA+IGludGVsX2NydGNfcGNoX3RyYW5zY29kZXIoaW50ZWxfY3J0 YyksCj4gPiArCQkJICAgIHRydWUpOwo+ID4gKwkJfQo+ID4gKwl9Cj4gPiAgCj4gPiAgCXJldHVy biAwOwo+ID4gIH0KPiA+IEBAIC00NDAyLDYgKzQ1MDAsMTAgQEAgc3RhdGljIGJvb2wgaW50ZWxf ZHBfaG90cGx1ZyhzdHJ1Y3QgaW50ZWxfZW5jb2Rlcgo+ID4gKmVuY29kZXIsCj4gPiAgCj4gPiAg CWNoYW5nZWQgPSBpbnRlbF9lbmNvZGVyX2hvdHBsdWcoZW5jb2RlciwgY29ubmVjdG9yKTsKPiA+ ICAKPiA+ICsJLyogV2UgZG9uJ3Qgd2FudCB0byBlbmQgdXAgdHJ5aW5nIHRvIHJldHJhaW4gTVNU IGxpbmtzISAqLwo+ID4gKwlpZiAoZW5jb2RlciAmJiBlbmNfdG9faW50ZWxfZHAoJmVuY29kZXIt PmJhc2UpLT5pc19tc3QpCj4gPiArCQlyZXR1cm4gY2hhbmdlZDsKPiA+ICsKPiA+ICAJZHJtX21v ZGVzZXRfYWNxdWlyZV9pbml0KCZjdHgsIDApOwo+ID4gIAo+ID4gIAlmb3IgKDs7KSB7Cj4gPiBA QCAtNDQ3OCw3ICs0NTgwLDcgQEAgaW50ZWxfZHBfc2hvcnRfcHVsc2Uoc3RydWN0IGludGVsX2Rw ICppbnRlbF9kcCkKPiA+ICAJfQo+ID4gIAo+ID4gIAkvKiBkZWZlciB0byB0aGUgaG90cGx1ZyB3 b3JrIGZvciBsaW5rIHJldHJhaW5pbmcgaWYgbmVlZGVkICovCj4gPiAtCWlmIChpbnRlbF9kcF9u ZWVkc19saW5rX3JldHJhaW4oaW50ZWxfZHApKQo+ID4gKwlpZiAoaW50ZWxfZHBfbmVlZHNfbGlu a19yZXRyYWluKGludGVsX2RwLCBOVUxMKSkKPiA+ICAJCXJldHVybiBmYWxzZTsKPiA+ICAKPiA+ ICAJaWYgKGludGVsX2RwLT5jb21wbGlhbmNlLnRlc3RfdHlwZSA9PSBEUF9URVNUX0xJTktfVFJB SU5JTkcpIHsKPiA+IEBAIC02MjY2LDI1ICs2MzY4LDk4IEBAIHN0YXRpYyBib29sIGludGVsX2Vk cF9pbml0X2Nvbm5lY3RvcihzdHJ1Y3QKPiA+IGludGVsX2RwICppbnRlbF9kcCwKPiA+ICAJcmV0 dXJuIGZhbHNlOwo+ID4gIH0KPiA+ICAKPiA+ICtzdGF0aWMgdm9pZCBpbnRlbF9kcF9tc3RfcmV0 cmFpbl9saW5rX3dvcmsoc3RydWN0IHdvcmtfc3RydWN0ICp3b3JrKQo+ID4gK3sKPiA+ICsJc3Ry dWN0IGRybV9tb2Rlc2V0X2FjcXVpcmVfY3R4IGN0eDsKPiA+ICsJc3RydWN0IGludGVsX2RwICpp bnRlbF9kcCA9IGNvbnRhaW5lcl9vZih3b3JrLCB0eXBlb2YoKmludGVsX2RwKSwKPiA+ICsJCQkJ CQkgbXN0X3JldHJhaW5fd29yayk7Cj4gPiArCXN0cnVjdCBpbnRlbF9lbmNvZGVyICppbnRlbF9l bmNvZGVyID0gJmRwX3RvX2RpZ19wb3J0KGludGVsX2RwKS0KPiA+ID5iYXNlOwo+ID4gKwlzdHJ1 Y3QgZHJtX2RldmljZSAqZGV2ID0gaW50ZWxfZW5jb2Rlci0+YmFzZS5kZXY7Cj4gPiArCWludCBy ZXQ7Cj4gPiArCWJvb2wgaGFkX2Vycm9yID0gZmFsc2U7Cj4gPiArCj4gPiArCWRybV9tb2Rlc2V0 X2FjcXVpcmVfaW5pdCgmY3R4LCAwKTsKPiA+ICsKPiA+ICsJZm9yICg7Oykgewo+ID4gKwkJcmV0 ID0gaW50ZWxfZHBfcmV0cmFpbl9saW5rKGludGVsX2VuY29kZXIsICZjdHgpOwo+ID4gKwkJaWYg KHJldCA9PSAtRURFQURMSykgewo+ID4gKwkJCWRybV9tb2Rlc2V0X2JhY2tvZmYoJmN0eCk7Cj4g PiArCQkJY29udGludWU7Cj4gPiArCQl9Cj4gPiArCj4gPiArCQlicmVhazsKPiA+ICsJfQo+ID4g KwlpZiAoIXJldCkgewo+ID4gKwkJRFJNX0RFQlVHX0tNUygiUmV0cmFpbiBjb21wbGV0ZVxuIik7 Cj4gPiArCQlnb3RvIG91dDsKPiA+ICsJfSBlbHNlIGlmIChyZXQgPT0gLUVJTykgewo+ID4gKwkJ RFJNX0VSUk9SKCJJTyBlcnJvciB3aXRoIHNpbmsgZHVyaW5nIHJldHJhaW4/Cj4gPiBBYm9ydGlu Z1xuIik7Cj4gPiArCQloYWRfZXJyb3IgPSB0cnVlOwo+ID4gKwkJZ290byBvdXQ7Cj4gPiArCX0K PiA+ICsKPiA+ICsJRFJNX0RFQlVHX0tNUygiUmV0cmFpbmluZyBmYWlsZWQgd2l0aCAlZCwgbWFy a2luZyBsaW5rIHN0YXR1cyBhcwo+ID4gYmFkXG4iLAo+ID4gKwkJICAgICAgcmV0KTsKPiA+ICsK PiA+ICsJLyogV2UgcmFuIG91dCBvZiByZXRyaWVzLCBpZiB0aGUgc2luayBoYXNuJ3QgY2hhbmdl ZCB0aGUgbGluawo+ID4gcmF0ZSBpbgo+ID4gKwkgKiBpdCdzIGRwY2QgeWV0IGZvcmNlIHVzIHRv IGZhbGxiYWNrIHRvIGEgbG93ZXIgbGluayByYXRlL2NvdW50Cj4gPiAqLwo+ID4gKwlpZiAocmV0 ID09IC1FSU5WQUwpIHsKPiA+ICsJCXJldCA9IGludGVsX2RwX2dldF9kcGNkKGludGVsX2RwKTsK PiA+ICsJCWlmICghcmV0KSB7Cj4gPiArCQkJRFJNX0VSUk9SKCJJTyBlcnJvciB3aGlsZSByZWFk aW5nIGRwY2QgZnJvbQo+ID4gc2lua1xuIik7Cj4gPiArCQkJaGFkX2Vycm9yID0gdHJ1ZTsKPiA+ ICsJCQlnb3RvIG91dDsKPiA+ICsJCX0KPiA+ICsKPiA+ICsJCWlmIChpbnRlbF9kcC0+bGlua19y YXRlID09Cj4gPiBpbnRlbF9kcF9tYXhfbGlua19yYXRlKGludGVsX2RwKSAmJgo+ID4gKwkJICAg IGludGVsX2RwLT5sYW5lX2NvdW50ID09Cj4gPiBpbnRlbF9kcF9tYXhfbGFuZV9jb3VudChpbnRl bF9kcCkpIHsKPiA+ICsJCQlpbnRlbF9kcF9nZXRfbGlua190cmFpbl9mYWxsYmFja192YWx1ZXMo Cj4gPiArCQkJICAgIGludGVsX2RwLCBpbnRlbF9kcF9tYXhfbGlua19yYXRlKGludGVsX2RwKSwK PiA+ICsJCQkgICAgaW50ZWxfZHBfbWF4X2xhbmVfY291bnQoaW50ZWxfZHApKTsKPiA+ICsJCX0K PiA+ICsJfQo+ID4gKwo+ID4gKwlpbnRlbF9kcC0+bXN0X2xpbmtfaXNfYmFkID0gdHJ1ZTsKPiA+ ICsJaW50ZWxfZHAtPm1zdF9id19sb2NrZWQgPSBmYWxzZTsKPiA+ICsJc2NoZWR1bGVfd29yaygm aW50ZWxfZHAtPm1vZGVzZXRfcmV0cnlfd29yayk7Cj4gPiArb3V0Ogo+ID4gKwlkcm1fbW9kZXNl dF9kcm9wX2xvY2tzKCZjdHgpOwo+ID4gKwlkcm1fbW9kZXNldF9hY3F1aXJlX2ZpbmkoJmN0eCk7 Cj4gPiArCWlmIChoYWRfZXJyb3IpCj4gPiArCQlkcm1fa21zX2hlbHBlcl9ob3RwbHVnX2V2ZW50 KGRldik7Cj4gPiArfQo+ID4gKwo+ID4gIHN0YXRpYyB2b2lkIGludGVsX2RwX21vZGVzZXRfcmV0 cnlfd29ya19mbihzdHJ1Y3Qgd29ya19zdHJ1Y3QgKndvcmspCj4gPiAgewo+ID4gIAlzdHJ1Y3Qg aW50ZWxfZHAgKmludGVsX2RwID0gY29udGFpbmVyX29mKHdvcmssIHR5cGVvZigqaW50ZWxfZHAp LAo+ID4gIAkJCQkJCSBtb2Rlc2V0X3JldHJ5X3dvcmspOwo+ID4gLQlzdHJ1Y3QgZHJtX2Nvbm5l Y3RvciAqY29ubmVjdG9yID0gJmludGVsX2RwLT5hdHRhY2hlZF9jb25uZWN0b3ItCj4gPiA+YmFz ZTsKPiA+ICsJc3RydWN0IGludGVsX2RpZ2l0YWxfcG9ydCAqaW50ZWxfZGlnX3BvcnQgPQo+ID4g ZHBfdG9fZGlnX3BvcnQoaW50ZWxfZHApOwo+ID4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0g aW50ZWxfZGlnX3BvcnQtPmJhc2UuYmFzZS5kZXY7Cj4gPiArCXN0cnVjdCBkcm1fY29ubmVjdG9y ICpjb25uZWN0b3I7Cj4gPiAgCj4gPiAtCURSTV9ERUJVR19LTVMoIltDT05ORUNUT1I6JWQ6JXNd XG4iLCBjb25uZWN0b3ItPmJhc2UuaWQsCj4gPiAtCQkgICAgICBjb25uZWN0b3ItPm5hbWUpOwo+ ID4gKwltdXRleF9sb2NrKCZkZXYtPm1vZGVfY29uZmlnLm11dGV4KTsKPiA+ICAKPiA+IC0JLyog R3JhYiB0aGUgbG9ja3MgYmVmb3JlIGNoYW5naW5nIGNvbm5lY3RvciBwcm9wZXJ0eSovCj4gPiAt CW11dGV4X2xvY2soJmNvbm5lY3Rvci0+ZGV2LT5tb2RlX2NvbmZpZy5tdXRleCk7Cj4gPiAtCS8q IFNldCBjb25uZWN0b3IgbGluayBzdGF0dXMgdG8gQkFEIGFuZCBzZW5kIGEgVWV2ZW50IHRvIG5v dGlmeQo+ID4gLQkgKiB1c2Vyc3BhY2UgdG8gZG8gYSBtb2Rlc2V0Lgo+ID4gKwkvKiBTZXQgdGhl IGNvbm5lY3RvciBsaW5rIHN0YXR1cyBvZiBhbGwgKHBvc3NpYmx5IGRvd25zdHJlYW0pCj4gPiBw b3J0cyB0bwo+ID4gKwkgKiBCQUQgYW5kIHNlbmQgYSBVZXZlbnQgdG8gbm90aWZ5IHVzZXJzcGFj ZSB0byBkbyBhIG1vZGVzZXQuCj4gPiAgCSAqLwo+ID4gLQlkcm1fbW9kZV9jb25uZWN0b3Jfc2V0 X2xpbmtfc3RhdHVzX3Byb3BlcnR5KGNvbm5lY3RvciwKPiA+IC0JCQkJCQkgICAgRFJNX01PREVf TElOS19TVEFUVVNfCj4gPiBCQUQpOwo+ID4gLQltdXRleF91bmxvY2soJmNvbm5lY3Rvci0+ZGV2 LT5tb2RlX2NvbmZpZy5tdXRleCk7Cj4gPiArCWlmIChpbnRlbF9kcC0+aXNfbXN0KSB7Cj4gPiAr CQlkcm1fZHBfbXN0X3RvcG9sb2d5X21ncl9sb3dlcl9saW5rX3JhdGUoCj4gPiArCQkgICAgJmlu dGVsX2RwLT5tc3RfbWdyLAo+ID4gKwkJICAgIGludGVsX2RwX21heF9saW5rX3JhdGUoaW50ZWxf ZHApLAo+ID4gKwkJICAgIGludGVsX2RwX21heF9sYW5lX2NvdW50KGludGVsX2RwKSk7Cj4gPiAr CX0gZWxzZSB7Cj4gPiArCQljb25uZWN0b3IgPSAmaW50ZWxfZHAtPmF0dGFjaGVkX2Nvbm5lY3Rv ci0+YmFzZTsKPiA+ICsKPiA+ICsJCURSTV9ERUJVR19LTVMoIltDT05ORUNUT1I6JWQ6JXNdXG4i LAo+ID4gKwkJCSAgICAgIGNvbm5lY3Rvci0+YmFzZS5pZCwgY29ubmVjdG9yLT5uYW1lKTsKPiA+ ICsJCWRybV9tb2RlX2Nvbm5lY3Rvcl9zZXRfbGlua19zdGF0dXNfcHJvcGVydHkoCj4gPiArCQkg ICAgY29ubmVjdG9yLCBEUk1fTU9ERV9MSU5LX1NUQVRVU19CQUQpOwo+ID4gKwl9Cj4gPiArCj4g PiArCW11dGV4X3VubG9jaygmZGV2LT5tb2RlX2NvbmZpZy5tdXRleCk7Cj4gPiArCj4gPiAgCS8q IFNlbmQgSG90cGx1ZyB1ZXZlbnQgc28gdXNlcnNwYWNlIGNhbiByZXByb2JlICovCj4gPiAtCWRy bV9rbXNfaGVscGVyX2hvdHBsdWdfZXZlbnQoY29ubmVjdG9yLT5kZXYpOwo+ID4gKwlkcm1fa21z X2hlbHBlcl9ob3RwbHVnX2V2ZW50KGRldik7Cj4gPiAgfQo+ID4gIAo+ID4gIGJvb2wKPiA+IEBA IC02MzAyLDYgKzY0NzcsOSBAQCBpbnRlbF9kcF9pbml0X2Nvbm5lY3RvcihzdHJ1Y3QgaW50ZWxf ZGlnaXRhbF9wb3J0Cj4gPiAqaW50ZWxfZGlnX3BvcnQsCj4gPiAgCS8qIEluaXRpYWxpemUgdGhl IHdvcmsgZm9yIG1vZGVzZXQgaW4gY2FzZSBvZiBsaW5rIHRyYWluIGZhaWx1cmUKPiA+ICovCj4g PiAgCUlOSVRfV09SSygmaW50ZWxfZHAtPm1vZGVzZXRfcmV0cnlfd29yaywKPiA+ICAJCSAgaW50 ZWxfZHBfbW9kZXNldF9yZXRyeV93b3JrX2ZuKTsKPiA+ICsJSU5JVF9XT1JLKCZpbnRlbF9kcC0+ bXN0X3JldHJhaW5fd29yaywKPiA+ICsJCSAgaW50ZWxfZHBfbXN0X3JldHJhaW5fbGlua193b3Jr KTsKPiA+ICsJaW5pdF9jb21wbGV0aW9uKCZpbnRlbF9kcC0+bXN0X3JldHJhaW5fY29tcGxldGlv bik7Cj4gPiAgCj4gPiAgCWlmIChXQVJOKGludGVsX2RpZ19wb3J0LT5tYXhfbGFuZXMgPCAxLAo+ ID4gIAkJICJOb3QgZW5vdWdoIGxhbmVzICglZCkgZm9yIERQIG9uIHBvcnQgJWNcbiIsCj4gPiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHBfbXN0LmMKPiA+IGIvZHJp dmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHBfbXN0LmMKPiA+IGluZGV4IGMwNTUzNDU2YjE4ZS4u MzEyMDJmODM4ZTg5IDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxf ZHBfbXN0LmMKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2RwX21zdC5jCj4g PiBAQCAtMTEwLDIxICsxMTAsMzIgQEAgc3RhdGljIGludCBpbnRlbF9kcF9tc3RfYXRvbWljX2No ZWNrKHN0cnVjdAo+ID4gZHJtX2Nvbm5lY3RvciAqY29ubmVjdG9yLAo+ID4gIAlzdHJ1Y3QgZHJt X2Nvbm5lY3Rvcl9zdGF0ZSAqb2xkX2Nvbm5fc3RhdGU7Cj4gPiAgCXN0cnVjdCBkcm1fY3J0YyAq b2xkX2NydGM7Cj4gPiAgCXN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZTsKPiA+ICsJ c3RydWN0IGRybV9kcF9tc3RfdG9wb2xvZ3lfbWdyICptZ3I7Cj4gPiArCXN0cnVjdCBkcm1fZW5j b2RlciAqZW5jb2RlcjsKPiA+ICAJaW50IHNsb3RzLCByZXQgPSAwOwo+ID4gKwlib29sIGNvdWxk X3JldHJhaW4gPSBmYWxzZTsKPiA+ICsKPiA+ICsJaWYgKG5ld19jb25uX3N0YXRlLT5jcnRjKSB7 Cj4gPiArCQljcnRjX3N0YXRlID0gZHJtX2F0b21pY19nZXRfbmV3X2NydGNfc3RhdGUoCj4gPiAr CQkgICAgc3RhdGUsIG5ld19jb25uX3N0YXRlLT5jcnRjKTsKPiA+ICsJCWlmIChjcnRjX3N0YXRl ICYmCj4gPiBkcm1fYXRvbWljX2NydGNfbmVlZHNfbW9kZXNldChjcnRjX3N0YXRlKSkKPiA+ICsJ CQljb3VsZF9yZXRyYWluID0gdHJ1ZTsKPiA+ICsJfQo+ID4gIAo+ID4gIAlvbGRfY29ubl9zdGF0 ZSA9IGRybV9hdG9taWNfZ2V0X29sZF9jb25uZWN0b3Jfc3RhdGUoc3RhdGUsCj4gPiBjb25uZWN0 b3IpOwo+ID4gIAlvbGRfY3J0YyA9IG9sZF9jb25uX3N0YXRlLT5jcnRjOwo+ID4gIAlpZiAoIW9s ZF9jcnRjKQo+ID4gLQkJcmV0dXJuIHJldDsKPiA+ICsJCWdvdG8gb3V0Owo+ID4gIAo+ID4gIAlj cnRjX3N0YXRlID0gZHJtX2F0b21pY19nZXRfbmV3X2NydGNfc3RhdGUoc3RhdGUsIG9sZF9jcnRj KTsKPiA+IC0Jc2xvdHMgPSB0b19pbnRlbF9jcnRjX3N0YXRlKGNydGNfc3RhdGUpLT5kcF9tX24u dHU7Cj4gPiAtCWlmIChkcm1fYXRvbWljX2NydGNfbmVlZHNfbW9kZXNldChjcnRjX3N0YXRlKSAm JiBzbG90cyA+IDApIHsKPiA+IC0JCXN0cnVjdCBkcm1fZHBfbXN0X3RvcG9sb2d5X21nciAqbWdy Owo+ID4gLQkJc3RydWN0IGRybV9lbmNvZGVyICpvbGRfZW5jb2RlcjsKPiA+ICsJaWYgKCFkcm1f YXRvbWljX2NydGNfbmVlZHNfbW9kZXNldChjcnRjX3N0YXRlKSkKPiA+ICsJCWdvdG8gb3V0Owo+ ID4gKwljb3VsZF9yZXRyYWluID0gdHJ1ZTsKPiA+ICAKPiA+IC0JCW9sZF9lbmNvZGVyID0gb2xk X2Nvbm5fc3RhdGUtPmJlc3RfZW5jb2RlcjsKPiA+IC0JCW1nciA9ICZlbmNfdG9fbXN0KG9sZF9l bmNvZGVyKS0+cHJpbWFyeS0+ZHAubXN0X21ncjsKPiA+ICsJc2xvdHMgPSB0b19pbnRlbF9jcnRj X3N0YXRlKGNydGNfc3RhdGUpLT5kcF9tX24udHU7Cj4gPiArCWlmIChzbG90cyA+IDApIHsKPiA+ ICsJCWVuY29kZXIgPSBvbGRfY29ubl9zdGF0ZS0+YmVzdF9lbmNvZGVyOwo+ID4gKwkJbWdyID0g JmVuY190b19tc3QoZW5jb2RlciktPnByaW1hcnktPmRwLm1zdF9tZ3I7Cj4gPiAgCj4gPiAgCQly ZXQgPSBkcm1fZHBfYXRvbWljX3JlbGVhc2VfdmNwaV9zbG90cyhzdGF0ZSwgbWdyLAo+ID4gc2xv dHMpOwo+ID4gIAkJaWYgKHJldCkKPiA+IEBAIC0xMzIsNiArMTQzLDE4IEBAIHN0YXRpYyBpbnQg aW50ZWxfZHBfbXN0X2F0b21pY19jaGVjayhzdHJ1Y3QKPiA+IGRybV9jb25uZWN0b3IgKmNvbm5l Y3RvciwKPiA+ICAJCWVsc2UKPiA+ICAJCQl0b19pbnRlbF9jcnRjX3N0YXRlKGNydGNfc3RhdGUp LT5kcF9tX24udHUgPSAwOwo+ID4gIAl9Cj4gPiArCj4gPiArb3V0Ogo+ID4gKwlpZiAoY291bGRf cmV0cmFpbiAmJgo+ID4gKwkgICAgb2xkX2Nvbm5fc3RhdGUtPmxpbmtfc3RhdHVzID09IERSTV9N T0RFX0xJTktfU1RBVFVTX0JBRCkgewo+ID4gKwkJaWYgKG5ld19jb25uX3N0YXRlLT5iZXN0X2Vu Y29kZXIpCj4gPiArCQkJZW5jb2RlciA9IG5ld19jb25uX3N0YXRlLT5iZXN0X2VuY29kZXI7Cj4g PiArCQllbHNlCj4gPiArCQkJZW5jb2RlciA9IG9sZF9jb25uX3N0YXRlLT5iZXN0X2VuY29kZXI7 Cj4gPiArCj4gPiArCQltZ3IgPSAmZW5jX3RvX21zdChlbmNvZGVyKS0+cHJpbWFyeS0+ZHAubXN0 X21ncjsKPiA+ICsJCXJldCA9IGRybV9hdG9taWNfZHBfbXN0X3JldHJhaW5fdG9wb2xvZ3koc3Rh dGUsIG1ncik7Cj4gPiArCX0KPiA+ICAJcmV0dXJuIHJldDsKPiA+ICB9Cj4gPiAgCj4gPiBAQCAt MTg2LDkgKzIwOSwxMiBAQCBzdGF0aWMgdm9pZCBpbnRlbF9tc3RfcG9zdF9kaXNhYmxlX2RwKHN0 cnVjdAo+ID4gaW50ZWxfZW5jb2RlciAqZW5jb2RlciwKPiA+ICAJaW50ZWxfZHAtPmFjdGl2ZV9t c3RfbGlua3MtLTsKPiA+ICAKPiA+ICAJaW50ZWxfbXN0LT5jb25uZWN0b3IgPSBOVUxMOwo+ID4g LQlpZiAoaW50ZWxfZHAtPmFjdGl2ZV9tc3RfbGlua3MgPT0gMCkKPiA+ICsJaWYgKGludGVsX2Rw LT5hY3RpdmVfbXN0X2xpbmtzID09IDApIHsKPiA+ICsJCWludGVsX2RwLT5tc3RfbGlua19pc19i YWQgPSBmYWxzZTsKPiA+ICsKPiA+ICAJCWludGVsX2RpZ19wb3J0LT5iYXNlLnBvc3RfZGlzYWJs ZSgmaW50ZWxfZGlnX3BvcnQtPmJhc2UsCj4gPiAgCQkJCQkJICBvbGRfY3J0Y19zdGF0ZSwgTlVM TCk7Cj4gPiArCX0KPiA+ICAKPiA+ICAJRFJNX0RFQlVHX0tNUygiYWN0aXZlIGxpbmtzICVkXG4i LCBpbnRlbF9kcC0+YWN0aXZlX21zdF9saW5rcyk7Cj4gPiAgfQo+ID4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rydi5oCj4gPiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX2Rydi5oCj4gPiBpbmRleCBmYzMzODUyOWU5MTguLmY0YTU4NjFlNGRmZiAxMDA2NDQK PiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rydi5oCj4gPiArKysgYi9kcml2 ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID4gQEAgLTExMTksNiArMTExOSwxMyBAQCBz dHJ1Y3QgaW50ZWxfZHAgewo+ID4gIAkvKiBtc3QgY29ubmVjdG9yIGxpc3QgKi8KPiA+ICAJc3Ry dWN0IGludGVsX2RwX21zdF9lbmNvZGVyICptc3RfZW5jb2RlcnNbSTkxNV9NQVhfUElQRVNdOwo+ ID4gIAlzdHJ1Y3QgZHJtX2RwX21zdF90b3BvbG9neV9tZ3IgbXN0X21ncjsKPiA+ICsJLyogV2Ug Y2FuJ3QgaGFuZGxlIHJldHJhaW5pbmcgZnJvbSB0aGUgZGlnIHdvcmtxdWV1ZSwgc28uLi4gKi8K PiA+ICsJc3RydWN0IHdvcmtfc3RydWN0IG1zdF9yZXRyYWluX3dvcms7Cj4gPiArCXN0cnVjdCBj b21wbGV0aW9uIG1zdF9yZXRyYWluX2NvbXBsZXRpb247Cj4gPiArCS8qIFNldCB3aGVuIHJldHJh aW5pbmcgdGhlIGxpbmsgYXQgdGhlIGN1cnJlbnQgcGFyYW1ldGVycyBpcwo+ID4gKwkgKiBpbXBv c3NpYmxlIGZvciBhbiBNU1QgY29ubmVjdGlvbgo+ID4gKwkgKi8KPiA+ICsJYm9vbCBtc3RfbGlu a19pc19iYWQ7Cj4gPiAgCj4gPiAgCXVpbnQzMl90ICgqZ2V0X2F1eF9jbG9ja19kaXZpZGVyKShz dHJ1Y3QgaW50ZWxfZHAgKmRwLCBpbnQKPiA+IGluZGV4KTsKPiA+ICAJLyoKPiA+IEBAIC0xNjg2 LDYgKzE2OTMsNyBAQCB2b2lkIGludGVsX2RwX2NvbXB1dGVfcmF0ZShzdHJ1Y3QgaW50ZWxfZHAK PiA+ICppbnRlbF9kcCwgaW50IHBvcnRfY2xvY2ssCj4gPiAgYm9vbCBpbnRlbF9kcF9zb3VyY2Vf c3VwcG9ydHNfaGJyMihzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwKTsKPiA+ICBib29sCj4gPiAg aW50ZWxfZHBfZ2V0X2xpbmtfc3RhdHVzKHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAsIHVpbnQ4 X3QKPiA+IGxpbmtfc3RhdHVzW0RQX0xJTktfU1RBVFVTX1NJWkVdKTsKPiA+ICtpbnQgaW50ZWxf ZHBfZ2V0X2NydGNfbWFzayhzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwKTsKPiA+ICAKPiA+ICBz dGF0aWMgaW5saW5lIHVuc2lnbmVkIGludCBpbnRlbF9kcF91bnVzZWRfbGFuZV9tYXNrKGludCBs YW5lX2NvdW50KQo+ID4gIHsKPiA+IC0tIAo+ID4gMi4xNC4zCj4gPiAKPiA+IF9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gPiBkcmktZGV2ZWwgbWFpbGlu ZyBsaXN0Cj4gPiBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCj4gPiBodHRwczovL2xp c3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAotLSAKQ2hlZXJz LAoJTHl1ZGUgUGF1bApfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5v cmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1n ZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751473AbeCLWQ3 (ORCPT ); Mon, 12 Mar 2018 18:16:29 -0400 Received: from mail-qt0-f177.google.com ([209.85.216.177]:34019 "EHLO mail-qt0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751282AbeCLWQ2 (ORCPT ); Mon, 12 Mar 2018 18:16:28 -0400 X-Google-Smtp-Source: AG47ELuNxSKM6HwZjDe/pcskqsZWPw3O6t07njOKw2cpUenHABQjkwH81P6Wp4g7Hrj0LMVF+L/lRQ== Message-ID: <1520892985.12372.14.camel@redhat.com> Subject: Re: [PATCH v3 5/5] drm/i915: Implement proper fallback training for MST From: Lyude Paul To: Manasi Navare Cc: intel-gfx@lists.freedesktop.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi Date: Mon, 12 Mar 2018 18:16:25 -0400 In-Reply-To: <20180312220522.GC3022@intel.com> References: <20180308232421.14049-1-lyude@redhat.com> <20180309213232.19855-1-lyude@redhat.com> <20180309213232.19855-5-lyude@redhat.com> <20180312220522.GC3022@intel.com> Organization: Red Hat Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.5 (3.26.5-1.fc27) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2018-03-12 at 15:05 -0700, Manasi Navare wrote: > On Fri, Mar 09, 2018 at 04:32:31PM -0500, Lyude Paul wrote: > > For a while we actually haven't had any way of retraining MST links with > > fallback link parameters like we do with SST. While uncommon, certain > > setups such as my Caldigit TS3 + EVGA MST hub require this since > > otherwise, they end up getting stuck in an infinite MST retraining loop. > > > > MST retraining is somewhat different then SST retraining. While it's > > possible during the normal link retraining sequence for a hub to indicate > > bad link status, it's also possible for a hub to only indicate this > > status through ESI messages and it's possible for this to happen after > > the initial link training succeeds. This can lead to a pattern that > > looks like this: > > > > - Train MST link > > - Training completes successfully > > - MST hub sets Channel EQ failed bit in ESI > > - Retraining starts > > - Retraining completes successfully > > - MST hub sets Channel EQ failed bit in ESI again > > - Rinse and repeat > > > > In these situations, we need to be able to actually trigger fallback > > link training from the ESI handler as well, along with using the ESI > > handler during retraining to figure out whether or not our retraining > > actually succeeded. > > > > This gets a bit more complicated since we have to ensure that we don't > > block the ESI handler at all while doing retraining. If we do, due to > > DisplayPort's general issues with being sensitive to IRQ latency most > > MST hubs will just stop responding to us if their interrupts aren't > > handled in a timely manner. > > > > So: move retraining into it's own seperate handler. Running in a > > seperate handler allows us to avoid stalling the ESI during link > > retraining, and we can have the ESI signal that the channel EQ bit was > > cleared through a simple completion struct. Additionally, we take care > > to stick as much of this into the SST retraining path as possible since > > sharing is caring. > > > > Thanks for the patch for MST retraining. So just to confirm my understanding > of the > cases where MS retraining is handled: > 1. On link the first link training failure during the modeset, this would > just > use SST modeset retry function and set the link status to BAD through > drm_dp_mst_topology_mgr_lower_link_rate() This shoyuld be the the case for hubs that are a bit less awkward then mine. I haven't actually seen the link training fail during the initial modeset once on my setup here, only the channel EQ bit in the ESI handler ever seems to get set. > > 2. In case that it suceeds here but then loses synchronization in between, > that time it will send IRQ_HPD and > indicate this through ESI and the way its handled is through > intel_dp_mst_check_link_status() and then through > the separate mst_retrain_link work. And this time we first try to retrain at > the current values for 5 times and > then fallback and retry by sending hotplug uevent. Yes. As well, there's two ways we could run into a situation that would count as a failure: * (Note, this doesn't happen because I forgot to include it in this patch series, but it'll be fixed in the next revision) If the hub does everything it's supposed to and actually reports the link training status as failing through the registers that intel_dp_start_link_train() relies on, then intel_dp_start_link_train() will try five times; fail; and then we'll skip any additional attempts in intel_dp_retrain_link() and start the modeset retry work. * If the hub doesn't do everything that it's supposed to like mine does and only reports channel EQ failures through the ESI handler, we'll end up successfully link training; time out waiting for the ESI handler to signal through mst_retrain_completion that the channel EQ bit has been cleared, and repeat five times until we give up and fall back to a lower link rate with the modeset retry work. > > Is this correct? > > Manasi > > > Signed-off-by: Lyude Paul > > Cc: Manasi Navare > > Cc: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_dp.c | 342 +++++++++++++++++++++++++++-- > > ------- > > drivers/gpu/drm/i915/intel_dp_mst.c | 42 ++++- > > drivers/gpu/drm/i915/intel_drv.h | 8 + > > 3 files changed, 302 insertions(+), 90 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > b/drivers/gpu/drm/i915/intel_dp.c > > index 5645a194de92..7626652732b6 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -45,6 +45,8 @@ > > > > #define DP_DPRX_ESI_LEN 14 > > > > +#define DP_MST_RETRAIN_TIMEOUT (msecs_to_jiffies(100)) > > + > > /* Compliance test status bits */ > > #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 > > #define INTEL_DP_RESOLUTION_PREFERRED (1 << > > INTEL_DP_RESOLUTION_SHIFT_MASK) > > @@ -4224,6 +4226,118 @@ static void intel_dp_handle_test_request(struct > > intel_dp *intel_dp) > > DRM_DEBUG_KMS("Could not write test response to sink\n"); > > } > > > > +/* Get a mask of the CRTCs that are running on the given intel_dp struct. > > For > > + * MST, this returns a crtc mask containing all of the CRTCs driving > > + * downstream sinks, for SST it just returns a mask of the attached > > + * connector's CRTC. > > + */ > > +int > > +intel_dp_get_crtc_mask(struct intel_dp *intel_dp) > > +{ > > + struct drm_device *dev = dp_to_dig_port(intel_dp)->base.base.dev; > > + struct drm_connector *connector; > > + struct drm_connector_state *conn_state; > > + struct intel_connector *intel_connector; > > + struct drm_crtc *crtc; > > + int crtc_mask = 0; > > + > > + WARN_ON(!drm_modeset_is_locked(&dev- > > >mode_config.connection_mutex)); > > + > > + if (intel_dp->is_mst) { > > + struct drm_connector_list_iter conn_iter; > > + > > + drm_connector_list_iter_begin(dev, &conn_iter); > > + for_each_intel_connector_iter(intel_connector, > > &conn_iter) { > > + if (intel_connector->mst_port != intel_dp) > > + continue; > > + > > + conn_state = intel_connector->base.state; > > + if (!conn_state->crtc) > > + continue; > > + > > + crtc_mask |= drm_crtc_mask(conn_state->crtc); > > + } > > + drm_connector_list_iter_end(&conn_iter); > > + } else { > > + connector = &intel_dp->attached_connector->base; > > + crtc = connector->state->crtc; > > + > > + if (crtc) > > + crtc_mask |= drm_crtc_mask(crtc); > > + } > > + > > + return crtc_mask; > > +} > > + > > +static bool > > +intel_dp_needs_link_retrain(struct intel_dp *intel_dp, > > + const u8 esi[DP_DPRX_ESI_LEN]) > > +{ > > + u8 buf[max(DP_LINK_STATUS_SIZE, DP_DPRX_ESI_LEN)]; > > + const u8 *link_status = NULL; > > + > > + if (intel_dp->is_mst) { > > + if (!intel_dp->active_mst_links) > > + return false; > > + if (intel_dp->mst_link_is_bad) > > + return false; > > + > > + if (esi) { > > + link_status = &esi[10]; > > + } else { > > + /* We're not running from the ESI handler, so > > wait a > > + * little bit to see if the ESI handler lets us > > know > > + * that the link status is OK > > + */ > > + if (wait_for_completion_timeout( > > + &intel_dp->mst_retrain_completion, > > + DP_MST_RETRAIN_TIMEOUT)) > > + return false; > > + } > > + } else { > > + if (intel_dp->link_trained) > > + return false; > > + if (!intel_dp_get_link_status(intel_dp, buf)) > > + return false; > > + > > + link_status = buf; > > + } > > + > > + /* > > + * Validate the cached values of intel_dp->link_rate and > > + * intel_dp->lane_count before attempting to retrain. > > + */ > > + if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, > > + intel_dp->lane_count)) > > + return false; > > + > > + if (link_status) { > > + return !drm_dp_channel_eq_ok(link_status, > > + intel_dp->lane_count); > > + } else { > > + return true; > > + } > > +} > > + > > +static inline void > > +intel_dp_mst_check_link_status(struct intel_dp *intel_dp, > > + const u8 esi[DP_DPRX_ESI_LEN]) > > +{ > > + if (intel_dp_needs_link_retrain(intel_dp, esi)) { > > + DRM_DEBUG_KMS("Channel EQ failing\n"); > > + > > + if (!work_busy(&intel_dp->mst_retrain_work)) { > > + reinit_completion(&intel_dp- > > >mst_retrain_completion); > > + schedule_work(&intel_dp->mst_retrain_work); > > + DRM_DEBUG_KMS("Retraining started\n"); > > + } > > + } else if (work_busy(&intel_dp->mst_retrain_work) && > > + !completion_done(&intel_dp->mst_retrain_completion)) { > > + DRM_DEBUG_KMS("Channel EQ stable\n"); > > + complete_all(&intel_dp->mst_retrain_completion); > > + } > > +} > > + > > static int > > intel_dp_check_mst_status(struct intel_dp *intel_dp) > > { > > @@ -4237,14 +4351,7 @@ intel_dp_check_mst_status(struct intel_dp > > *intel_dp) > > bret = intel_dp_get_sink_irq_esi(intel_dp, esi); > > go_again: > > if (bret == true) { > > - > > - /* check link status - esi[10] = 0x200c */ > > - if (intel_dp->active_mst_links && > > - !drm_dp_channel_eq_ok(&esi[10], intel_dp- > > >lane_count)) { > > - DRM_DEBUG_KMS("channel EQ not ok, > > retraining\n"); > > - intel_dp_start_link_train(intel_dp); > > - intel_dp_stop_link_train(intel_dp); > > - } > > + intel_dp_mst_check_link_status(intel_dp, esi); > > > > DRM_DEBUG_KMS("got esi %3ph\n", esi); > > ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, > > &handled); > > @@ -4281,29 +4388,6 @@ intel_dp_check_mst_status(struct intel_dp > > *intel_dp) > > return -EINVAL; > > } > > > > -static bool > > -intel_dp_needs_link_retrain(struct intel_dp *intel_dp) > > -{ > > - u8 link_status[DP_LINK_STATUS_SIZE]; > > - > > - if (!intel_dp->link_trained) > > - return false; > > - > > - if (!intel_dp_get_link_status(intel_dp, link_status)) > > - return false; > > - > > - /* > > - * Validate the cached values of intel_dp->link_rate and > > - * intel_dp->lane_count before attempting to retrain. > > - */ > > - if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, > > - intel_dp->lane_count)) > > - return false; > > - > > - /* Retrain if Channel EQ or CR not ok */ > > - return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); > > -} > > - > > /* > > * If display is now connected check links status, > > * there has been known issues of link loss triggering > > @@ -4319,64 +4403,78 @@ intel_dp_needs_link_retrain(struct intel_dp > > *intel_dp) > > int intel_dp_retrain_link(struct intel_encoder *encoder, > > struct drm_modeset_acquire_ctx *ctx) > > { > > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > + struct drm_device *dev = encoder->base.dev; > > + struct drm_i915_private *dev_priv = to_i915(dev); > > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > > - struct intel_connector *connector = intel_dp->attached_connector; > > - struct drm_connector_state *conn_state; > > - struct intel_crtc_state *crtc_state; > > - struct intel_crtc *crtc; > > + struct drm_crtc *crtc; > > + struct intel_crtc *intel_crtc; > > + int crtc_mask, retry_count = 0; > > int ret; > > > > - /* FIXME handle the MST connectors as well */ > > - > > - if (!connector || connector->base.status != > > connector_status_connected) > > - return 0; > > - > > ret = drm_modeset_lock(&dev_priv- > > >drm.mode_config.connection_mutex, > > ctx); > > if (ret) > > return ret; > > > > - conn_state = connector->base.state; > > - > > - crtc = to_intel_crtc(conn_state->crtc); > > - if (!crtc) > > - return 0; > > + crtc_mask = intel_dp_get_crtc_mask(intel_dp); > > + for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) { > > + struct drm_crtc_state *crtc_state; > > + struct intel_crtc_state *intel_crtc_state; > > > > - ret = drm_modeset_lock(&crtc->base.mutex, ctx); > > - if (ret) > > - return ret; > > + crtc = &intel_crtc->base; > > + ret = drm_modeset_lock(&crtc->mutex, ctx); > > + if (ret) > > + return ret; > > > > - crtc_state = to_intel_crtc_state(crtc->base.state); > > + crtc_state = crtc->state; > > + intel_crtc_state = to_intel_crtc_state(crtc_state); > > + WARN_ON(!intel_crtc_has_dp_encoder(intel_crtc_state)); > > > > - WARN_ON(!intel_crtc_has_dp_encoder(crtc_state)); > > + if (crtc_state->commit && > > + !try_wait_for_completion(&crtc_state->commit- > > >hw_done)) > > + return 0; > > + } > > > > - if (!crtc_state->base.active) > > + if (!intel_dp_needs_link_retrain(intel_dp, NULL)) > > return 0; > > > > - if (conn_state->commit && > > - !try_wait_for_completion(&conn_state->commit->hw_done)) > > - return 0; > > + for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) { > > + intel_set_cpu_fifo_underrun_reporting( > > + dev_priv, intel_crtc->pipe, false); > > > > - if (!intel_dp_needs_link_retrain(intel_dp)) > > - return 0; > > + if (intel_crtc->config->has_pch_encoder) { > > + intel_set_pch_fifo_underrun_reporting( > > + dev_priv, > > intel_crtc_pch_transcoder(intel_crtc), > > + false); > > + } > > + } > > > > - /* Suppress underruns caused by re-training */ > > - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, > > false); > > - if (crtc->config->has_pch_encoder) > > - intel_set_pch_fifo_underrun_reporting(dev_priv, > > - intel_crtc_pch_tran > > scoder(crtc), false); > > + do { > > + if (++retry_count > 5) { > > + DRM_DEBUG_KMS("Too many retries, can't > > retrain\n"); > > + return -EINVAL; > > + } > > > > - intel_dp_start_link_train(intel_dp); > > - intel_dp_stop_link_train(intel_dp); > > + intel_dp_start_link_train(intel_dp); > > + intel_dp_stop_link_train(intel_dp); > > + } while (intel_dp_needs_link_retrain(intel_dp, NULL)); > > + > > + /* Wait for things to become stable */ > > + for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) > > + intel_wait_for_vblank(dev_priv, intel_crtc->pipe); > > > > - /* Keep underrun reporting disabled until things are stable */ > > - intel_wait_for_vblank(dev_priv, crtc->pipe); > > + /* Now that we know everything is OK, finally re-enable underrun > > + * reporting */ > > + for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) { > > + intel_set_cpu_fifo_underrun_reporting( > > + dev_priv, intel_crtc->pipe, true); > > > > - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, > > true); > > - if (crtc->config->has_pch_encoder) > > - intel_set_pch_fifo_underrun_reporting(dev_priv, > > - intel_crtc_pch_tran > > scoder(crtc), true); > > + if (intel_crtc->config->has_pch_encoder) { > > + intel_set_pch_fifo_underrun_reporting( > > + dev_priv, > > intel_crtc_pch_transcoder(intel_crtc), > > + true); > > + } > > + } > > > > return 0; > > } > > @@ -4402,6 +4500,10 @@ static bool intel_dp_hotplug(struct intel_encoder > > *encoder, > > > > changed = intel_encoder_hotplug(encoder, connector); > > > > + /* We don't want to end up trying to retrain MST links! */ > > + if (encoder && enc_to_intel_dp(&encoder->base)->is_mst) > > + return changed; > > + > > drm_modeset_acquire_init(&ctx, 0); > > > > for (;;) { > > @@ -4478,7 +4580,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) > > } > > > > /* defer to the hotplug work for link retraining if needed */ > > - if (intel_dp_needs_link_retrain(intel_dp)) > > + if (intel_dp_needs_link_retrain(intel_dp, NULL)) > > return false; > > > > if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { > > @@ -6266,25 +6368,98 @@ static bool intel_edp_init_connector(struct > > intel_dp *intel_dp, > > return false; > > } > > > > +static void intel_dp_mst_retrain_link_work(struct work_struct *work) > > +{ > > + struct drm_modeset_acquire_ctx ctx; > > + struct intel_dp *intel_dp = container_of(work, typeof(*intel_dp), > > + mst_retrain_work); > > + struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)- > > >base; > > + struct drm_device *dev = intel_encoder->base.dev; > > + int ret; > > + bool had_error = false; > > + > > + drm_modeset_acquire_init(&ctx, 0); > > + > > + for (;;) { > > + ret = intel_dp_retrain_link(intel_encoder, &ctx); > > + if (ret == -EDEADLK) { > > + drm_modeset_backoff(&ctx); > > + continue; > > + } > > + > > + break; > > + } > > + if (!ret) { > > + DRM_DEBUG_KMS("Retrain complete\n"); > > + goto out; > > + } else if (ret == -EIO) { > > + DRM_ERROR("IO error with sink during retrain? > > Aborting\n"); > > + had_error = true; > > + goto out; > > + } > > + > > + DRM_DEBUG_KMS("Retraining failed with %d, marking link status as > > bad\n", > > + ret); > > + > > + /* We ran out of retries, if the sink hasn't changed the link > > rate in > > + * it's dpcd yet force us to fallback to a lower link rate/count > > */ > > + if (ret == -EINVAL) { > > + ret = intel_dp_get_dpcd(intel_dp); > > + if (!ret) { > > + DRM_ERROR("IO error while reading dpcd from > > sink\n"); > > + had_error = true; > > + goto out; > > + } > > + > > + if (intel_dp->link_rate == > > intel_dp_max_link_rate(intel_dp) && > > + intel_dp->lane_count == > > intel_dp_max_lane_count(intel_dp)) { > > + intel_dp_get_link_train_fallback_values( > > + intel_dp, intel_dp_max_link_rate(intel_dp), > > + intel_dp_max_lane_count(intel_dp)); > > + } > > + } > > + > > + intel_dp->mst_link_is_bad = true; > > + intel_dp->mst_bw_locked = false; > > + schedule_work(&intel_dp->modeset_retry_work); > > +out: > > + drm_modeset_drop_locks(&ctx); > > + drm_modeset_acquire_fini(&ctx); > > + if (had_error) > > + drm_kms_helper_hotplug_event(dev); > > +} > > + > > static void intel_dp_modeset_retry_work_fn(struct work_struct *work) > > { > > struct intel_dp *intel_dp = container_of(work, typeof(*intel_dp), > > modeset_retry_work); > > - struct drm_connector *connector = &intel_dp->attached_connector- > > >base; > > + struct intel_digital_port *intel_dig_port = > > dp_to_dig_port(intel_dp); > > + struct drm_device *dev = intel_dig_port->base.base.dev; > > + struct drm_connector *connector; > > > > - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, > > - connector->name); > > + mutex_lock(&dev->mode_config.mutex); > > > > - /* Grab the locks before changing connector property*/ > > - mutex_lock(&connector->dev->mode_config.mutex); > > - /* Set connector link status to BAD and send a Uevent to notify > > - * userspace to do a modeset. > > + /* Set the connector link status of all (possibly downstream) > > ports to > > + * BAD and send a Uevent to notify userspace to do a modeset. > > */ > > - drm_mode_connector_set_link_status_property(connector, > > - DRM_MODE_LINK_STATUS_ > > BAD); > > - mutex_unlock(&connector->dev->mode_config.mutex); > > + if (intel_dp->is_mst) { > > + drm_dp_mst_topology_mgr_lower_link_rate( > > + &intel_dp->mst_mgr, > > + intel_dp_max_link_rate(intel_dp), > > + intel_dp_max_lane_count(intel_dp)); > > + } else { > > + connector = &intel_dp->attached_connector->base; > > + > > + DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", > > + connector->base.id, connector->name); > > + drm_mode_connector_set_link_status_property( > > + connector, DRM_MODE_LINK_STATUS_BAD); > > + } > > + > > + mutex_unlock(&dev->mode_config.mutex); > > + > > /* Send Hotplug uevent so userspace can reprobe */ > > - drm_kms_helper_hotplug_event(connector->dev); > > + drm_kms_helper_hotplug_event(dev); > > } > > > > bool > > @@ -6302,6 +6477,9 @@ intel_dp_init_connector(struct intel_digital_port > > *intel_dig_port, > > /* Initialize the work for modeset in case of link train failure > > */ > > INIT_WORK(&intel_dp->modeset_retry_work, > > intel_dp_modeset_retry_work_fn); > > + INIT_WORK(&intel_dp->mst_retrain_work, > > + intel_dp_mst_retrain_link_work); > > + init_completion(&intel_dp->mst_retrain_completion); > > > > if (WARN(intel_dig_port->max_lanes < 1, > > "Not enough lanes (%d) for DP on port %c\n", > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c > > b/drivers/gpu/drm/i915/intel_dp_mst.c > > index c0553456b18e..31202f838e89 100644 > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > > @@ -110,21 +110,32 @@ static int intel_dp_mst_atomic_check(struct > > drm_connector *connector, > > struct drm_connector_state *old_conn_state; > > struct drm_crtc *old_crtc; > > struct drm_crtc_state *crtc_state; > > + struct drm_dp_mst_topology_mgr *mgr; > > + struct drm_encoder *encoder; > > int slots, ret = 0; > > + bool could_retrain = false; > > + > > + if (new_conn_state->crtc) { > > + crtc_state = drm_atomic_get_new_crtc_state( > > + state, new_conn_state->crtc); > > + if (crtc_state && > > drm_atomic_crtc_needs_modeset(crtc_state)) > > + could_retrain = true; > > + } > > > > old_conn_state = drm_atomic_get_old_connector_state(state, > > connector); > > old_crtc = old_conn_state->crtc; > > if (!old_crtc) > > - return ret; > > + goto out; > > > > crtc_state = drm_atomic_get_new_crtc_state(state, old_crtc); > > - slots = to_intel_crtc_state(crtc_state)->dp_m_n.tu; > > - if (drm_atomic_crtc_needs_modeset(crtc_state) && slots > 0) { > > - struct drm_dp_mst_topology_mgr *mgr; > > - struct drm_encoder *old_encoder; > > + if (!drm_atomic_crtc_needs_modeset(crtc_state)) > > + goto out; > > + could_retrain = true; > > > > - old_encoder = old_conn_state->best_encoder; > > - mgr = &enc_to_mst(old_encoder)->primary->dp.mst_mgr; > > + slots = to_intel_crtc_state(crtc_state)->dp_m_n.tu; > > + if (slots > 0) { > > + encoder = old_conn_state->best_encoder; > > + mgr = &enc_to_mst(encoder)->primary->dp.mst_mgr; > > > > ret = drm_dp_atomic_release_vcpi_slots(state, mgr, > > slots); > > if (ret) > > @@ -132,6 +143,18 @@ static int intel_dp_mst_atomic_check(struct > > drm_connector *connector, > > else > > to_intel_crtc_state(crtc_state)->dp_m_n.tu = 0; > > } > > + > > +out: > > + if (could_retrain && > > + old_conn_state->link_status == DRM_MODE_LINK_STATUS_BAD) { > > + if (new_conn_state->best_encoder) > > + encoder = new_conn_state->best_encoder; > > + else > > + encoder = old_conn_state->best_encoder; > > + > > + mgr = &enc_to_mst(encoder)->primary->dp.mst_mgr; > > + ret = drm_atomic_dp_mst_retrain_topology(state, mgr); > > + } > > return ret; > > } > > > > @@ -186,9 +209,12 @@ static void intel_mst_post_disable_dp(struct > > intel_encoder *encoder, > > intel_dp->active_mst_links--; > > > > intel_mst->connector = NULL; > > - if (intel_dp->active_mst_links == 0) > > + if (intel_dp->active_mst_links == 0) { > > + intel_dp->mst_link_is_bad = false; > > + > > intel_dig_port->base.post_disable(&intel_dig_port->base, > > old_crtc_state, NULL); > > + } > > > > DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); > > } > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > > b/drivers/gpu/drm/i915/intel_drv.h > > index fc338529e918..f4a5861e4dff 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -1119,6 +1119,13 @@ struct intel_dp { > > /* mst connector list */ > > struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; > > struct drm_dp_mst_topology_mgr mst_mgr; > > + /* We can't handle retraining from the dig workqueue, so... */ > > + struct work_struct mst_retrain_work; > > + struct completion mst_retrain_completion; > > + /* Set when retraining the link at the current parameters is > > + * impossible for an MST connection > > + */ > > + bool mst_link_is_bad; > > > > uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int > > index); > > /* > > @@ -1686,6 +1693,7 @@ void intel_dp_compute_rate(struct intel_dp > > *intel_dp, int port_clock, > > bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); > > bool > > intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t > > link_status[DP_LINK_STATUS_SIZE]); > > +int intel_dp_get_crtc_mask(struct intel_dp *intel_dp); > > > > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) > > { > > -- > > 2.14.3 > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Cheers, Lyude Paul