From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kani, Toshi" Subject: Re: [PATCH v2 2/4] ioremap: Implement TLB_INV before huge mapping Date: Thu, 15 Mar 2018 16:12:52 +0000 Message-ID: <1521130368.2693.177.camel@hpe.com> References: <1521117906-20107-1-git-send-email-cpandya@codeaurora.org> <1521117906-20107-3-git-send-email-cpandya@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1521117906-20107-3-git-send-email-cpandya@codeaurora.org> Content-Language: en-US Content-ID: <9168F7EEE5567C4387AEFF4307500D03@NAMPRD84.PROD.OUTLOOK.COM> Sender: linux-kernel-owner@vger.kernel.org To: "cpandya@codeaurora.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "arnd@arndb.de" Cc: "linux-kernel@vger.kernel.org" , "ard.biesheuvel@linaro.org" , "tglx@linutronix.de" , "takahiro.akashi@linaro.org" , "james.morse@arm.com" , "kristina.martsenko@arm.com" , "mark.rutland@arm.com" , "akpm@linux-foundation.org" , "gregkh@linuxfoundation.org" , "linux-arm-kernel@lists.infradead.org" , "marc.zyngier@arm.com" , "linux-arch@vger.kernel.org" List-Id: linux-arch.vger.kernel.org T24gVGh1LCAyMDE4LTAzLTE1IGF0IDE4OjE1ICswNTMwLCBDaGludGFuIFBhbmR5YSB3cm90ZToN Cj4gSHVnZSBtYXBwaW5nIGNoYW5nZXMgUE1EL1BVRCB3aGljaCBjb3VsZCBoYXZlDQo+IHZhbGlk IHByZXZpb3VzIGVudHJpZXMuIFRoaXMgcmVxdWlyZXMgcHJvcGVyDQo+IFRMQiBtYWludGFuYW5j ZSBvbiBzb21lIGFyY2hpdGVjdHVyZXMsIGxpa2UNCj4gQVJNNjQuDQo+IA0KPiBJbXBsZW50IEJC TSAoYnJlYWstYmVmb3JlLW1ha2UpIHNhZmUgVExCDQo+IGludmFsaWRhdGlvbi4NCj4gDQo+IEhl cmUsIEkndmUgdXNlZCBmbHVzaF90bGJfcGd0YWJsZSgpIGluc3RlYWQNCj4gb2YgZmx1c2hfa2Vy bmVsX3JhbmdlKCkgYmVjYXVzZSBpbnZhbGlkYXRpbmcNCj4gaW50ZXJtZWRpYXRlIHBhZ2VfdGFi bGUgZW50cmllcyBjb3VsZCBoYXZlDQo+IGJlZW4gb3B0aW1pemVkIGZvciBzcGVjaWZpYyBhcmNo LiBUaGF0J3MgdGhlDQo+IGNhc2Ugd2l0aCBBUk02NCBhdCBsZWFzdC4NCj4gDQo+IFNpZ25lZC1v ZmYtYnk6IENoaW50YW4gUGFuZHlhIDxjcGFuZHlhQGNvZGVhdXJvcmEub3JnPg0KPiAtLS0NCj4g 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KTsNCg0KSSBkbyBub3QgdW5kZXJzdGFuZCB3aHkgeW91IG5lZWRlZCB0byBtYWtlIHRoaXMgY2hh bmdlLiANCnBtZF9mcmVlX3B0ZV9wYWdlKCkgaXMgZGVmaW5lZCBhcyBhbiBhcmNoLXNwZWNpZmlj IGZ1bmN0aW9uIHNvIHRoYXQgeW91DQpjYW4gYWRkaXRpb25hbGx5IHBlcmZvcm0gVExCIHB1cmdl cyBvbiBhcm02NC4gIFBsZWFzZSB0cnkgdG8gbWFrZSBwcm9wZXINCmFybTY0IGltcGxlbWVudGF0 aW9uIG9mIHRoaXMgaW50ZXJmYWNlLiAgQW5kIGlmIHlvdSBmaW5kIGFueSBpc3N1ZSBpbg0KdGhp cyBpbnRlcmZhY2UsIHBsZWFzZSBsZXQgbWUga25vdy4NCg0KU2FtZSBmb3IgcHVkLg0KDQpUaGFu a3MsDQotVG9zaGkNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: toshi.kani@hpe.com (Kani, Toshi) Date: Thu, 15 Mar 2018 16:12:52 +0000 Subject: [PATCH v2 2/4] ioremap: Implement TLB_INV before huge mapping In-Reply-To: <1521117906-20107-3-git-send-email-cpandya@codeaurora.org> References: <1521117906-20107-1-git-send-email-cpandya@codeaurora.org> <1521117906-20107-3-git-send-email-cpandya@codeaurora.org> Message-ID: <1521130368.2693.177.camel@hpe.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, 2018-03-15 at 18:15 +0530, Chintan Pandya wrote: > Huge mapping changes PMD/PUD which could have > valid previous entries. This requires proper > TLB maintanance on some architectures, like > ARM64. > > Implent BBM (break-before-make) safe TLB > invalidation. > > Here, I've used flush_tlb_pgtable() instead > of flush_kernel_range() because invalidating > intermediate page_table entries could have > been optimized for specific arch. That's the > case with ARM64 at least. > > Signed-off-by: Chintan Pandya > --- > lib/ioremap.c | 25 +++++++++++++++++++------ > 1 file changed, 19 insertions(+), 6 deletions(-) > > diff --git a/lib/ioremap.c b/lib/ioremap.c > index 54e5bba..55f8648 100644 > --- a/lib/ioremap.c > +++ b/lib/ioremap.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > > #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP > static int __read_mostly ioremap_p4d_capable; > @@ -80,6 +81,7 @@ static inline int ioremap_pmd_range(pud_t *pud, unsigned long addr, > unsigned long end, phys_addr_t phys_addr, pgprot_t prot) > { > pmd_t *pmd; > + pmd_t old_pmd; > unsigned long next; > > phys_addr -= addr; > @@ -91,10 +93,15 @@ static inline int ioremap_pmd_range(pud_t *pud, unsigned long addr, > > if (ioremap_pmd_enabled() && > ((next - addr) == PMD_SIZE) && > - IS_ALIGNED(phys_addr + addr, PMD_SIZE) && > - pmd_free_pte_page(pmd)) { > - if (pmd_set_huge(pmd, phys_addr + addr, prot)) > + IS_ALIGNED(phys_addr + addr, PMD_SIZE)) { > + old_pmd = *pmd; > + pmd_clear(pmd); pmd_clear() is one of the operations pmd_free_pte_page() needs to do. See the x86 version. > + flush_tlb_pgtable(&init_mm, addr); You can call it in pmd_free_pte_page() on arm64 as well. > + if (pmd_set_huge(pmd, phys_addr + addr, prot)) { > + pmd_free_pte_page(&old_pmd); > continue; > + } else > + set_pmd(pmd, old_pmd); I do not understand why you needed to make this change. pmd_free_pte_page() is defined as an arch-specific function so that you can additionally perform TLB purges on arm64. Please try to make proper arm64 implementation of this interface. And if you find any issue in this interface, please let me know. Same for pud. Thanks, -Toshi