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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
Date: Tue, 10 Apr 2018 14:17:15 -0700	[thread overview]
Message-ID: <1523395035.2564.21.camel@intel.com> (raw)
In-Reply-To: <152339444407.13225.6043125068915540900@mail.alporthouse.com>

Em Ter, 2018-04-10 às 22:07 +0100, Chris Wilson escreveu:
> Quoting Chris Wilson (2018-04-10 22:01:33)
> > Quoting Paulo Zanoni (2018-04-10 21:39:31)
> > > Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> > > > Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > > > 
> > > > > This table is used for voltage swing programming sequence
> > > > > during
> > > > > DDI
> > > > > Buffer initialization for MG PHY DDI Buffers on Icelake.
> > > > 
> > > > Except it is not used at all...
> > > 
> > > It's going to be used later in the series.
> 
> In the context of this patch in merged series, it means that we have
> added unexecuted, untested code. Please justify that. (Unused data
> tables have in the past remain unused, leaving the code using old
> tables; a bug that would have been caught by the compiler.)
> 
> We know our test coverage is lacking, this makes it worse. Yes, it's
> icl, yes we won't even have sim coverage for the entire set of freq
> tables, so what's stopping us from writing unittests to double check
> the
> code at least conforms to our expectations and is exercised?

We have properly tested this code and verified it works. It's just that
we didn't upstream the whole series yet since it's too big. Almost 100
ICL patches already made it to the list already, and about 60 were
merged, but the specific patch that uses that table is not here yet.
I'll take the blame for missing that patch from this series.

> -Chris
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  reply	other threads:[~2018-04-10 21:17 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
2018-03-23 17:24 ` [PATCH 1/7] drm/i915/icl: Add register definitions for Combo PHY vswing sequences Paulo Zanoni
2018-03-23 17:24 ` [PATCH 2/7] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake Paulo Zanoni
2018-03-23 17:24 ` [PATCH 3/7] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI Paulo Zanoni
2018-03-23 17:24 ` [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer Paulo Zanoni
2018-04-10  8:51   ` Chris Wilson
2018-04-10 20:39     ` Paulo Zanoni
2018-04-10 21:01       ` Chris Wilson
2018-04-10 21:07         ` Chris Wilson
2018-04-10 21:17           ` Paulo Zanoni [this message]
2018-04-10 21:29         ` Paulo Zanoni
2018-03-23 17:24 ` [PATCH 5/7] drm/i915/icl: HPD pin for port F Paulo Zanoni
2018-03-23 17:24 ` [PATCH 6/7] drm/i915/icl: Added 5k source scaling support for Gen11 platform Paulo Zanoni
2018-03-23 17:24 ` [PATCH 7/7] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL Paulo Zanoni
2018-03-23 18:53 ` ✗ Fi.CI.CHECKPATCH: warning for ICL reviewed mergeable patches Patchwork
2018-03-23 19:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-23 23:16 ` ✓ Fi.CI.IGT: " Patchwork

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