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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id m68si1572293qkd.298.2018.04.17.13.49.14 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 17 Apr 2018 13:49:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@codeaurora.org header.s=default header.b=YhvJ0khC; dkim=fail header.i=@codeaurora.org header.s=default header.b=P4RLCbqM; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Received: from localhost ([::1]:33400 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8XXO-0002uF-8w for alex.bennee@linaro.org; Tue, 17 Apr 2018 16:49:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8XNe-00032k-AT for qemu-arm@nongnu.org; Tue, 17 Apr 2018 16:39:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f8XNc-0006L8-8O for qemu-arm@nongnu.org; Tue, 17 Apr 2018 16:39:10 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:40112) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f8XNb-0006CC-OI; Tue, 17 Apr 2018 16:39:08 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 12C3C60FB1; Tue, 17 Apr 2018 20:39:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523997546; bh=oU7VGZkZTlzl2Jleg5SMD9XIAH3JOHaYtZV6624s5HI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YhvJ0khCaRiWr2jHakysEyel/PWckuPBD9kpoNbAhUfYB661b1q4SueWURpWnACEd KvqQaZi+XaZ8BCS7JA/h6j+A5gpxQRSygWJXmUFJrRJhRcUPmuwbLY+9xtjuYWkbeI jcoQ0QmjtRdTav/v8KQHiwYMpl/8EWWhLKepk+M4= Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9E84A60F8E; Tue, 17 Apr 2018 20:39:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523997542; bh=oU7VGZkZTlzl2Jleg5SMD9XIAH3JOHaYtZV6624s5HI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P4RLCbqM9I6wskjcUAnNheuFOqKL3/1qfhxFtvfL3TYL3f3miysMwZdi1Cn3k63cL wsgUf5KU7/YkvaUkt9h284H17VxGbrkl3OFP/kIo+BwHrFSDmXq/1QGaXuZPwx5M19 O+BmqHAQBlNt1U3MjUq+/BWcHkjEGmB0qGW7RAII= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9E84A60F8E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Tue, 17 Apr 2018 16:37:58 -0400 Message-Id: <1523997485-1905-15-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523997485-1905-1-git-send-email-alindsay@codeaurora.org> References: <1523997485-1905-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-arm] [PATCH v4 14/21] target/arm: Implement PMOVSSET X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: xjdUMy92xuaa Adding an array for v7VE+ CP registers was necessary so that PMOVSSET wasn't defined for all v7 processors. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 20b42b4..572709e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1262,9 +1262,17 @@ static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + value &= PMU_COUNTER_MASK(env); env->cp15.c9_pmovsr &= ~value; } +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= PMU_COUNTER_MASK(env); + env->cp15.c9_pmovsr |= value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1614,6 +1622,25 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v7ve_cp_reginfo[] = { + /* Performance monitor registers which are not implemented in v7 before + * v7ve: + */ + { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4965,6 +4992,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, v7ve_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. 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