From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [1/3] Documentation: dt: socfpga: Add Stratix10 ECC Manager binding From: thor.thayer@linux.intel.com Message-Id: <1524594959-5259-2-git-send-email-thor.thayer@linux.intel.com> Date: Tue, 24 Apr 2018 13:35:57 -0500 To: bp@alien8.de, mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: thor.thayer@linux.intel.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org List-ID: RnJvbTogVGhvciBUaGF5ZXIgPHRob3IudGhheWVyQGxpbnV4LmludGVsLmNvbT4KCkFkZCB0aGUg ZGV2aWNlIHRyZWUgYmluZGluZ3MgbmVlZGVkIHRvIHN1cHBvcnQgdGhlIFN0cmF0aXgxMApFQ0Mg TWFuYWdlciBhbmQgU0RSQU0gRUNDIHRvIHRoZSBleGlzdGluZyBiaW5kaW5ncy4KClNpZ25lZC1v ZmYtYnk6IFRob3IgVGhheWVyIDx0aG9yLnRoYXllckBsaW51eC5pbnRlbC5jb20+Ci0tLQogLi4u L2JpbmRpbmdzL2FybS9hbHRlcmEvc29jZnBnYS1lY2NtZ3IudHh0ICAgICAgICAgfCA0NyArKysr KysrKysrKysrKysrKysrKysrCiAxIGZpbGUgY2hhbmdlZCwgNDcgaW5zZXJ0aW9ucygrKQoKZGlm ZiAtLWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0vYWx0ZXJhL3Nv Y2ZwZ2EtZWNjbWdyLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0v YWx0ZXJhL3NvY2ZwZ2EtZWNjbWdyLnR4dAppbmRleCA0YTE3MTRmOTZiYWIuLmZlNDhhZDI5M2Ey NCAxMDA2NDQKLS0tIGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2FybS9hbHRl cmEvc29jZnBnYS1lY2NtZ3IudHh0CisrKyBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5k aW5ncy9hcm0vYWx0ZXJhL3NvY2ZwZ2EtZWNjbWdyLnR4dApAQCAtMjMxLDMgKzIzMSw1MCBAQCBF eGFtcGxlOgogCQkJCSAgICAgPDQ4IElSUV9UWVBFX0xFVkVMX0hJR0g+OwogCQl9OwogCX07CisK K1N0cmF0aXgxMCBTb0NGUEdBIEVDQyBNYW5hZ2VyCitUaGUgU3RyYXRpeDEwIFNvQyBFQ0MgTWFu YWdlciBoYW5kbGVzIHRoZSBJUlFzIGZvciBlYWNoIHBlcmlwaGVyYWwKK2luIGEgc2hhcmVkIHJl Z2lzdGVyIHNpbWlsYXIgdG8gdGhlIEFycmlhMTAuIEhvd2V2ZXIsIEVDQyByZXF1aXJlcworYWNj ZXNzIHRvIHJlZ2lzdGVycyB0aGF0IGNhbiBvbmx5IGJlIHJlYWQgaW4gRUwzIHdpdGggU01DIGNh bGxzLgorVGhlcmVmb3JlIHRoZSBkZXZpY2UgdHJlZSBpcyBzbGlnaHRseSBkaWZmZXJlbnQuCisK K1JlcXVpcmVkIFByb3BlcnRpZXM6CistIGNvbXBhdGlibGUgOiBTaG91bGQgYmUgImFsdHIsc29j ZnBnYS1zMTAtZWNjLW1hbmFnZXIiCistIGFsdHIsc3lzZ3Itc3lzY29uIDogcGhhbmRsZSB0byBT dHJhdGl4MTAgU3lzdGVtIE1hbmFnZXIgQmxvY2sKKwljb250YWluaW5nIHRoZSBFQ0MgbWFuYWdl ciByZWdpc3RlcnMuCistICNhZGRyZXNzLWNlbGxzOiBtdXN0IGJlIDEKKy0gI3NpemUtY2VsbHM6 IG11c3QgYmUgMQorLSBpbnRlcnJ1cHRzIDogU2hvdWxkIGJlIHNpbmdsZSBiaXQgZXJyb3IgaW50 ZXJydXB0LCB0aGVuIGRvdWJsZSBiaXQgZXJyb3IKKwlpbnRlcnJ1cHQuCistIGludGVycnVwdC1j b250cm9sbGVyIDogYm9vbGVhbiBpbmRpY2F0b3IgdGhhdCBFQ0MgTWFuYWdlciBpcyBhbiBpbnRl cnJ1cHQgY29udHJvbGxlcgorLSAjaW50ZXJydXB0LWNlbGxzIDogbXVzdCBiZSBzZXQgdG8gMi4K Ky0gcmFuZ2VzIDogc3RhbmRhcmQgZGVmaW5pdGlvbiwgc2hvdWxkIHRyYW5zbGF0ZSBmcm9tIGxv Y2FsIGFkZHJlc3NlcworCitTdWJjb21wb25lbnRzOgorCitTRFJBTSBFQ0MKK1JlcXVpcmVkIFBy b3BlcnRpZXM6CistIGNvbXBhdGlibGUgOiBTaG91bGQgYmUgImFsdHIsc2RyYW0tZWRhYy1zMTAi CistIHJlZyA6IEFkZHJlc3MgYW5kIHNpemUgZm9yIEVDQyBlcnJvciBpbnRlcnJ1cHQgY2xlYXIg cmVnaXN0ZXJzLgorLSBpbnRlcnJ1cHRzIDogU2hvdWxkIGJlIHNpbmdsZSBiaXQgZXJyb3IgaW50 ZXJydXB0LCB0aGVuIGRvdWJsZSBiaXQgZXJyb3IKKwlpbnRlcnJ1cHQsIGluIHRoaXMgb3JkZXIu CisKK0V4YW1wbGU6CisKKwllY2NtZ3I6IGVjY21nckBmZmQxMjAwMCB7CisJCWNvbXBhdGlibGUg PSAiYWx0cixzb2NmcGdhLXMxMC1lY2MtbWFuYWdlciI7CisJCWFsdHIsc3lzbWdyLXN5c2NvbiA9 IDwmc3lzbWdyPjsKKwkJI2FkZHJlc3MtY2VsbHMgPSA8MT47CisJCSNzaXplLWNlbGxzID0gPDE+ OworCQlpbnRlcnJ1cHRzID0gPDAgMTUgND4sIDwwIDk1IDQ+OworCQlpbnRlcnJ1cHQtY29udHJv bGxlcjsKKwkJI2ludGVycnVwdC1jZWxscyA9IDwyPjsKKwkJcmFuZ2VzOworCisJCXNkcmFtZWRh Y0BmODAxMTEwMCB7CisJCQljb21wYXRpYmxlID0gImFsdHIsc2RyYW0tZWRhYy1zMTAiOworCQkJ cmVnID0gPDB4ZjgwMTExMDAgMHhDMD47CisJCQlpbnRlcnJ1cHRzID0gPDE2IDQ+LCA8NDggND47 CisJCX07CisJfTsKKwo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: thor.thayer@linux.intel.com (thor.thayer at linux.intel.com) Date: Tue, 24 Apr 2018 13:35:57 -0500 Subject: [PATCH 1/3] Documentation: dt: socfpga: Add Stratix10 ECC Manager binding In-Reply-To: <1524594959-5259-1-git-send-email-thor.thayer@linux.intel.com> References: <1524594959-5259-1-git-send-email-thor.thayer@linux.intel.com> Message-ID: <1524594959-5259-2-git-send-email-thor.thayer@linux.intel.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Thor Thayer Add the device tree bindings needed to support the Stratix10 ECC Manager and SDRAM ECC to the existing bindings. Signed-off-by: Thor Thayer --- .../bindings/arm/altera/socfpga-eccmgr.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt index 4a1714f96bab..fe48ad293a24 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt @@ -231,3 +231,50 @@ Example: <48 IRQ_TYPE_LEVEL_HIGH>; }; }; + +Stratix10 SoCFPGA ECC Manager +The Stratix10 SoC ECC Manager handles the IRQs for each peripheral +in a shared register similar to the Arria10. However, ECC requires +access to registers that can only be read in EL3 with SMC calls. +Therefore the device tree is slightly different. + +Required Properties: +- compatible : Should be "altr,socfpga-s10-ecc-manager" +- altr,sysgr-syscon : phandle to Stratix10 System Manager Block + containing the ECC manager registers. +- #address-cells: must be 1 +- #size-cells: must be 1 +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. +- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller +- #interrupt-cells : must be set to 2. +- ranges : standard definition, should translate from local addresses + +Subcomponents: + +SDRAM ECC +Required Properties: +- compatible : Should be "altr,sdram-edac-s10" +- reg : Address and size for ECC error interrupt clear registers. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt, in this order. + +Example: + + eccmgr: eccmgr at ffd12000 { + compatible = "altr,socfpga-s10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 15 4>, <0 95 4>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac at f8011100 { + compatible = "altr,sdram-edac-s10"; + reg = <0xf8011100 0xC0>; + interrupts = <16 4>, <48 4>; + }; + }; + -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: thor.thayer@linux.intel.com Subject: [PATCH 1/3] Documentation: dt: socfpga: Add Stratix10 ECC Manager binding Date: Tue, 24 Apr 2018 13:35:57 -0500 Message-ID: <1524594959-5259-2-git-send-email-thor.thayer@linux.intel.com> References: <1524594959-5259-1-git-send-email-thor.thayer@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1524594959-5259-1-git-send-email-thor.thayer@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: bp@alien8.de, mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, thor.thayer@linux.intel.com, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org List-Id: devicetree@vger.kernel.org From: Thor Thayer Add the device tree bindings needed to support the Stratix10 ECC Manager and SDRAM ECC to the existing bindings. Signed-off-by: Thor Thayer --- .../bindings/arm/altera/socfpga-eccmgr.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt index 4a1714f96bab..fe48ad293a24 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt @@ -231,3 +231,50 @@ Example: <48 IRQ_TYPE_LEVEL_HIGH>; }; }; + +Stratix10 SoCFPGA ECC Manager +The Stratix10 SoC ECC Manager handles the IRQs for each peripheral +in a shared register similar to the Arria10. However, ECC requires +access to registers that can only be read in EL3 with SMC calls. +Therefore the device tree is slightly different. + +Required Properties: +- compatible : Should be "altr,socfpga-s10-ecc-manager" +- altr,sysgr-syscon : phandle to Stratix10 System Manager Block + containing the ECC manager registers. +- #address-cells: must be 1 +- #size-cells: must be 1 +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. +- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller +- #interrupt-cells : must be set to 2. +- ranges : standard definition, should translate from local addresses + +Subcomponents: + +SDRAM ECC +Required Properties: +- compatible : Should be "altr,sdram-edac-s10" +- reg : Address and size for ECC error interrupt clear registers. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt, in this order. + +Example: + + eccmgr: eccmgr@ffd12000 { + compatible = "altr,socfpga-s10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 15 4>, <0 95 4>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac@f8011100 { + compatible = "altr,sdram-edac-s10"; + reg = <0xf8011100 0xC0>; + interrupts = <16 4>, <48 4>; + }; + }; + -- 2.7.4