diff for duplicates of <1525997810-10964-1-git-send-email-festevam@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 0cea5ad..3692453 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,9 +3,9 @@ From: Fabio Estevam <fabio.estevam@nxp.com> Remove unit-address and reg property from anatop regulators to fix the following DTC warnings with W=1: -arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140) -arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140) -arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140) +arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140) +arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140) +arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140) Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> --- @@ -27,7 +27,7 @@ index 69648e2..22942dd 100644 - #address-cells = <1>; - #size-cells = <0>; -- regulator-1p1 at 20c8110 { +- regulator-1p1@20c8110 { - reg = <0x20c8110>; + regulator-1p1 { compatible = "fsl,anatop-regulator"; @@ -37,7 +37,7 @@ index 69648e2..22942dd 100644 anatop-enable-bit = <0>; }; -- regulator-3p0 at 20c8120 { +- regulator-3p0@20c8120 { - reg = <0x20c8120>; + regulator-3p0 { compatible = "fsl,anatop-regulator"; @@ -47,7 +47,7 @@ index 69648e2..22942dd 100644 anatop-enable-bit = <0>; }; -- regulator-2p5 at 20c8130 { +- regulator-2p5@20c8130 { - reg = <0x20c8130>; + regulator-2p5 { compatible = "fsl,anatop-regulator"; @@ -57,7 +57,7 @@ index 69648e2..22942dd 100644 anatop-enable-bit = <0>; }; -- reg_arm: regulator-vddcore at 20c8140 { +- reg_arm: regulator-vddcore@20c8140 { - reg = <0x20c8140>; + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; @@ -67,7 +67,7 @@ index 69648e2..22942dd 100644 anatop-max-voltage = <1450000>; }; -- reg_pu: regulator-vddpu at 20c8140 { +- reg_pu: regulator-vddpu@20c8140 { - reg = <0x20c8140>; + reg_pu: regulator-vddpu { compatible = "fsl,anatop-regulator"; @@ -77,7 +77,7 @@ index 69648e2..22942dd 100644 anatop-max-voltage = <1450000>; }; -- reg_soc: regulator-vddsoc at 20c8140 { +- reg_soc: regulator-vddsoc@20c8140 { - reg = <0x20c8140>; + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; @@ -94,7 +94,7 @@ index 2002db2..8c838ba 100644 - #address-cells = <1>; - #size-cells = <0>; -- regulator-1p1 at 20c8110 { +- regulator-1p1@20c8110 { - reg = <0x20c8110>; + regulator-1p1 { compatible = "fsl,anatop-regulator"; @@ -104,7 +104,7 @@ index 2002db2..8c838ba 100644 anatop-enable-bit = <0>; }; -- regulator-3p0 at 20c8120 { +- regulator-3p0@20c8120 { - reg = <0x20c8120>; + regulator-3p0 { compatible = "fsl,anatop-regulator"; @@ -114,7 +114,7 @@ index 2002db2..8c838ba 100644 anatop-enable-bit = <0>; }; -- regulator-2p5 at 20c8130 { +- regulator-2p5@20c8130 { - reg = <0x20c8130>; + regulator-2p5 { compatible = "fsl,anatop-regulator"; @@ -124,7 +124,7 @@ index 2002db2..8c838ba 100644 anatop-enable-bit = <0>; }; -- reg_arm: regulator-vddcore at 20c8140 { +- reg_arm: regulator-vddcore@20c8140 { - reg = <0x20c8140>; + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; @@ -134,7 +134,7 @@ index 2002db2..8c838ba 100644 anatop-max-voltage = <1450000>; }; -- reg_pu: regulator-vddpu at 20c8140 { +- reg_pu: regulator-vddpu@20c8140 { - reg = <0x20c8140>; + reg_pu: regulator-vddpu { compatible = "fsl,anatop-regulator"; @@ -144,7 +144,7 @@ index 2002db2..8c838ba 100644 anatop-max-voltage = <1450000>; }; -- reg_soc: regulator-vddsoc at 20c8140 { +- reg_soc: regulator-vddsoc@20c8140 { - reg = <0x20c8140>; + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; @@ -161,7 +161,7 @@ index 7e463d2..4a97513 100644 - #address-cells = <1>; - #size-cells = <0>; -- regulator-1p1 at 20c8110 { +- regulator-1p1@20c8110 { - reg = <0x20c8110>; + regulator-1p1 { compatible = "fsl,anatop-regulator"; @@ -171,7 +171,7 @@ index 7e463d2..4a97513 100644 anatop-enable-bit = <0>; }; -- regulator-3p0 at 20c8120 { +- regulator-3p0@20c8120 { - reg = <0x20c8120>; + regulator-3p0 { compatible = "fsl,anatop-regulator"; @@ -181,7 +181,7 @@ index 7e463d2..4a97513 100644 anatop-enable-bit = <0>; }; -- regulator-2p5 at 20c8130 { +- regulator-2p5@20c8130 { - reg = <0x20c8130>; + regulator-2p5 { compatible = "fsl,anatop-regulator"; @@ -191,7 +191,7 @@ index 7e463d2..4a97513 100644 anatop-enable-bit = <0>; }; -- reg_arm: regulator-vddcore at 20c8140 { +- reg_arm: regulator-vddcore@20c8140 { - reg = <0x20c8140>; + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; @@ -201,7 +201,7 @@ index 7e463d2..4a97513 100644 anatop-max-voltage = <1450000>; }; -- reg_pcie: regulator-vddpcie at 20c8140 { +- reg_pcie: regulator-vddpcie@20c8140 { - reg = <0x20c8140>; + reg_pcie: regulator-vddpcie { compatible = "fsl,anatop-regulator"; @@ -211,7 +211,7 @@ index 7e463d2..4a97513 100644 anatop-max-voltage = <1450000>; }; -- reg_soc: regulator-vddsoc at 20c8140 { +- reg_soc: regulator-vddsoc@20c8140 { - reg = <0x20c8140>; + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; @@ -228,7 +228,7 @@ index 2b854d1..1818b6c 100644 - #address-cells = <1>; - #size-cells = <0>; -- reg_3p0: regulator-3p0 at 20c8110 { +- reg_3p0: regulator-3p0@20c8110 { - reg = <0x20c8110>; + reg_3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; @@ -238,7 +238,7 @@ index 2b854d1..1818b6c 100644 anatop-enable-bit = <0>; }; -- reg_arm: regulator-vddcore at 20c8140 { +- reg_arm: regulator-vddcore@20c8140 { - reg = <0x20c8140>; + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; @@ -248,7 +248,7 @@ index 2b854d1..1818b6c 100644 anatop-max-voltage = <1450000>; }; -- reg_soc: regulator-vddsoc at 20c8140 { +- reg_soc: regulator-vddsoc@20c8140 { - reg = <0x20c8140>; + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; @@ -265,7 +265,7 @@ index b416d2b..99f92ec 100644 - #address-cells = <1>; - #size-cells = <0>; -- reg_1p0d: regulator-vdd1p0d at 30360210 { +- reg_1p0d: regulator-vdd1p0d@30360210 { - reg = <0x30360210>; + reg_1p0d: regulator-vdd1p0d { compatible = "fsl,anatop-regulator"; @@ -275,7 +275,7 @@ index b416d2b..99f92ec 100644 anatop-enable-bit = <0>; }; -- reg_1p2: regulator-vdd1p2 at 30360220 { +- reg_1p2: regulator-vdd1p2@30360220 { - reg = <0x30360220>; + reg_1p2: regulator-vdd1p2 { compatible = "fsl,anatop-regulator"; diff --git a/a/content_digest b/N1/content_digest index 4c233de..aedee04 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,7 +1,11 @@ - "From\0festevam@gmail.com (Fabio Estevam)\0" + "From\0Fabio Estevam <festevam@gmail.com>\0" "Subject\0[PATCH 1/3] ARM: dts: imx6/7: Remove unit-address from anatop regulators\0" "Date\0Thu, 10 May 2018 21:16:48 -0300\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0shawnguo@kernel.org\0" + "Cc\0Fabio Estevam <fabio.estevam@nxp.com>" + devicetree@vger.kernel.org + robh+dt@kernel.org + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "From: Fabio Estevam <fabio.estevam@nxp.com>\n" @@ -9,9 +13,9 @@ "Remove unit-address and reg property from anatop regulators to fix\n" "the following DTC warnings with W=1:\n" "\n" - "arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140)\n" - "arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140)\n" - "arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140)\n" + "arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140)\n" + "arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140)\n" + "arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140)\n" "\n" "Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>\n" "---\n" @@ -33,7 +37,7 @@ "-\t\t\t\t#address-cells = <1>;\n" "-\t\t\t\t#size-cells = <0>;\n" " \n" - "-\t\t\t\tregulator-1p1 at 20c8110 {\n" + "-\t\t\t\tregulator-1p1@20c8110 {\n" "-\t\t\t\t\treg = <0x20c8110>;\n" "+\t\t\t\tregulator-1p1 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -43,7 +47,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\tregulator-3p0 at 20c8120 {\n" + "-\t\t\t\tregulator-3p0@20c8120 {\n" "-\t\t\t\t\treg = <0x20c8120>;\n" "+\t\t\t\tregulator-3p0 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -53,7 +57,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\tregulator-2p5 at 20c8130 {\n" + "-\t\t\t\tregulator-2p5@20c8130 {\n" "-\t\t\t\t\treg = <0x20c8130>;\n" "+\t\t\t\tregulator-2p5 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -63,7 +67,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "-\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_arm: regulator-vddcore {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -73,7 +77,7 @@ " \t\t\t\t\tanatop-max-voltage = <1450000>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_pu: regulator-vddpu at 20c8140 {\n" + "-\t\t\t\treg_pu: regulator-vddpu@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_pu: regulator-vddpu {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -83,7 +87,7 @@ " \t\t\t\t\tanatop-max-voltage = <1450000>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "-\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_soc: regulator-vddsoc {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -100,7 +104,7 @@ "-\t\t\t\t#address-cells = <1>;\n" "-\t\t\t\t#size-cells = <0>;\n" " \n" - "-\t\t\t\tregulator-1p1 at 20c8110 {\n" + "-\t\t\t\tregulator-1p1@20c8110 {\n" "-\t\t\t\t\treg = <0x20c8110>;\n" "+\t\t\t\tregulator-1p1 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -110,7 +114,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\tregulator-3p0 at 20c8120 {\n" + "-\t\t\t\tregulator-3p0@20c8120 {\n" "-\t\t\t\t\treg = <0x20c8120>;\n" "+\t\t\t\tregulator-3p0 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -120,7 +124,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\tregulator-2p5 at 20c8130 {\n" + "-\t\t\t\tregulator-2p5@20c8130 {\n" "-\t\t\t\t\treg = <0x20c8130>;\n" "+\t\t\t\tregulator-2p5 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -130,7 +134,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "-\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_arm: regulator-vddcore {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -140,7 +144,7 @@ " \t\t\t\t\tanatop-max-voltage = <1450000>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_pu: regulator-vddpu at 20c8140 {\n" + "-\t\t\t\treg_pu: regulator-vddpu@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_pu: regulator-vddpu {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -150,7 +154,7 @@ " \t\t\t\t\tanatop-max-voltage = <1450000>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "-\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_soc: regulator-vddsoc {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -167,7 +171,7 @@ "-\t\t\t\t#address-cells = <1>;\n" "-\t\t\t\t#size-cells = <0>;\n" " \n" - "-\t\t\t\tregulator-1p1 at 20c8110 {\n" + "-\t\t\t\tregulator-1p1@20c8110 {\n" "-\t\t\t\t\treg = <0x20c8110>;\n" "+\t\t\t\tregulator-1p1 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -177,7 +181,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\tregulator-3p0 at 20c8120 {\n" + "-\t\t\t\tregulator-3p0@20c8120 {\n" "-\t\t\t\t\treg = <0x20c8120>;\n" "+\t\t\t\tregulator-3p0 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -187,7 +191,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\tregulator-2p5 at 20c8130 {\n" + "-\t\t\t\tregulator-2p5@20c8130 {\n" "-\t\t\t\t\treg = <0x20c8130>;\n" "+\t\t\t\tregulator-2p5 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -197,7 +201,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "-\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_arm: regulator-vddcore {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -207,7 +211,7 @@ " \t\t\t\t\tanatop-max-voltage = <1450000>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_pcie: regulator-vddpcie at 20c8140 {\n" + "-\t\t\t\treg_pcie: regulator-vddpcie@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_pcie: regulator-vddpcie {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -217,7 +221,7 @@ " \t\t\t\t\tanatop-max-voltage = <1450000>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "-\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_soc: regulator-vddsoc {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -234,7 +238,7 @@ "-\t\t\t\t#address-cells = <1>;\n" "-\t\t\t\t#size-cells = <0>;\n" " \n" - "-\t\t\t\treg_3p0: regulator-3p0 at 20c8110 {\n" + "-\t\t\t\treg_3p0: regulator-3p0@20c8110 {\n" "-\t\t\t\t\treg = <0x20c8110>;\n" "+\t\t\t\treg_3p0: regulator-3p0 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -244,7 +248,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "-\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_arm: regulator-vddcore {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -254,7 +258,7 @@ " \t\t\t\t\tanatop-max-voltage = <1450000>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "-\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "-\t\t\t\t\treg = <0x20c8140>;\n" "+\t\t\t\treg_soc: regulator-vddsoc {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -271,7 +275,7 @@ "-\t\t\t\t#address-cells = <1>;\n" "-\t\t\t\t#size-cells = <0>;\n" " \n" - "-\t\t\t\treg_1p0d: regulator-vdd1p0d at 30360210 {\n" + "-\t\t\t\treg_1p0d: regulator-vdd1p0d@30360210 {\n" "-\t\t\t\t\treg = <0x30360210>;\n" "+\t\t\t\treg_1p0d: regulator-vdd1p0d {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -281,7 +285,7 @@ " \t\t\t\t\tanatop-enable-bit = <0>;\n" " \t\t\t\t};\n" " \n" - "-\t\t\t\treg_1p2: regulator-vdd1p2 at 30360220 {\n" + "-\t\t\t\treg_1p2: regulator-vdd1p2@30360220 {\n" "-\t\t\t\t\treg = <0x30360220>;\n" "+\t\t\t\treg_1p2: regulator-vdd1p2 {\n" " \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -290,4 +294,4 @@ "-- \n" 2.7.4 -88350511385b3322f29402517610aa3143bd20be57f586b85d5f29b6d2fbce2f +4a2497f518a4b8c49bb3bbf1e1fbfe8de55abfcc6777d317107fddd7a456fe89
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