From: Alexandru Stefan ISAILA <aisaila@bitdefender.com>
To: "rcojocaru@bitdefender.com" <rcojocaru@bitdefender.com>,
"JBeulich@suse.com" <JBeulich@suse.com>,
"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>
Cc: "George.Dunlap@eu.citrix.com" <George.Dunlap@eu.citrix.com>,
"tamas@tklengyel.com" <tamas@tklengyel.com>,
"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Subject: Re: [PATCH v1 1/2] x86/mm: Add mem access rights to NPT
Date: Tue, 5 Jun 2018 14:45:32 +0000 [thread overview]
Message-ID: <1528209932.25123.27.camel@bitdefender.com> (raw)
In-Reply-To: <c9ff1b1a-5174-5072-34d5-1d5d2a7a0913@citrix.com>
On Mi, 2018-05-30 at 14:56 +0100, Andrew Cooper wrote:
> On 30/05/18 12:29, Jan Beulich wrote:
> >
> > >
> > > >
> > > > >
> > > > > On 30.05.18 at 13:20, <aisaila@bitdefender.com> wrote:
> > > On Mi, 2018-05-30 at 03:52 -0600, Jan Beulich wrote:
> > > >
> > > > >
> > > > > >
> > > > > > >
> > > > > > > On 30.05.18 at 11:04, <aisaila@bitdefender.com> wrote:
> > > > > Sorry for the misunderstanding, I wanted to clarify if the
> > > > > 59:56
> > > > > bits
> > > > > are fully ok to be used or if not then where should I use 4
> > > > > bits to
> > > > > store the mem access info?
> > > > I thought I had sufficiently explained this - you have two
> > > > options:
> > > > 1) Make sure (via some prereq patch(es)) bit 59 has no other
> > > > use, and
> > > > then use 59:56.
> > > > 2) Use another range that's provably having no other use, e.g.
> > > > 58:55.
> > > I've checked and bits 40:52 are defined in asm/page.h for page
> > > flags.
> > 40:52? Hardly.
> >
> > >
> > > I've tried bits 53:56 and there where some problems with the
> > > guest not
> > > starting or the image freezing,
> > Well, you'll have to explain this (perhaps just to yourself).
> >
> > >
> > > bits 62 and 63 are not free so 59:56 is
> > > the only space to be used for this purpose and is seems to
> > > function
> > > correctly.
> > Well - as said before, bit 59 is not available for use without some
> > prereq work.
> There are no software available bits in the top of an AMD IOMMU PTE.
> Bits 59:62 are defined, while bits 52:58 are strictly reserved and
> fault
> if used.
>
> I'm also not convinced of the safety of our current uses of bits 9:11
> which are software available in the regular pagetables, but have
> specific meaning in the IOMMU entries.
>
> If the code IOMMU code disables page sharing, then lets go one small
> step further and prohibit its use entirely. There is no point trying
> to
> maintain compatibility for an option which isn't used, especially if
> it
> gets in the way of improvements like this in the SVM code.
>
Another idea is to save the mem access info in a radix tree like on the
ARM side and we can store the radix tree root in the p2m_domain.
I think that this is the fastest and cleanest way to solve the free
bits problem.
Is this a suitable way to go?
Thanks,
Alex
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next prev parent reply other threads:[~2018-06-05 14:45 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-11 11:11 [PATCH v1 1/2] x86/mm: Add mem access rights to NPT Alexandru Isaila
2018-05-11 11:11 ` [PATCH v1 2/2] hvm/svm: Enable EMUL_UNIMPLEMENTED events on svm Alexandru Isaila
2018-05-14 17:56 ` Tamas K Lengyel
2018-05-18 15:32 ` Jan Beulich
2018-05-18 16:00 ` Tamas K Lengyel
2018-05-18 18:22 ` Razvan Cojocaru
2018-07-02 10:59 ` Jan Beulich
2018-07-02 11:29 ` Alexandru Stefan ISAILA
2018-07-05 13:35 ` Jan Beulich
2018-05-18 15:30 ` [PATCH v1 1/2] x86/mm: Add mem access rights to NPT Jan Beulich
2018-05-18 18:30 ` Razvan Cojocaru
2018-05-22 9:49 ` Jan Beulich
2018-05-22 13:35 ` Alexandru Stefan ISAILA
2018-05-22 13:44 ` Jan Beulich
2018-05-30 9:04 ` Alexandru Stefan ISAILA
2018-05-30 9:52 ` Jan Beulich
2018-05-30 11:20 ` Alexandru Stefan ISAILA
2018-05-30 11:29 ` Jan Beulich
2018-05-30 13:56 ` Andrew Cooper
2018-06-05 14:45 ` Alexandru Stefan ISAILA [this message]
2018-06-05 15:38 ` Jan Beulich
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