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From: Kenneth Feng <kenneth.feng-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Kenneth Feng <kenneth.feng-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH] drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD
Date: Tue, 12 Jun 2018 22:54:13 +0800	[thread overview]
Message-ID: <1528815253-14142-1-git-send-email-kenneth.feng@amd.com> (raw)

Fix the issue that SCLK&MCLK can't be set higher than dpm7 when
OD is enabled in SMU7.

Change-Id: If8249795739e29a063154cffce693b3c77cca151
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b763c54..11e1762 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3762,7 +3762,10 @@ static int smu7_generate_dpm_level_enable_mask(
 	const struct smu7_power_state *smu7_ps =
 			cast_const_phw_smu7_power_state(states->pnew_state);
 
-	result = smu7_trim_dpm_states(hwmgr, smu7_ps);
+	/*skip the trim if od is enabled*/
+	if (!hwmgr->od_enabled)
+		result = smu7_trim_dpm_states(hwmgr, smu7_ps);
+
 	if (result)
 		return result;
 
-- 
2.7.4

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             reply	other threads:[~2018-06-12 14:54 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 14:54 Kenneth Feng [this message]
     [not found] ` <1528815253-14142-1-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
2018-06-12 15:01   ` [PATCH] drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD Zhu, Rex
     [not found]     ` <CY4PR12MB1687467F513BB24796B1FC63FB7F0-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-06-12 20:29       ` Deucher, Alexander

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