From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH 13/28] drm/mediatek: add connection from RDMA0 to DSI3 Date: Wed, 13 Jun 2018 13:45:51 +0800 Message-ID: <1528868751.15127.10.camel@mtksdaap41> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-14-git-send-email-stu.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1528687580-549-14-git-send-email-stu.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stu Hsieh Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFN0dToKClR3byBpbmxpbmUgY29tbWVudC4KCk9uIE1vbiwgMjAxOC0wNi0xMSBhdCAxMToy NiArMDgwMCwgU3R1IEhzaWVoIHdyb3RlOgo+IFRoaXMgcGF0Y2ggYWRkIHRoZSBjb25uZWN0aW9u IGZyb20gUkRNQTAgdG8gRFNJMwo+IAo+IFNpZ25lZC1vZmYtYnk6IFN0dSBIc2llaCA8c3R1Lmhz aWVoQG1lZGlhdGVrLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k cm1fZGRwLmMgICAgICB8IDQgKysrKwo+ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Ry bV9kZHBfY29tcC5jIHwgMiArLQo+ICAyIGZpbGVzIGNoYW5nZWQsIDUgaW5zZXJ0aW9ucygrKSwg MSBkZWxldGlvbigtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsv bXRrX2RybV9kZHAuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5jCj4g aW5kZXggYzA4YWVkOGRhZTQ0Li5mZWQxYjU3MDQzNTUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9n cHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvbXRrX2RybV9kZHAuYwo+IEBAIC04Myw2ICs4Myw3IEBACj4gICNkZWZpbmUgR0FNTUFf TU9VVF9FTl9SRE1BMQkJMHgxCj4gICNkZWZpbmUgUkRNQTBfTU9VVF9EUEkwCQkJMHgyCj4gICNk ZWZpbmUgUkRNQTBfTU9VVF9EU0kyCQkJMHg0Cj4gKyNkZWZpbmUgUkRNQTBfTU9VVF9EU0kzCQkJ MHg1CgpVc3VhbGx5LCBlYWNoIGJpdCBvZiBhIG1vdXQgcmVnaXN0ZXIgcmVwcmVzZW50IGEgb3V0 cHV0IGVuYWJsZS4gSXMgdGhpcwp2YWx1ZSAweDUgaXMgYSBjb3JyZWN0IHZhbHVlPwoKPiAgI2Rl ZmluZSBSRE1BMV9NT1VUX0RQSTAJCQkweDIKPiAgI2RlZmluZSBEUEkwX1NFTF9JTl9SRE1BMQkJ MHgxCj4gICNkZWZpbmUgQ09MT1IxX1NFTF9JTl9PVkwxCQkweDEKPiBAQCAtMTY0LDYgKzE2NSw5 IEBAIHN0YXRpYyB1bnNpZ25lZCBpbnQgbXRrX2RkcF9tb3V0X2VuKGVudW0gbXRrX2RkcF9jb21w X2lkIGN1ciwKPiAgCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTAgJiYgbmV4 dCA9PSBERFBfQ09NUE9ORU5UX0RTSTIpIHsKPiAgCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19E SVNQX1JETUEwX01PVVRfRU47Cj4gIAkJdmFsdWUgPSBSRE1BMF9NT1VUX0RTSTI7Cj4gKwl9IGVs c2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEwICYmIG5leHQgPT0gRERQX0NPTVBPTkVO VF9EU0kzKSB7Cj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9SRE1BMF9NT1VUX0VO Owo+ICsJCXZhbHVlID0gUkRNQTBfTU9VVF9EU0kzOwo+ICAJfSBlbHNlIGlmIChjdXIgPT0gRERQ X0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMCkgewo+ICAJCSph ZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTFfTU9VVF9FTjsKPiAgCQl2YWx1ZSA9IFJE TUExX01PVVRfRFBJMDsKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210 a19kcm1fZGRwX2NvbXAuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9j b21wLmMKPiBpbmRleCBmZTZmZGMwMjFmYzcuLjIyZjRjNzJmYTc4NSAxMDA2NDQKPiAtLS0gYS9k cml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jCj4gKysrIGIvZHJpdmVy cy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuYwo+IEBAIC0yMjgsNyArMjI4LDcg QEAgc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfZGRwX2NvbXBfbWF0Y2ggbXRrX2RkcF9tYXRjaGVz W0REUF9DT01QT05FTlRfSURfTUFYXSA9IHsKPiAgCVtERFBfQ09NUE9ORU5UX0RTSTBdCT0geyBN VEtfRFNJLAkJMCwgTlVMTCB9LAo+ICAJW0REUF9DT01QT05FTlRfRFNJMV0JPSB7IE1US19EU0ks CQkxLCBOVUxMIH0sCj4gIAlbRERQX0NPTVBPTkVOVF9EU0kyXQk9IHsgTVRLX0RTSSwJCTIsIE5V TEwgfSwKPiAtCVtERFBfQ09NUE9ORU5UX0RTSTJdCT0geyBNVEtfRFNJLAkJMywgTlVMTCB9LAo+ ICsJW0REUF9DT01QT05FTlRfRFNJM10JPSB7IE1US19EU0ksCQkzLCBOVUxMIH0sCgpJIHRoaW5r IHRoaXMgaXMgbm90IHJlbGF0ZWQgdG8gdGhpcyBwYXRjaC4KClJlZ2FyZHMsCkNLCgo+ICAJW0RE UF9DT01QT05FTlRfR0FNTUFdCT0geyBNVEtfRElTUF9HQU1NQSwJMCwgJmRkcF9nYW1tYSB9LAo+ ICAJW0REUF9DT01QT05FTlRfT0QwXQk9IHsgTVRLX0RJU1BfT0QsCTAsICZkZHBfb2QgfSwKPiAg CVtERFBfQ09NUE9ORU5UX09EMV0JPSB7IE1US19ESVNQX09ELAkxLCAmZGRwX29kIH0sCgoKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1h aWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMu ZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: ck.hu@mediatek.com (CK Hu) Date: Wed, 13 Jun 2018 13:45:51 +0800 Subject: [PATCH 13/28] drm/mediatek: add connection from RDMA0 to DSI3 In-Reply-To: <1528687580-549-14-git-send-email-stu.hsieh@mediatek.com> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-14-git-send-email-stu.hsieh@mediatek.com> Message-ID: <1528868751.15127.10.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Stu: Two inline comment. On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > This patch add the connection from RDMA0 to DSI3 > > Signed-off-by: Stu Hsieh > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index c08aed8dae44..fed1b5704355 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -83,6 +83,7 @@ > #define GAMMA_MOUT_EN_RDMA1 0x1 > #define RDMA0_MOUT_DPI0 0x2 > #define RDMA0_MOUT_DSI2 0x4 > +#define RDMA0_MOUT_DSI3 0x5 Usually, each bit of a mout register represent a output enable. Is this value 0x5 is a correct value? > #define RDMA1_MOUT_DPI0 0x2 > #define DPI0_SEL_IN_RDMA1 0x1 > #define COLOR1_SEL_IN_OVL1 0x1 > @@ -164,6 +165,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > *addr = DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN; > value = RDMA0_MOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN; > + value = RDMA0_MOUT_DSI3; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI0; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index fe6fdc021fc7..22f4c72fa785 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -228,7 +228,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 3, NULL }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, I think this is not related to this patch. Regards, CK > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id ACEB0C433EF for ; Wed, 13 Jun 2018 05:46:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6DCC82086A for ; Wed, 13 Jun 2018 05:46:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6DCC82086A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934272AbeFMFqH (ORCPT ); Wed, 13 Jun 2018 01:46:07 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:45059 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1754469AbeFMFqF (ORCPT ); Wed, 13 Jun 2018 01:46:05 -0400 X-UUID: a1d39078826f4bcfa184cea79f5f72af-20180613 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1721347134; Wed, 13 Jun 2018 13:45:59 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 13 Jun 2018 13:45:51 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 13 Jun 2018 13:45:51 +0800 Message-ID: <1528868751.15127.10.camel@mtksdaap41> Subject: Re: [PATCH 13/28] drm/mediatek: add connection from RDMA0 to DSI3 From: CK Hu To: Stu Hsieh CC: Philipp Zabel , David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , Date: Wed, 13 Jun 2018 13:45:51 +0800 In-Reply-To: <1528687580-549-14-git-send-email-stu.hsieh@mediatek.com> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-14-git-send-email-stu.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Stu: Two inline comment. On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > This patch add the connection from RDMA0 to DSI3 > > Signed-off-by: Stu Hsieh > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index c08aed8dae44..fed1b5704355 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -83,6 +83,7 @@ > #define GAMMA_MOUT_EN_RDMA1 0x1 > #define RDMA0_MOUT_DPI0 0x2 > #define RDMA0_MOUT_DSI2 0x4 > +#define RDMA0_MOUT_DSI3 0x5 Usually, each bit of a mout register represent a output enable. Is this value 0x5 is a correct value? > #define RDMA1_MOUT_DPI0 0x2 > #define DPI0_SEL_IN_RDMA1 0x1 > #define COLOR1_SEL_IN_OVL1 0x1 > @@ -164,6 +165,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > *addr = DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN; > value = RDMA0_MOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN; > + value = RDMA0_MOUT_DSI3; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI0; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index fe6fdc021fc7..22f4c72fa785 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -228,7 +228,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 3, NULL }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, I think this is not related to this patch. Regards, CK > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },