From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH 16/28] drm/mediatek: add connection from RDMA1 to DSI2 Date: Wed, 13 Jun 2018 15:00:20 +0800 Message-ID: <1528873220.30263.2.camel@mtksdaap41> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-17-git-send-email-stu.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1528687580-549-17-git-send-email-stu.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stu Hsieh Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFN0dToKCk9uIE1vbiwgMjAxOC0wNi0xMSBhdCAxMToyNiArMDgwMCwgU3R1IEhzaWVoIHdy b3RlOgo+IFRoaXMgcGF0Y2ggYWRkIHRoZSBjb25uZWN0aW9uIGZyb20gUkRNQTEgdG8gRFNJMgo+ IAo+IFNpZ25lZC1vZmYtYnk6IFN0dSBIc2llaCA8c3R1LmhzaWVoQG1lZGlhdGVrLmNvbT4KClJl dmlld2VkLWJ5OiBDSyBIdSA8Y2suaHUgYXQgbWVkaWF0ZWsuY29tPgoKPiAtLS0KPiAgZHJpdmVy cy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMgfCA5ICsrKysrKysrKwo+ICAxIGZpbGUg Y2hhbmdlZCwgOSBpbnNlcnRpb25zKCspCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHJtX2RkcC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k cm1fZGRwLmMKPiBpbmRleCA3ZTRhZDU1ODBjZjYuLmMzZTY0N2IwNGZmZCAxMDA2NDQKPiAtLS0g YS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYwo+ICsrKyBiL2RyaXZlcnMv Z3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5jCj4gQEAgLTI4LDYgKzI4LDcgQEAKPiAgI2Rl ZmluZSBESVNQX1JFR19DT05GSUdfRElTUF9VRk9FX01PVVRfRU4JMHgwNTAKPiAgI2RlZmluZSBE SVNQX1JFR19DT05GSUdfRElTUF9DT0xPUjBfU0VMX0lOCTB4MDg0Cj4gICNkZWZpbmUgRElTUF9S RUdfQ09ORklHX0RJU1BfQ09MT1IxX1NFTF9JTgkweDA4OAo+ICsjZGVmaW5lIERJU1BfUkVHX0NP TkZJR19EU0lFX1NFTF9JTgkJMHgwYTQKPiAgI2RlZmluZSBESVNQX1JFR19DT05GSUdfRFNJT19T RUxfSU4JCTB4MGE4Cj4gICNkZWZpbmUgRElTUF9SRUdfQ09ORklHX0RQSV9TRUxfSU4JCTB4MGFj Cj4gICNkZWZpbmUgRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTBfTU9VVF9FTgkweDBjNAo+IEBA IC04NiwxMSArODcsMTMgQEAKPiAgI2RlZmluZSBSRE1BMF9NT1VUX0RTSTIJCQkweDQKPiAgI2Rl ZmluZSBSRE1BMF9NT1VUX0RTSTMJCQkweDUKPiAgI2RlZmluZSBSRE1BMV9NT1VUX0RTSTEJCQkw eDEKPiArI2RlZmluZSBSRE1BMV9NT1VUX0RTSTIJCQkweDQKPiAgI2RlZmluZSBSRE1BMV9NT1VU X0RQSTAJCQkweDIKPiAgI2RlZmluZSBSRE1BMV9NT1VUX0RQSTEJCQkweDMKPiAgI2RlZmluZSBE UEkwX1NFTF9JTl9SRE1BMQkJMHgxCj4gICNkZWZpbmUgRFBJMV9TRUxfSU5fUkRNQTEJCSgweDEg PDwgOCkKPiAgI2RlZmluZSBEU0kxX1NFTF9JTl9SRE1BMQkJMHgxCj4gKyNkZWZpbmUgRFNJMl9T RUxfSU5fUkRNQTEJCSgweDEgPDwgMTYpCj4gICNkZWZpbmUgQ09MT1IxX1NFTF9JTl9PVkwxCQkw eDEKPiAgCj4gICNkZWZpbmUgT1ZMX01PVVRfRU5fUkRNQQkJMHgxCj4gQEAgLTE3Niw2ICsxNzks OSBAQCBzdGF0aWMgdW5zaWduZWQgaW50IG10a19kZHBfbW91dF9lbihlbnVtIG10a19kZHBfY29t cF9pZCBjdXIsCj4gIAl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUExICYmIG5l eHQgPT0gRERQX0NPTVBPTkVOVF9EU0kxKSB7Cj4gIAkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdf RElTUF9SRE1BMV9NT1VUX0VOOwo+ICAJCXZhbHVlID0gUkRNQTFfTU9VVF9EU0kxOwo+ICsJfSBl bHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09IEREUF9DT01QT05F TlRfRFNJMikgewo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTFfTU9VVF9F TjsKPiArCQl2YWx1ZSA9IFJETUExX01PVVRfRFNJMjsKPiAgCX0gZWxzZSBpZiAoY3VyID09IERE UF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQSTApIHsKPiAgCQkq YWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JETUExX01PVVRfRU47Cj4gIAkJdmFsdWUgPSBS RE1BMV9NT1VUX0RQSTA7Cj4gQEAgLTIwNyw2ICsyMTMsOSBAQCBzdGF0aWMgdW5zaWduZWQgaW50 IG10a19kZHBfc2VsX2luKGVudW0gbXRrX2RkcF9jb21wX2lkIGN1ciwKPiAgCX0gZWxzZSBpZiAo Y3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RTSTEp IHsKPiAgCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EU0lPX1NFTF9JTjsKPiAgCQl2YWx1ZSA9 IERTSTFfU0VMX0lOX1JETUExOwo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9S RE1BMSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMikgewo+ICsJCSphZGRyID0gRElTUF9S RUdfQ09ORklHX0RTSUVfU0VMX0lOOwo+ICsJCXZhbHVlID0gRFNJMl9TRUxfSU5fUkRNQTE7Cj4g IAl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX09WTDEgJiYgbmV4dCA9PSBERFBfQ09N UE9ORU5UX0NPTE9SMSkgewo+ICAJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfQ09MT1Ix X1NFTF9JTjsKPiAgCQl2YWx1ZSA9IENPTE9SMV9TRUxfSU5fT1ZMMTsKCgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0 CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3Rv cC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: ck.hu@mediatek.com (CK Hu) Date: Wed, 13 Jun 2018 15:00:20 +0800 Subject: [PATCH 16/28] drm/mediatek: add connection from RDMA1 to DSI2 In-Reply-To: <1528687580-549-17-git-send-email-stu.hsieh@mediatek.com> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-17-git-send-email-stu.hsieh@mediatek.com> Message-ID: <1528873220.30263.2.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Stu: On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > This patch add the connection from RDMA1 to DSI2 > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 7e4ad5580cf6..c3e647b04ffd 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -28,6 +28,7 @@ > #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > #define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4 > @@ -86,11 +87,13 @@ > #define RDMA0_MOUT_DSI2 0x4 > #define RDMA0_MOUT_DSI3 0x5 > #define RDMA1_MOUT_DSI1 0x1 > +#define RDMA1_MOUT_DSI2 0x4 > #define RDMA1_MOUT_DPI0 0x2 > #define RDMA1_MOUT_DPI1 0x3 > #define DPI0_SEL_IN_RDMA1 0x1 > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > #define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > #define COLOR1_SEL_IN_OVL1 0x1 > > #define OVL_MOUT_EN_RDMA 0x1 > @@ -176,6 +179,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > + value = RDMA1_MOUT_DSI2; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI0; > @@ -207,6 +213,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > value = COLOR1_SEL_IN_OVL1; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id 65D43C433EF for ; Wed, 13 Jun 2018 07:00:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 25F2D20693 for ; Wed, 13 Jun 2018 07:00:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 25F2D20693 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934491AbeFMHA0 (ORCPT ); Wed, 13 Jun 2018 03:00:26 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:55550 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S933318AbeFMHAZ (ORCPT ); Wed, 13 Jun 2018 03:00:25 -0400 X-UUID: 4810694ad5da4753b0eb64b8e596d0e6-20180613 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1449557878; Wed, 13 Jun 2018 15:00:22 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 13 Jun 2018 15:00:20 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 13 Jun 2018 15:00:20 +0800 Message-ID: <1528873220.30263.2.camel@mtksdaap41> Subject: Re: [PATCH 16/28] drm/mediatek: add connection from RDMA1 to DSI2 From: CK Hu To: Stu Hsieh CC: Philipp Zabel , David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , Date: Wed, 13 Jun 2018 15:00:20 +0800 In-Reply-To: <1528687580-549-17-git-send-email-stu.hsieh@mediatek.com> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-17-git-send-email-stu.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Stu: On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > This patch add the connection from RDMA1 to DSI2 > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 7e4ad5580cf6..c3e647b04ffd 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -28,6 +28,7 @@ > #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > #define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4 > @@ -86,11 +87,13 @@ > #define RDMA0_MOUT_DSI2 0x4 > #define RDMA0_MOUT_DSI3 0x5 > #define RDMA1_MOUT_DSI1 0x1 > +#define RDMA1_MOUT_DSI2 0x4 > #define RDMA1_MOUT_DPI0 0x2 > #define RDMA1_MOUT_DPI1 0x3 > #define DPI0_SEL_IN_RDMA1 0x1 > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > #define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > #define COLOR1_SEL_IN_OVL1 0x1 > > #define OVL_MOUT_EN_RDMA 0x1 > @@ -176,6 +179,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > + value = RDMA1_MOUT_DSI2; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI0; > @@ -207,6 +213,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > value = COLOR1_SEL_IN_OVL1;