From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stu Hsieh Subject: Re: [PATCH 14/28] drm/mediatek: add connection from RDMA1 to DPI1 Date: Wed, 13 Jun 2018 15:56:14 +0800 Message-ID: <1528876574.11190.32.camel@mtksdccf07> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-15-git-send-email-stu.hsieh@mediatek.com> <1528870410.15127.11.camel@mtksdaap41> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1528870410.15127.11.camel@mtksdaap41> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: CK Hu Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIENLOgoKT24gV2VkLCAyMDE4LTA2LTEzIGF0IDE0OjEzICswODAwLCBDSyBIdSB3cm90ZToK PiBIaSwgU3R1Ogo+IAo+IE9uIE1vbiwgMjAxOC0wNi0xMSBhdCAxMToyNiArMDgwMCwgU3R1IEhz aWVoIHdyb3RlOgo+ID4gVGhpcyBwYXRjaCBhZGQgdGhlIGNvbm5lY3Rpb24gZnJvbSBSRE1BMSB0 byBEUEkxCj4gPiAKPiA+IFNpZ25lZC1vZmYtYnk6IFN0dSBIc2llaCA8c3R1LmhzaWVoQG1lZGlh dGVrLmNvbT4KPiA+IC0tLQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rk cC5jIHwgOCArKysrKysrKwo+ID4gIDEgZmlsZSBjaGFuZ2VkLCA4IGluc2VydGlvbnMoKykKPiA+ IAo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5j IGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMKPiA+IGluZGV4IGZlZDFi NTcwNDM1NS4uNGFiZDVkYWJlY2NmIDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fZGRwLmMKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZHJtX2RkcC5jCj4gPiBAQCAtODUsNyArODUsOSBAQAo+ID4gICNkZWZpbmUgUkRNQTBfTU9V VF9EU0kyCQkJMHg0Cj4gPiAgI2RlZmluZSBSRE1BMF9NT1VUX0RTSTMJCQkweDUKPiA+ICAjZGVm aW5lIFJETUExX01PVVRfRFBJMAkJCTB4Mgo+ID4gKyNkZWZpbmUgUkRNQTFfTU9VVF9EUEkxCQkJ MHgzCj4gCj4gVXN1YWxseSwgZWFjaCBiaXQgb2YgYSBtb3V0IHJlZ2lzdGVyIHJlcHJlc2VudCBh IG91dHB1dCBlbmFibGUuIElzIHRoaXMKPiB2YWx1ZSAweDMgYSBjb3JyZWN0IHZhbHVlPwo+IAo+ IFJlZ2FyZHMsCj4gQ0sKPiAKSW4gSFcgQ09ORklHIFNQRUMgc2hvdyBhcyBmb2xsb3dpbmcKCkJp dChzKQlOYW1lCQkJRGVzY3JpcHRpb24KMjowCURJU1BfUEFUSDFfU09VVF9TRUxfSU4JMCA6IE91 dHB1dCB0byBEU0kwCgkJCQkxOiAgT291dHB1dCB0byBEU0kxCgkJCQkyOiAgT291dHB1dCB0byBE UEkKCQkJCTM6ICBPb3V0cHV0IHRvIERQSTEKCQkJCTQ6ICBPb3V0cHV0IHRvIERTSTIKCQkJCTU6 ICBPb3V0cHV0IHRvIERTSTMKCQkJCTYgOiByZXNlcnZlZAoJCQkJNzogIE9vdXRwdXQgdG8gRElT UF9VRk9FCgpTbywgMHgzIGlzIGNvcnJlY3QgdmFsdWUKClJlZ2FyZCwKU3R1CgoKPiA+ICAjZGVm aW5lIERQSTBfU0VMX0lOX1JETUExCQkweDEKPiA+ICsjZGVmaW5lIERQSTFfU0VMX0lOX1JETUEx CQkoMHgxIDw8IDgpCj4gPiAgI2RlZmluZSBDT0xPUjFfU0VMX0lOX09WTDEJCTB4MQo+ID4gIAo+ ID4gICNkZWZpbmUgT1ZMX01PVVRfRU5fUkRNQQkJMHgxCj4gPiBAQCAtMTcxLDYgKzE3Myw5IEBA IHN0YXRpYyB1bnNpZ25lZCBpbnQgbXRrX2RkcF9tb3V0X2VuKGVudW0gbXRrX2RkcF9jb21wX2lk IGN1ciwKPiA+ICAJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0 ID09IEREUF9DT01QT05FTlRfRFBJMCkgewo+ID4gIAkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdf RElTUF9SRE1BMV9NT1VUX0VOOwo+ID4gIAkJdmFsdWUgPSBSRE1BMV9NT1VUX0RQSTA7Cj4gPiAr CX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09N UE9ORU5UX0RQSTEpIHsKPiA+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTFf TU9VVF9FTjsKPiA+ICsJCXZhbHVlID0gUkRNQTFfTU9VVF9EUEkxOwo+ID4gIAl9IGVsc2Ugewo+ ID4gIAkJdmFsdWUgPSAwOwo+ID4gIAl9Cj4gPiBAQCAtMTkwLDYgKzE5NSw5IEBAIHN0YXRpYyB1 bnNpZ25lZCBpbnQgbXRrX2RkcF9zZWxfaW4oZW51bSBtdGtfZGRwX2NvbXBfaWQgY3VyLAo+ID4g IAl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUExICYmIG5leHQgPT0gRERQX0NP TVBPTkVOVF9EUEkwKSB7Cj4gPiAgCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EUElfU0VMX0lO Owo+ID4gIAkJdmFsdWUgPSBEUEkwX1NFTF9JTl9SRE1BMTsKPiA+ICsJfSBlbHNlIGlmIChjdXIg PT0gRERQX0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMSkgewo+ ID4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRFBJX1NFTF9JTjsKPiA+ICsJCXZhbHVlID0g RFBJMV9TRUxfSU5fUkRNQTE7Cj4gPiAgCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRf T1ZMMSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfQ09MT1IxKSB7Cj4gPiAgCQkqYWRkciA9IERJ U1BfUkVHX0NPTkZJR19ESVNQX0NPTE9SMV9TRUxfSU47Cj4gPiAgCQl2YWx1ZSA9IENPTE9SMV9T RUxfSU5fT1ZMMTsKPiAKPiAKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVz a3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9k cmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: stu.hsieh@mediatek.com (Stu Hsieh) Date: Wed, 13 Jun 2018 15:56:14 +0800 Subject: [PATCH 14/28] drm/mediatek: add connection from RDMA1 to DPI1 In-Reply-To: <1528870410.15127.11.camel@mtksdaap41> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-15-git-send-email-stu.hsieh@mediatek.com> <1528870410.15127.11.camel@mtksdaap41> Message-ID: <1528876574.11190.32.camel@mtksdccf07> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, CK: On Wed, 2018-06-13 at 14:13 +0800, CK Hu wrote: > Hi, Stu: > > On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > > This patch add the connection from RDMA1 to DPI1 > > > > Signed-off-by: Stu Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index fed1b5704355..4abd5dabeccf 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -85,7 +85,9 @@ > > #define RDMA0_MOUT_DSI2 0x4 > > #define RDMA0_MOUT_DSI3 0x5 > > #define RDMA1_MOUT_DPI0 0x2 > > +#define RDMA1_MOUT_DPI1 0x3 > > Usually, each bit of a mout register represent a output enable. Is this > value 0x3 a correct value? > > Regards, > CK > In HW CONFIG SPEC show as following Bit(s) Name Description 2:0 DISP_PATH1_SOUT_SEL_IN 0 : Output to DSI0 1: Ooutput to DSI1 2: Ooutput to DPI 3: Ooutput to DPI1 4: Ooutput to DSI2 5: Ooutput to DSI3 6 : reserved 7: Ooutput to DISP_UFOE So, 0x3 is correct value Regard, Stu > > #define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > #define COLOR1_SEL_IN_OVL1 0x1 > > > > #define OVL_MOUT_EN_RDMA 0x1 > > @@ -171,6 +173,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > > value = RDMA1_MOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > > + value = RDMA1_MOUT_DPI1; > > } else { > > value = 0; > > } > > @@ -190,6 +195,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > value = COLOR1_SEL_IN_OVL1; > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id 3A835C433EF for ; Wed, 13 Jun 2018 07:56:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF8C12086A for ; Wed, 13 Jun 2018 07:56:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF8C12086A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754530AbeFMH40 (ORCPT ); Wed, 13 Jun 2018 03:56:26 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:24047 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S934124AbeFMH4Z (ORCPT ); Wed, 13 Jun 2018 03:56:25 -0400 X-UUID: dd5e41dd33a84596a40c37ae71fab719-20180613 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1179570235; Wed, 13 Jun 2018 15:56:22 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 13 Jun 2018 15:56:14 +0800 Received: from [172.21.84.99] (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 13 Jun 2018 15:56:14 +0800 Message-ID: <1528876574.11190.32.camel@mtksdccf07> Subject: Re: [PATCH 14/28] drm/mediatek: add connection from RDMA1 to DPI1 From: Stu Hsieh To: CK Hu CC: Philipp Zabel , David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , Date: Wed, 13 Jun 2018 15:56:14 +0800 In-Reply-To: <1528870410.15127.11.camel@mtksdaap41> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-15-git-send-email-stu.hsieh@mediatek.com> <1528870410.15127.11.camel@mtksdaap41> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, CK: On Wed, 2018-06-13 at 14:13 +0800, CK Hu wrote: > Hi, Stu: > > On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > > This patch add the connection from RDMA1 to DPI1 > > > > Signed-off-by: Stu Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index fed1b5704355..4abd5dabeccf 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -85,7 +85,9 @@ > > #define RDMA0_MOUT_DSI2 0x4 > > #define RDMA0_MOUT_DSI3 0x5 > > #define RDMA1_MOUT_DPI0 0x2 > > +#define RDMA1_MOUT_DPI1 0x3 > > Usually, each bit of a mout register represent a output enable. Is this > value 0x3 a correct value? > > Regards, > CK > In HW CONFIG SPEC show as following Bit(s) Name Description 2:0 DISP_PATH1_SOUT_SEL_IN 0 : Output to DSI0 1: Ooutput to DSI1 2: Ooutput to DPI 3: Ooutput to DPI1 4: Ooutput to DSI2 5: Ooutput to DSI3 6 : reserved 7: Ooutput to DISP_UFOE So, 0x3 is correct value Regard, Stu > > #define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > #define COLOR1_SEL_IN_OVL1 0x1 > > > > #define OVL_MOUT_EN_RDMA 0x1 > > @@ -171,6 +173,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > > value = RDMA1_MOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > > + value = RDMA1_MOUT_DPI1; > > } else { > > value = 0; > > } > > @@ -190,6 +195,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > value = COLOR1_SEL_IN_OVL1; > >