From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1 Date: Wed, 13 Jun 2018 17:01:01 +0800 Message-ID: <1528880461.18148.1.camel@mtksdaap41> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-20-git-send-email-stu.hsieh@mediatek.com> <1528874037.30263.6.camel@mtksdaap41> <1528876862.11190.35.camel@mtksdccf07> <1528877675.30263.27.camel@mtksdaap41> <1528880291.11190.45.camel@mtksdccf07> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1528880291.11190.45.camel@mtksdccf07> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stu Hsieh Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFN0dToKCk9uIFdlZCwgMjAxOC0wNi0xMyBhdCAxNjo1OCArMDgwMCwgU3R1IEhzaWVoIHdy b3RlOgo+IEhpLCBDSzoKPiAKPiBPbiBXZWQsIDIwMTgtMDYtMTMgYXQgMTY6MTQgKzA4MDAsIENL IEh1IHdyb3RlOgo+ID4gSGksIFN0dToKPiA+IAo+ID4gT24gV2VkLCAyMDE4LTA2LTEzIGF0IDE2 OjAxICswODAwLCBTdHUgSHNpZWggd3JvdGU6Cj4gPiA+IEhpLCBDSzoKPiA+ID4gCj4gPiA+IAo+ ID4gPiBPbiBXZWQsIDIwMTgtMDYtMTMgYXQgMTU6MTMgKzA4MDAsIENLIEh1IHdyb3RlOgo+ID4g PiA+IEhpLCBTdHU6Cj4gPiA+ID4gCj4gPiA+ID4gT24gTW9uLCAyMDE4LTA2LTExIGF0IDExOjI2 ICswODAwLCBTdHUgSHNpZWggd3JvdGU6Cj4gPiA+ID4gPiBUaGlzIHBhdGNoIGFkZCB0aGUgY29u bmVjdGlvbiBmcm9tIFJETUEyIHRvIERQSTEKPiA+ID4gPiA+IAo+ID4gPiA+ID4gU2lnbmVkLW9m Zi1ieTogU3R1IEhzaWVoIDxzdHUuaHNpZWhAbWVkaWF0ZWsuY29tPgo+ID4gPiA+ID4gLS0tCj4g PiA+ID4gPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMgfCA4ICsrKysr KysrCj4gPiA+ID4gPiAgMSBmaWxlIGNoYW5nZWQsIDggaW5zZXJ0aW9ucygrKQo+ID4gPiA+ID4g Cj4gPiA+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1f ZGRwLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYwo+ID4gPiA+ID4g aW5kZXggMzFhMDgzMmVmOWVjLi4yZDg4MzgxNWQ3OWMgMTAwNjQ0Cj4gPiA+ID4gPiAtLS0gYS9k cml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYwo+ID4gPiA+ID4gKysrIGIvZHJp dmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMKPiA+ID4gPiA+IEBAIC05Myw5ICs5 MywxMSBAQAo+ID4gPiA+ID4gICNkZWZpbmUgUkRNQTFfTU9VVF9EUEkwCQkJMHgyCj4gPiA+ID4g PiAgI2RlZmluZSBSRE1BMV9NT1VUX0RQSTEJCQkweDMKPiA+ID4gPiA+ICAjZGVmaW5lIFJETUEy X01PVVRfRFBJMAkJCTB4Mgo+ID4gPiA+ID4gKyNkZWZpbmUgUkRNQTJfTU9VVF9EUEkxCQkJMHgz Cj4gPiA+ID4gCj4gPiA+ID4gVXN1YWxseSwgZWFjaCBiaXQgb2YgYSBtb3V0IHJlZ2lzdGVyIHJl cHJlc2VudCBhIG91dHB1dCBlbmFibGUuIElzIHRoaXMKPiA+ID4gPiB2YWx1ZSAweDMgYSBjb3Jy ZWN0IHZhbHVlPwo+ID4gPiA+IAo+ID4gPiA+IFJlZ2FyZHMsCj4gPiA+ID4gQ0sKPiA+ID4gPiAK PiA+ID4gSW4gSFcgQ09ORklHIFNQRUMgb3IgTVQyNzEyX0UyX01NU1lTX0NoYW5nZV9ub3RlIHNo b3cgYXMgZm9sbG93aW5nOgo+ID4gPiAKPiA+ID4gQml0KHMpCU5hbWUJCQlEZXNjcmlwdGlvbgo+ ID4gPiAyOjAJRElTUF9SRE1BMl9TT1VUX1NFTF9JTgkwOiBvdXRwdXQgdG8gZHNpMAo+ID4gPiAJ CQkJMTogb3V0cHR1IHRvIGRzaTEKPiA+ID4gCQkJCTI6IG91dHB1dCB0byBkcGkwCj4gPiA+IAkJ CQkzOiBvdXRwdXQgdG8gZHBpMQo+ID4gPiAJCQkJNDogb3V0cHV0IHRvIGRzaTIKPiA+ID4gCQkJ CTU6IG91dHB1dCB0byBkc2kzCj4gPiA+IAo+ID4gPiBTbywgMHgzIGlzIGNvcnJlY3QgdmFsdWUu Cj4gPiAKPiA+IFRoZSBkYXRhIHNoZWV0IHVzZSB0aGUgdGVybSBTT1VUIG1hdGNoIGl0cyBmdW5j dGlvbiwgc28gSSB0aGluayBkcml2ZXIKPiA+IGhhdmUgYmV0dGVyIGNoYW5nZSB0aGUgbmFtaW5n IHRvIFNPVVQuCj4gPiAKPiA+IFJlZ2FyZHMsCj4gPiBDSwo+ID4gCj4gCj4gVGhlIGRlZmluaXRp b24gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTJfU09VVCBpcyB1c2UgdGVybSBTT1VUIGluIHRo aXMKPiBwYXRjaC4KPiAKCkkga25vdywgYnV0IFJETUEyX01PVVRfRFBJMSBzaG91bGQgYmUgY2hh bmdlZCB0byBSRE1BMl9TT1VUX0RQSTEuCgpSZWdhcmRzLApDSwoKPiBSZWdhcmQsCj4gU3R1Cj4g Cj4gPiA+IAo+ID4gPiBSZWdhcmQsCj4gPiA+IFN0dQo+ID4gPiAKPiA+ID4gPiA+ICAjZGVmaW5l IERQSTBfU0VMX0lOX1JETUExCQkweDEKPiA+ID4gPiA+ICAjZGVmaW5lIERQSTBfU0VMX0lOX1JE TUEyCQkweDMKPiA+ID4gPiA+ICAjZGVmaW5lIERQSTFfU0VMX0lOX1JETUExCQkoMHgxIDw8IDgp Cj4gPiA+ID4gPiArI2RlZmluZSBEUEkxX1NFTF9JTl9SRE1BMgkJKDB4MyA8PCA4KQo+ID4gPiA+ ID4gICNkZWZpbmUgRFNJMV9TRUxfSU5fUkRNQTEJCTB4MQo+ID4gPiA+ID4gICNkZWZpbmUgRFNJ Ml9TRUxfSU5fUkRNQTEJCSgweDEgPDwgMTYpCj4gPiA+ID4gPiAgI2RlZmluZSBEU0kzX1NFTF9J Tl9SRE1BMQkJKDB4MSA8PCAxNikKPiA+ID4gPiA+IEBAIC0xOTksNiArMjAxLDkgQEAgc3RhdGlj IHVuc2lnbmVkIGludCBtdGtfZGRwX21vdXRfZW4oZW51bSBtdGtfZGRwX2NvbXBfaWQgY3VyLAo+ ID4gPiA+ID4gIAl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQg PT0gRERQX0NPTVBPTkVOVF9EUEkwKSB7Cj4gPiA+ID4gPiAgCQkqYWRkciA9IERJU1BfUkVHX0NP TkZJR19ESVNQX1JETUEyX1NPVVQ7Cj4gPiA+ID4gPiAgCQl2YWx1ZSA9IFJETUEyX01PVVRfRFBJ MDsKPiA+ID4gPiA+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMiAmJiBu ZXh0ID09IEREUF9DT01QT05FTlRfRFBJMSkgewo+ID4gPiA+ID4gKwkJKmFkZHIgPSBESVNQX1JF R19DT05GSUdfRElTUF9SRE1BMl9TT1VUOwo+ID4gPiA+ID4gKwkJdmFsdWUgPSBSRE1BMl9NT1VU X0RQSTE7Cj4gPiA+ID4gPiAgCX0gZWxzZSB7Cj4gPiA+ID4gPiAgCQl2YWx1ZSA9IDA7Cj4gPiA+ ID4gPiAgCX0KPiA+ID4gPiA+IEBAIC0yMzMsNiArMjM4LDkgQEAgc3RhdGljIHVuc2lnbmVkIGlu dCBtdGtfZGRwX3NlbF9pbihlbnVtIG10a19kZHBfY29tcF9pZCBjdXIsCj4gPiA+ID4gPiAgCX0g ZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTIgJiYgbmV4dCA9PSBERFBfQ09NUE9O RU5UX0RQSTApIHsKPiA+ID4gPiA+ICAJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RQSV9TRUxf SU47Cj4gPiA+ID4gPiAgCQl2YWx1ZSA9IERQSTBfU0VMX0lOX1JETUEyOwo+ID4gPiA+ID4gKwl9 IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQgPT0gRERQX0NPTVBP TkVOVF9EUEkxKSB7Cj4gPiA+ID4gPiArCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EUElfU0VM X0lOOwo+ID4gPiA+ID4gKwkJdmFsdWUgPSBEUEkxX1NFTF9JTl9SRE1BMjsKPiA+ID4gPiA+ICAJ fSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9PVkwxICYmIG5leHQgPT0gRERQX0NPTVBP TkVOVF9DT0xPUjEpIHsKPiA+ID4gPiA+ICAJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1Bf Q09MT1IxX1NFTF9JTjsKPiA+ID4gPiA+ICAJCXZhbHVlID0gQ09MT1IxX1NFTF9JTl9PVkwxOwo+ ID4gPiA+IAo+ID4gPiA+IAo+ID4gPiAKPiA+ID4gCj4gPiAKPiA+IAo+IAo+IAoKCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5n IGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVk ZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: ck.hu@mediatek.com (CK Hu) Date: Wed, 13 Jun 2018 17:01:01 +0800 Subject: [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1 In-Reply-To: <1528880291.11190.45.camel@mtksdccf07> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-20-git-send-email-stu.hsieh@mediatek.com> <1528874037.30263.6.camel@mtksdaap41> <1528876862.11190.35.camel@mtksdccf07> <1528877675.30263.27.camel@mtksdaap41> <1528880291.11190.45.camel@mtksdccf07> Message-ID: <1528880461.18148.1.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Stu: On Wed, 2018-06-13 at 16:58 +0800, Stu Hsieh wrote: > Hi, CK: > > On Wed, 2018-06-13 at 16:14 +0800, CK Hu wrote: > > Hi, Stu: > > > > On Wed, 2018-06-13 at 16:01 +0800, Stu Hsieh wrote: > > > Hi, CK: > > > > > > > > > On Wed, 2018-06-13 at 15:13 +0800, CK Hu wrote: > > > > Hi, Stu: > > > > > > > > On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > > > > > This patch add the connection from RDMA2 to DPI1 > > > > > > > > > > Signed-off-by: Stu Hsieh > > > > > --- > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ > > > > > 1 file changed, 8 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > > > index 31a0832ef9ec..2d883815d79c 100644 > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > > > @@ -93,9 +93,11 @@ > > > > > #define RDMA1_MOUT_DPI0 0x2 > > > > > #define RDMA1_MOUT_DPI1 0x3 > > > > > #define RDMA2_MOUT_DPI0 0x2 > > > > > +#define RDMA2_MOUT_DPI1 0x3 > > > > > > > > Usually, each bit of a mout register represent a output enable. Is this > > > > value 0x3 a correct value? > > > > > > > > Regards, > > > > CK > > > > > > > In HW CONFIG SPEC or MT2712_E2_MMSYS_Change_note show as following: > > > > > > Bit(s) Name Description > > > 2:0 DISP_RDMA2_SOUT_SEL_IN 0: output to dsi0 > > > 1: outptu to dsi1 > > > 2: output to dpi0 > > > 3: output to dpi1 > > > 4: output to dsi2 > > > 5: output to dsi3 > > > > > > So, 0x3 is correct value. > > > > The data sheet use the term SOUT match its function, so I think driver > > have better change the naming to SOUT. > > > > Regards, > > CK > > > > The definition DISP_REG_CONFIG_DISP_RDMA2_SOUT is use term SOUT in this > patch. > I know, but RDMA2_MOUT_DPI1 should be changed to RDMA2_SOUT_DPI1. Regards, CK > Regard, > Stu > > > > > > > Regard, > > > Stu > > > > > > > > #define DPI0_SEL_IN_RDMA1 0x1 > > > > > #define DPI0_SEL_IN_RDMA2 0x3 > > > > > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > > > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > > > > #define DSI1_SEL_IN_RDMA1 0x1 > > > > > #define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > > > > #define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > > > > @@ -199,6 +201,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > > > > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > > > > *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > > > > value = RDMA2_MOUT_DPI0; > > > > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > > > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > > > > + value = RDMA2_MOUT_DPI1; > > > > > } else { > > > > > value = 0; > > > > > } > > > > > @@ -233,6 +238,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > > > > > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > > > > *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > > > > value = DPI0_SEL_IN_RDMA2; > > > > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > > > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > > > > + value = DPI1_SEL_IN_RDMA2; > > > > > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > > > > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > > > > value = COLOR1_SEL_IN_OVL1; > > > > > > > > > > > > > > > > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: ** X-Spam-Status: No, score=2.1 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,UNPARSEABLE_RELAY,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id 27CCAC433EF for ; Wed, 13 Jun 2018 09:01:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D970620891 for ; Wed, 13 Jun 2018 09:01:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D970620891 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934893AbeFMJBK (ORCPT ); Wed, 13 Jun 2018 05:01:10 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34650 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750922AbeFMJBH (ORCPT ); Wed, 13 Jun 2018 05:01:07 -0400 X-UUID: a8fa29aec3314fd69014f21a0accf94d-20180613 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 386226893; Wed, 13 Jun 2018 17:01:02 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 13 Jun 2018 17:01:01 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 13 Jun 2018 17:01:01 +0800 Message-ID: <1528880461.18148.1.camel@mtksdaap41> Subject: Re: [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1 From: CK Hu To: Stu Hsieh CC: Philipp Zabel , David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , Date: Wed, 13 Jun 2018 17:01:01 +0800 In-Reply-To: <1528880291.11190.45.camel@mtksdccf07> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-20-git-send-email-stu.hsieh@mediatek.com> <1528874037.30263.6.camel@mtksdaap41> <1528876862.11190.35.camel@mtksdccf07> <1528877675.30263.27.camel@mtksdaap41> <1528880291.11190.45.camel@mtksdccf07> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Stu: On Wed, 2018-06-13 at 16:58 +0800, Stu Hsieh wrote: > Hi, CK: > > On Wed, 2018-06-13 at 16:14 +0800, CK Hu wrote: > > Hi, Stu: > > > > On Wed, 2018-06-13 at 16:01 +0800, Stu Hsieh wrote: > > > Hi, CK: > > > > > > > > > On Wed, 2018-06-13 at 15:13 +0800, CK Hu wrote: > > > > Hi, Stu: > > > > > > > > On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > > > > > This patch add the connection from RDMA2 to DPI1 > > > > > > > > > > Signed-off-by: Stu Hsieh > > > > > --- > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ > > > > > 1 file changed, 8 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > > > index 31a0832ef9ec..2d883815d79c 100644 > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > > > @@ -93,9 +93,11 @@ > > > > > #define RDMA1_MOUT_DPI0 0x2 > > > > > #define RDMA1_MOUT_DPI1 0x3 > > > > > #define RDMA2_MOUT_DPI0 0x2 > > > > > +#define RDMA2_MOUT_DPI1 0x3 > > > > > > > > Usually, each bit of a mout register represent a output enable. Is this > > > > value 0x3 a correct value? > > > > > > > > Regards, > > > > CK > > > > > > > In HW CONFIG SPEC or MT2712_E2_MMSYS_Change_note show as following: > > > > > > Bit(s) Name Description > > > 2:0 DISP_RDMA2_SOUT_SEL_IN 0: output to dsi0 > > > 1: outptu to dsi1 > > > 2: output to dpi0 > > > 3: output to dpi1 > > > 4: output to dsi2 > > > 5: output to dsi3 > > > > > > So, 0x3 is correct value. > > > > The data sheet use the term SOUT match its function, so I think driver > > have better change the naming to SOUT. > > > > Regards, > > CK > > > > The definition DISP_REG_CONFIG_DISP_RDMA2_SOUT is use term SOUT in this > patch. > I know, but RDMA2_MOUT_DPI1 should be changed to RDMA2_SOUT_DPI1. Regards, CK > Regard, > Stu > > > > > > > Regard, > > > Stu > > > > > > > > #define DPI0_SEL_IN_RDMA1 0x1 > > > > > #define DPI0_SEL_IN_RDMA2 0x3 > > > > > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > > > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > > > > #define DSI1_SEL_IN_RDMA1 0x1 > > > > > #define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > > > > #define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > > > > @@ -199,6 +201,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > > > > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > > > > *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > > > > value = RDMA2_MOUT_DPI0; > > > > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > > > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > > > > + value = RDMA2_MOUT_DPI1; > > > > > } else { > > > > > value = 0; > > > > > } > > > > > @@ -233,6 +238,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > > > > > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > > > > *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > > > > value = DPI0_SEL_IN_RDMA2; > > > > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > > > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > > > > + value = DPI1_SEL_IN_RDMA2; > > > > > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > > > > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > > > > value = COLOR1_SEL_IN_OVL1; > > > > > > > > > > > > > > > > > > > >