From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v3 4/7] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink
Date: Wed, 13 Jun 2018 15:01:48 -0700 [thread overview]
Message-ID: <1528927308.31662.49.camel@intel.com> (raw)
In-Reply-To: <68f6ecf94bc3afafee5c5fe632e8dcc397ff5b62.camel@intel.com>
On Wed, 2018-06-13 at 20:02 +0000, Souza, Jose wrote:
> On Wed, 2018-06-13 at 13:17 -0700, Dhinakaran Pandiyan wrote:
> >
> > On Tue, 2018-06-05 at 22:45 +0000, Souza, Jose wrote:
> > >
> > > On Tue, 2018-05-22 at 16:58 -0700, Dhinakaran Pandiyan wrote:
> > > >
> > > >
> > > > On Thu, 2018-05-17 at 15:21 -0700, José Roberto de Souza wrote:
> > > > >
> > > > >
> > > > > eDP spec states that sink device will do a short pulse in HPD
> > > > > line when there is a PSR/PSR2 error that needs to be handled
> > > > > by
> > > > > source, this is handling the first and most simples error:
> > > > > DP_PSR_SINK_INTERNAL_ERROR.
> > > > >
> > > > > Here taking the safest approach and disabling PSR(at least
> > > > > until
> > > > > the next modeset), to avoid multiple rendering issues due to
> > > > > bad pannels.
> > > > >
> > > > > v3:
> > > > > disabling PSR instead of exiting on error
> > > > >
> > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_dp.c | 2 ++
> > > > > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > > > > drivers/gpu/drm/i915/intel_psr.c | 62
> > > > > +++++++++++++++++++++++++-
> > > > > --
> > > > > --
> > > > > --
> > > > > 3 files changed, 52 insertions(+), 13 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index b86da48fd38e..fa2851d4fb36 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -4479,6 +4479,8 @@ intel_dp_short_pulse(struct intel_dp
> > > > > *intel_dp)
> > > > > if (intel_dp_needs_link_retrain(intel_dp))
> > > > > return false;
> > > > >
> > > > > + intel_psr_short_pulse(intel_dp);
> > > > > +
> > > > > if (intel_dp->compliance.test_type ==
> > > > > DP_TEST_LINK_TRAINING)
> > > > > {
> > > > > DRM_DEBUG_KMS("Link Training Compliance Test
> > > > > requested\n");
> > > > > /* Send a Hotplug Uevent to userspace to
> > > > > start
> > > > > modeset */
> > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > > index 4508be628450..892da65358e9 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > > @@ -1921,6 +1921,7 @@ void intel_psr_compute_config(struct
> > > > > intel_dp
> > > > > *intel_dp,
> > > > > struct intel_crtc_state
> > > > > *crtc_state);
> > > > > void intel_psr_irq_control(struct drm_i915_private
> > > > > *dev_priv,
> > > > > bool
> > > > > debug);
> > > > > void intel_psr_irq_handler(struct drm_i915_private
> > > > > *dev_priv,
> > > > > u32
> > > > > psr_iir);
> > > > > +void intel_psr_short_pulse(struct intel_dp *intel_dp);
> > > > >
> > > > > /* intel_runtime_pm.c */
> > > > > int intel_power_domains_init(struct drm_i915_private *);
> > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > index d88799482875..60797c8f9f0e 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > @@ -741,6 +741,23 @@ static void hsw_psr_disable(struct
> > > > > intel_dp
> > > > > *intel_dp)
> > > > > psr_aux_io_power_put(intel_dp);
> > > > > }
> > > > >
> > > > > +static void psr_disable(struct intel_dp *intel_dp)
> > nit: How about __psr_disable()? Might be worth checking other files
> > what the right convention is.
> It varies from file to file but inside of intel_psr.c we are not
> adding
> "__" so better keep that, right?
Sure, either way is okay with me.
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next prev parent reply other threads:[~2018-06-13 21:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-17 22:21 [PATCH v3 1/7] drm/i915/psr: Nuke PSR support for VLV and CHV José Roberto de Souza
2018-05-17 22:21 ` [PATCH v3 2/7] drm/i915/dp: Use intel_dp_aux_wait_done() to wait for previous aux xfer José Roberto de Souza
2018-06-06 23:47 ` Dhinakaran Pandiyan
2018-05-17 22:21 ` [PATCH v3 3/7] drm/i915/psr: Remove intel_crtc_state parameter from disable() José Roberto de Souza
2018-05-22 21:24 ` Dhinakaran Pandiyan
2018-05-17 22:21 ` [PATCH v3 4/7] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink José Roberto de Souza
2018-05-22 23:58 ` Dhinakaran Pandiyan
2018-06-05 22:45 ` Souza, Jose
2018-06-13 20:17 ` Dhinakaran Pandiyan
2018-06-13 20:02 ` Souza, Jose
2018-06-13 22:01 ` Dhinakaran Pandiyan [this message]
2018-05-17 22:21 ` [PATCH v3 5/7] drm/i915/psr: Handle PSR RFB storage error José Roberto de Souza
2018-06-13 23:00 ` Dhinakaran Pandiyan
2018-05-17 22:21 ` [PATCH v3 6/7] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side José Roberto de Souza
2018-05-23 0:02 ` Dhinakaran Pandiyan
2018-05-17 22:21 ` [PATCH v3 7/7] drm/i915/psr: Avoid PSR exit max time timeout José Roberto de Souza
2018-05-17 22:38 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV and CHV Patchwork
2018-05-17 22:40 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-17 22:55 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-18 4:28 ` ✗ Fi.CI.IGT: failure " Patchwork
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