From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Lankhorst, Maarten" Subject: Re: [v2] drm/i915: Enable hw workaround to bypass alpha Date: Fri, 22 Jun 2018 08:42:21 +0000 Message-ID: <1529656610.11846.10.camel@intel.com> References: <1529594036-25036-1-git-send-email-vandita.kulkarni@intel.com> <20180621210922.xerj5m5hxzjparnd@InViCtUs> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1755740661==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 513A76E328 for ; Fri, 22 Jun 2018 08:42:26 +0000 (UTC) In-Reply-To: <20180621210922.xerj5m5hxzjparnd@InViCtUs> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Sripada, Radhakrishna" , "Kulkarni, Vandita" Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org --===============1755740661== Content-Language: en-US Content-Type: multipart/signed; micalg=sha-1; protocol="application/x-pkcs7-signature"; boundary="=-/8NKyTIcYooDecMUPyzN" --=-/8NKyTIcYooDecMUPyzN Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable tor 2018-06-21 klockan 14:09 -0700 skrev Radhakrishna Sripada: > On Thu, Jun 21, 2018 at 08:43:56PM +0530, Vandita Kulkarni wrote: > > Alpha blending with alpha 0 and 0xff passes through > > alpha math and rounding logic causing differences > > compared to fully transparent or opaque plane,resulting > > in CRC mismatch. > > This WA on icl and above enables hardware to bypass alpha > > math and rounding for per pixel alpha values of 00 and 0xff > >=20 > > v2: Fix patchwork checkpatch warnings. > >=20 > > Signed-off-by: Vandita Kulkarni > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > > 2 files changed, 20 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 4bfd7a9..b66ec9b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7366,6 +7366,14 @@ enum { > > #define BDW_SCRATCH1 _MMIO( > > 0xb11c) > > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) > > =20 > > +/*GEN11 chicken */ > > +#define _PIPEA_CHICKEN 0x70038 > > +#define _PIPEB_CHICKEN 0x71038 > > +#define _PIPEC_CHICKEN 0x72038 > > +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, > > _PIPEA_CHICKEN,\ > > + _PIPEB_CHICKEN) > > + > > /* PCH */ > > =20 > > /* south display engine interrupt: IBX */ > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 2c8fef3..3d849ec 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct > > intel_crtc_state *pipe_config, > > struct intel_atomic_state *old_intel_state =3D > > to_intel_atomic_state(old_state); > > bool psl_clkgate_wa; > > + u32 pipe_chicken; > > =20 > > if (WARN_ON(intel_crtc->active)) > > return; > > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct > > intel_crtc_state *pipe_config, > > */ > > intel_color_load_luts(&pipe_config->base); > > =20 > > + /* > > + * Display WA #1153: enable hardware to bypass the alpha > > math > > + * and rounding for per-pixel values 00 and 0xff > > + */ > > + if (INTEL_GEN(dev_priv) >=3D 11) { > > + pipe_chicken =3D I915_READ(PIPE_CHICKEN(pipe)); > > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > > + pipe_chicken | > > PER_PIXEL_ALPHA_BYPASS_EN); > > + } >=20 > This would enable the wa by default for gen > 11. Would this impact > for non 00, 0xff alpha cases? > In other words, should we enable the wa only when alpha is 00/0xff > and not enable for other values? >=20 This is about per pixel values, unlike the plane alpha. This looks at the pixel contents, so if a pixel has (0xff, R, G, B), we pass through RGB unmodified. If it's (0x00, R, G, B), we do the same for the background pixel without introducing rounding errors. When we program plane alpha, we handle 0x00 by disabling the plane, and 0xff by disabling plane alpha and making the plane opaque. Thanks for the patch, pushed. :) ~Maarten --=-/8NKyTIcYooDecMUPyzN Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExCzAJBgUrDgMCGgUAMIAGCSqGSIb3DQEHAQAAoIIKfTCCBOsw ggPToAMCAQICEFLpAsoR6ESdlGU4L6MaMLswDQYJKoZIhvcNAQEFBQAwbzELMAkGA1UEBhMCU0Ux FDASBgNVBAoTC0FkZFRydXN0IEFCMSYwJAYDVQQLEx1BZGRUcnVzdCBFeHRlcm5hbCBUVFAgTmV0 d29yazEiMCAGA1UEAxMZQWRkVHJ1c3QgRXh0ZXJuYWwgQ0EgUm9vdDAeFw0xMzAzMTkwMDAwMDBa Fw0yMDA1MzAxMDQ4MzhaMHkxCzAJBgNVBAYTAlVTMQswCQYDVQQIEwJDQTEUMBIGA1UEBxMLU2Fu dGEgQ2xhcmExGjAYBgNVBAoTEUludGVsIENvcnBvcmF0aW9uMSswKQYDVQQDEyJJbnRlbCBFeHRl cm5hbCBCYXNpYyBJc3N1aW5nIENBIDRBMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA 4LDMgJ3YSVX6A9sE+jjH3b+F3Xa86z3LLKu/6WvjIdvUbxnoz2qnvl9UKQI3sE1zURQxrfgvtP0b Pgt1uDwAfLc6H5eqnyi+7FrPsTGCR4gwDmq1WkTQgNDNXUgb71e9/6sfq+WfCDpi8ScaglyLCRp7 ph/V60cbitBvnZFelKCDBh332S6KG3bAdnNGB/vk86bwDlY6omDs6/RsfNwzQVwo/M3oPrux6y6z yIoRulfkVENbM0/9RrzQOlyK4W5Vk4EEsfW2jlCV4W83QKqRccAKIUxw2q/HoHVPbbETrrLmE6RR Z/+eWlkGWl+mtx42HOgOmX0BRdTRo9vH7yeBowIDAQABo4IBdzCCAXMwHwYDVR0jBBgwFoAUrb2Y ejS0Jvf6xCZU7wO94CTLVBowHQYDVR0OBBYEFB5pKrTcKP5HGE4hCz+8rBEv8Jj1MA4GA1UdDwEB /wQEAwIBhjASBgNVHRMBAf8ECDAGAQH/AgEAMDYGA1UdJQQvMC0GCCsGAQUFBwMEBgorBgEEAYI3 CgMEBgorBgEEAYI3CgMMBgkrBgEEAYI3FQUwFwYDVR0gBBAwDjAMBgoqhkiG+E0BBQFpMEkGA1Ud HwRCMEAwPqA8oDqGOGh0dHA6Ly9jcmwudHJ1c3QtcHJvdmlkZXIuY29tL0FkZFRydXN0RXh0ZXJu YWxDQVJvb3QuY3JsMDoGCCsGAQUFBwEBBC4wLDAqBggrBgEFBQcwAYYeaHR0cDovL29jc3AudHJ1 c3QtcHJvdmlkZXIuY29tMDUGA1UdHgQuMCygKjALgQlpbnRlbC5jb20wG6AZBgorBgEEAYI3FAID oAsMCWludGVsLmNvbTANBgkqhkiG9w0BAQUFAAOCAQEAKcLNo/2So1Jnoi8G7W5Q6FSPq1fmyKW3 sSDf1amvyHkjEgd25n7MKRHGEmRxxoziPKpcmbfXYU+J0g560nCo5gPF78Wd7ZmzcmCcm1UFFfIx fw6QA19bRpTC8bMMaSSEl8y39Pgwa+HENmoPZsM63DdZ6ziDnPqcSbcfYs8qd/m5d22rpXq5IGVU tX6LX7R/hSSw/3sfATnBLgiJtilVyY7OGGmYKCAS2I04itvSS1WtecXTt9OZDyNbl7LtObBrgMLh ZkpJW+pOR9f3h5VG2S5uKkA7Th9NC9EoScdwQCAIw+UWKbSQ0Isj2UFL7fHKvmqWKVTL98sRzvI3 seNC4DCCBYowggRyoAMCAQICEzMAAKy/3G1bO81ImVcAAAAArL8wDQYJKoZIhvcNAQEFBQAweTEL MAkGA1UEBhMCVVMxCzAJBgNVBAgTAkNBMRQwEgYDVQQHEwtTYW50YSBDbGFyYTEaMBgGA1UEChMR SW50ZWwgQ29ycG9yYXRpb24xKzApBgNVBAMTIkludGVsIEV4dGVybmFsIEJhc2ljIElzc3Vpbmcg Q0EgNEEwHhcNMTcxMDIzMTMwNjAwWhcNMTgxMDE4MTMwNjAwWjBJMRswGQYDVQQDExJMYW5raG9y c3QsIE1hYXJ0ZW4xKjAoBgkqhkiG9w0BCQEWG21hYXJ0ZW4ubGFua2hvcnN0QGludGVsLmNvbTCC ASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKgdSd2jCANFF8kf/86t0JEJtzIGlarSmghj bT8yJW87KEyBSqKOOoN5fE/tZ0ahyLlsGeiXK+DsAowaP5GP4fMLBP+GUwab8IxTYEcF6ddxgT+F 63DO/sTzKtKyIfcPz0YEl2WPZaVBPRNPirHLjaqqvr6QbzrqHsTm6SpL605UBcZnf4BhHRrG0mrv 4hBwGj4HAglW2qEfHyPHJ2VGJXFk9fwYD4NZVvW/DGbM2UMcT9G+PWPpZwZB7tbO5MMEiJwbtNyX F2TV2+XSKn8UG1zPdFC7JTlLhsVFYM3NY6pi0lWk7rwsMgtYBGgv6zh8iLunLP0xuM+MQonT9KEo 9kkCAwEAAaOCAjkwggI1MB0GA1UdDgQWBBQzvZm2BWwDAD408y8HzIxxsewayTAfBgNVHSMEGDAW gBQeaSq03Cj+RxhOIQs/vKwRL/CY9TBlBgNVHR8EXjBcMFqgWKBWhlRodHRwOi8vd3d3LmludGVs LmNvbS9yZXBvc2l0b3J5L0NSTC9JbnRlbCUyMEV4dGVybmFsJTIwQmFzaWMlMjBJc3N1aW5nJTIw Q0ElMjA0QS5jcmwwgZ8GCCsGAQUFBwEBBIGSMIGPMGkGCCsGAQUFBzAChl1odHRwOi8vd3d3Lmlu dGVsLmNvbS9yZXBvc2l0b3J5L2NlcnRpZmljYXRlcy9JbnRlbCUyMEV4dGVybmFsJTIwQmFzaWMl MjBJc3N1aW5nJTIwQ0ElMjA0QS5jcnQwIgYIKwYBBQUHMAGGFmh0dHA6Ly9vY3NwLmludGVsLmNv bS8wCwYDVR0PBAQDAgeAMDwGCSsGAQQBgjcVBwQvMC0GJSsGAQQBgjcVCIbDjHWEmeVRg/2BKIWO n1OCkcAJZ4HevTmV8EMCAWQCAQkwHwYDVR0lBBgwFgYIKwYBBQUHAwQGCisGAQQBgjcKAwwwKQYJ KwYBBAGCNxUKBBwwGjAKBggrBgEFBQcDBDAMBgorBgEEAYI3CgMMMFMGA1UdEQRMMEqgKwYKKwYB BAGCNxQCA6AdDBttYWFydGVuLmxhbmtob3JzdEBpbnRlbC5jb22BG21hYXJ0ZW4ubGFua2hvcnN0 QGludGVsLmNvbTANBgkqhkiG9w0BAQUFAAOCAQEAJfZIpZQN1A6IaAcFZHe1oPyJW27+Jjg//4v4 E0ElHzO9OgQqqmZjngWwurgHmFpViwKkNeSN1xYHFt4+apmLzI6x7F3s3abJr5BpBv1vHqhL6cuS dFtsU8D24AhYoaWaYe3EhoDO8dG3VmO/vMarERoHokvqmSLVzZ+jeSRM/re/y+qkOfZNF62PRpvJ iAO71ed8USzrGowddFOshoXRnjvTPRIBzBHEVqJ/Ju0C5Vb2AwvRlXxzlcRw8BnwjFOJOig6x65o c18EGXYWYydy+h95Lq0DcqnLEvdRWFCLsKhG0lXa32Lb9CrcfDrXF/xnOb9dNXpJDGEhCPKvKDNm NjGCAhcwggITAgEBMIGQMHkxCzAJBgNVBAYTAlVTMQswCQYDVQQIEwJDQTEUMBIGA1UEBxMLU2Fu dGEgQ2xhcmExGjAYBgNVBAoTEUludGVsIENvcnBvcmF0aW9uMSswKQYDVQQDEyJJbnRlbCBFeHRl cm5hbCBCYXNpYyBJc3N1aW5nIENBIDRBAhMzAACsv9xtWzvNSJlXAAAAAKy/MAkGBSsOAwIaBQCg XTAYBgkqhkiG9w0BCQMxCwYJKoZIhvcNAQcBMBwGCSqGSIb3DQEJBTEPFw0xODA2MjIwODM2NTBa MCMGCSqGSIb3DQEJBDEWBBSK6UUO8Cl7Wh4D/iCCIhO+peE7zDANBgkqhkiG9w0BAQEFAASCAQB1 H5aXEC7AEcEKv+RGzVYxRTi0gbVuOzUf8E++oS1HTmrhsk6X3Lezg/lzJa+azrfB2VuhbGFvwME6 5l3r+xAhnbEkwJ9/PluK/Yu13RvHhejcpa8aR4GjMua4ZOWyDwnh0jAaUIi/7UE9s/fXJ9yEC1iy /osVmOLjNt7PY8ABIMzLB5SwGhK12p8rkkUI6Vwu/FEuBGkJb0w52xOwGPCPEHZyyvJbVlp7D02T 8G6mfNm4a9zrr/M+m1tNXSxJB7AIZ1qSFt/iikCM+8cntk8htPjZNWBBp+J9jswwe4K0KNV66Dt1 CF+97DdmT2u+VFpIhbv/G3z4+BTxKrTZy0LHAAAAAAAA --=-/8NKyTIcYooDecMUPyzN-- --===============1755740661== Content-Type: text/plain; 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