From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= Date: Fri, 13 Jul 2018 14:11:15 +0200 Subject: [U-Boot] [ v2 07/10] video: add support of STM32 MIPI DSI controller driver In-Reply-To: <1531483878-15217-1-git-send-email-yannick.fertre@st.com> References: <1531483878-15217-1-git-send-email-yannick.fertre@st.com> Message-ID: <1531483878-15217-8-git-send-email-yannick.fertre@st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Add the STM32 DSI controller driver that uses the Synopsys DesignWare MIPI DSI host controller bridge. Signed-off-by: Yannick Fertr=C3=A9 --- drivers/video/stm32/Kconfig | 10 + drivers/video/stm32/Makefile | 1 + drivers/video/stm32/stm32_dsi.c | 427 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 438 insertions(+) create mode 100644 drivers/video/stm32/stm32_dsi.c diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig index 78b1fac..5b5e2c4 100644 --- a/drivers/video/stm32/Kconfig +++ b/drivers/video/stm32/Kconfig @@ -13,6 +13,16 @@ menuconfig VIDEO_STM32 DSI. This option enables these supports which can be used on devices which have RGB TFT or DSI display connected. =20 +config VIDEO_STM32_DSI + bool "Enable STM32 DSI video support" + depends on VIDEO_STM32 + select VIDEO_MIPI_DSI + select VIDEO_BRIDGE + select VIDEO_DW_MIPI_DSI + help + This option enables support DSI internal bridge which can be used on + devices which have DSI devices connected. + config VIDEO_STM32_MAX_XRES int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_STM32 diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile index 7297e5f..f8b42d1 100644 --- a/drivers/video/stm32/Makefile +++ b/drivers/video/stm32/Makefile @@ -6,3 +6,4 @@ # Yannick Fertre =20 obj-${CONFIG_VIDEO_STM32} =3D stm32_ltdc.o +obj-${CONFIG_VIDEO_STM32_DSI} +=3D stm32_dsi.o diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_ds= i.c new file mode 100644 index 0000000..43da83d --- /dev/null +++ b/drivers/video/stm32/stm32_dsi.c @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 STMicroelectronics - All Rights Reserved + * Author(s): Philippe Cornu for STMicroelectronic= s. + * Yannick Fertre for STMicroelectronics. + * + * This MIPI DSI controller driver is inspired from the Linux Kernel driver + * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HWVER_130 0x31333000 /* IP version 1.30 */ +#define HWVER_131 0x31333100 /* IP version 1.31 */ + +/* DSI digital registers & bit definitions */ +#define DSI_VERSION 0x00 +#define VERSION GENMASK(31, 8) + +/* + * DSI wrapper registers & bit definitions + * Note: registers are named as in the Reference Manual + */ +#define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */ +#define WCFGR_DSIM BIT(0) /* DSI Mode */ +#define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */ + +#define DSI_WCR 0x0404 /* Wrapper Control Reg */ +#define WCR_DSIEN BIT(3) /* DSI ENable */ + +#define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */ +#define WISR_PLLLS BIT(8) /* PLL Lock Status */ +#define WISR_RRS BIT(12) /* Regulator Ready Status */ + +#define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */ +#define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */ +#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */ + +#define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */ +#define WRPCR_PLLEN BIT(0) /* PLL ENable */ +#define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */ +#define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */ +#define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */ +#define WRPCR_REGEN BIT(24) /* REGulator ENable */ +#define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */ +#define IDF_MIN 1 +#define IDF_MAX 7 +#define NDIV_MIN 10 +#define NDIV_MAX 125 +#define ODF_MIN 1 +#define ODF_MAX 8 + +/* dsi color format coding according to the datasheet */ +enum dsi_color { + DSI_RGB565_CONF1, + DSI_RGB565_CONF2, + DSI_RGB565_CONF3, + DSI_RGB666_CONF1, + DSI_RGB666_CONF2, + DSI_RGB888, +}; + +#define LANE_MIN_KBPS 31250 +#define LANE_MAX_KBPS 500000 + +/* Timeout for regulator on/off, pll lock/unlock & fifo empty */ +#define TIMEOUT_US 200000 + +struct stm32_dsi_priv { + struct mipi_dsi_device device; + void __iomem *base; + struct udevice *panel; + u32 pllref_clk; + u32 hw_version; + int lane_min_kbps; + int lane_max_kbps; +}; + +static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val) +{ + writel(val, dsi->base + reg); +} + +static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg) +{ + return readl(dsi->base + reg); +} + +static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask) +{ + dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); +} + +static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask) +{ + dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); +} + +static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg, + u32 mask, u32 val) +{ + dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); +} + +static enum dsi_color dsi_color_from_mipi(u32 fmt) +{ + switch (fmt) { + case MIPI_DSI_FMT_RGB888: + return DSI_RGB888; + case MIPI_DSI_FMT_RGB666: + return DSI_RGB666_CONF2; + case MIPI_DSI_FMT_RGB666_PACKED: + return DSI_RGB666_CONF1; + case MIPI_DSI_FMT_RGB565: + return DSI_RGB565_CONF1; + default: + pr_err("MIPI color invalid, so we use rgb888\n"); + } + return DSI_RGB888; +} + +static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int od= f) +{ + int divisor =3D idf * odf; + + /* prevent from division by 0 */ + if (!divisor) + return 0; + + return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor); +} + +static int dsi_pll_get_params(struct stm32_dsi_priv *dsi, + int clkin_khz, int clkout_khz, + int *idf, int *ndiv, int *odf) +{ + int i, o, n, n_min, n_max; + int fvco_min, fvco_max, delta, best_delta; /* all in khz */ + + /* Early checks preventing division by 0 & odd results */ + if (clkin_khz <=3D 0 || clkout_khz <=3D 0) + return -EINVAL; + + fvco_min =3D dsi->lane_min_kbps * 2 * ODF_MAX; + fvco_max =3D dsi->lane_max_kbps * 2 * ODF_MIN; + + best_delta =3D 1000000; /* big started value (1000000khz) */ + + for (i =3D IDF_MIN; i <=3D IDF_MAX; i++) { + /* Compute ndiv range according to Fvco */ + n_min =3D ((fvco_min * i) / (2 * clkin_khz)) + 1; + n_max =3D (fvco_max * i) / (2 * clkin_khz); + + /* No need to continue idf loop if we reach ndiv max */ + if (n_min >=3D NDIV_MAX) + break; + + /* Clamp ndiv to valid values */ + if (n_min < NDIV_MIN) + n_min =3D NDIV_MIN; + if (n_max > NDIV_MAX) + n_max =3D NDIV_MAX; + + for (o =3D ODF_MIN; o <=3D ODF_MAX; o *=3D 2) { + n =3D DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz); + /* Check ndiv according to vco range */ + if (n < n_min || n > n_max) + continue; + /* Check if new delta is better & saves parameters */ + delta =3D dsi_pll_get_clkout_khz(clkin_khz, i, n, o) - + clkout_khz; + if (delta < 0) + delta =3D -delta; + if (delta < best_delta) { + *idf =3D i; + *ndiv =3D n; + *odf =3D o; + best_delta =3D delta; + } + /* fast return in case of "perfect result" */ + if (!delta) + return 0; + } + } + + return 0; +} + +static int dsi_phy_init(void *priv_data) +{ + struct mipi_dsi_device *device =3D priv_data; + struct udevice *dev =3D device->dev; + struct stm32_dsi_priv *dsi =3D dev_get_priv(dev); + u32 val; + int ret; + + /* Enable the regulator */ + dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); + ret =3D readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, + TIMEOUT_US); + if (ret) { + dev_err(dev, "!TIMEOUT! waiting REGU\n"); + return ret; + } + + /* Enable the DSI PLL & wait for its lock */ + dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN); + ret =3D readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, + TIMEOUT_US); + if (ret) { + dev_err(dev, "!TIMEOUT! waiting PLL\n"); + return ret; + } + + /* Enable the DSI wrapper */ + dsi_set(dsi, DSI_WCR, WCR_DSIEN); + + return 0; +} + +static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timin= gs, + u32 lanes, u32 format, unsigned int *lane_mbps) +{ + struct mipi_dsi_device *device =3D priv_data; + struct udevice *dev =3D device->dev; + struct stm32_dsi_priv *dsi =3D dev_get_priv(dev); + int idf, ndiv, odf, pll_in_khz, pll_out_khz; + int ret, bpp; + u32 val; + + /* Update lane capabilities according to hw version */ + dsi->hw_version =3D dsi_read(dsi, DSI_VERSION) & VERSION; + dsi->lane_min_kbps =3D LANE_MIN_KBPS; + dsi->lane_max_kbps =3D LANE_MAX_KBPS; + if (dsi->hw_version =3D=3D HWVER_131) { + dsi->lane_min_kbps *=3D 2; + dsi->lane_max_kbps *=3D 2; + } + + pll_in_khz =3D dsi->pllref_clk / 1000; + + /* Compute requested pll out */ + bpp =3D mipi_dsi_pixel_format_to_bpp(format); + pll_out_khz =3D (timings->pixelclock.typ / 1000) * bpp / lanes; + /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ + pll_out_khz =3D (pll_out_khz * 12) / 10; + if (pll_out_khz > dsi->lane_max_kbps) { + pll_out_khz =3D dsi->lane_max_kbps; + dev_warn(dev, "Warning max phy mbps is used\n"); + } + if (pll_out_khz < dsi->lane_min_kbps) { + pll_out_khz =3D dsi->lane_min_kbps; + dev_warn(dev, "Warning min phy mbps is used\n"); + } + + /* Compute best pll parameters */ + idf =3D 0; + ndiv =3D 0; + odf =3D 0; + ret =3D dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, + &idf, &ndiv, &odf); + if (ret) { + dev_err(dev, "Warning dsi_pll_get_params(): bad params\n"); + return ret; + } + + /* Get the adjusted pll out value */ + pll_out_khz =3D dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); + + /* Set the PLL division factors */ + dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, + (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); + + /* Compute uix4 & set the bit period in high-speed mode */ + val =3D 4000000 / pll_out_khz; + dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); + + /* Select video mode by resetting DSIM bit */ + dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM); + + /* Select the color coding */ + dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX, + dsi_color_from_mipi(format) << 1); + + *lane_mbps =3D pll_out_khz / 1000; + + debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", + pll_in_khz, pll_out_khz, *lane_mbps); + + return 0; +} + +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops =3D { + .init =3D dsi_phy_init, + .get_lane_mbps =3D dsi_get_lane_mbps, +}; + +static int stm32_dsi_attach(struct udevice *dev) +{ + struct stm32_dsi_priv *priv =3D dev_get_priv(dev); + struct dw_mipi_dsi_plat_data *platdata =3D dev_get_platdata(dev); + struct mipi_dsi_device *device =3D &priv->device; + int ret; + + platdata->max_data_lanes =3D 2; + platdata->phy_ops =3D &dw_mipi_dsi_stm_phy_ops; + + ret =3D uclass_first_device(UCLASS_PANEL, &platdata->panel); + if (ret) { + dev_err(dev, "panel device error %d\n", ret); + return ret; + } + + ret =3D dw_mipi_dsi_init_bridge(device); + if (ret) { + dev_err(dev, "failed to initialize mipi dsi host\n"); + return ret; + } + + return 0; +} + +static int stm32_dsi_set_backlight(struct udevice *dev, int percent) +{ + struct dw_mipi_dsi_plat_data *dplat =3D dev_get_platdata(dev); + struct stm32_dsi_priv *priv =3D dev_get_priv(dev); + struct mipi_dsi_device *device =3D &priv->device; + struct udevice *panel =3D dplat->panel; + struct mipi_dsi_panel_plat *mplat; + int ret; + + mplat =3D dev_get_platdata(panel); + mplat->device =3D device; + + ret =3D panel_enable_backlight(panel); + if (ret) { + dev_err(dev, "panel %s enable backlight error %d\n", + panel->name, ret); + return ret; + } + + dw_mipi_dsi_bridge_enable(device); + + return 0; +} + +static int stm32_dsi_probe(struct udevice *dev) +{ + struct stm32_dsi_priv *priv =3D dev_get_priv(dev); + struct mipi_dsi_device *device =3D &priv->device; + struct reset_ctl rst; + struct clk clk; + int ret; + + device->dev =3D dev; + + priv->base =3D (void *)dev_read_addr(dev); + if ((fdt_addr_t)priv->base =3D=3D FDT_ADDR_T_NONE) { + dev_err(dev, "dsi dt register address error\n"); + return -EINVAL; + } + + ret =3D clk_get_by_name(device->dev, "pclk", &clk); + if (ret) { + dev_err(dev, "peripheral clock get error %d\n", ret); + return -ENODEV; + } + + ret =3D clk_enable(&clk); + if (ret) { + dev_err(dev, "peripheral clock enable error %d\n", ret); + return -ENODEV; + } + + ret =3D clk_get_by_name(dev, "ref", &clk); + if (ret) { + dev_err(dev, "pll reference clock get error %d\n", ret); + return ret; + } + + priv->pllref_clk =3D (unsigned int)clk_get_rate(&clk); + + ret =3D reset_get_by_index(device->dev, 0, &rst); + if (ret) { + dev_err(dev, "missing dsi hardware reset\n"); + return -ENODEV; + } + + /* Reset */ + reset_assert(&rst); + udelay(20); + reset_deassert(&rst); + + return 0; +} + +struct video_bridge_ops stm32_dsi_ops =3D { + .attach =3D stm32_dsi_attach, + .set_backlight =3D stm32_dsi_set_backlight, +}; + +static const struct udevice_id stm32_dsi_ids[] =3D { + { .compatible =3D "st,stm32-dsi"}, + { } +}; + +U_BOOT_DRIVER(stm32_dsi) =3D { + .name =3D "stm32-display-dsi", + .id =3D UCLASS_VIDEO_BRIDGE, + .of_match =3D stm32_dsi_ids, + .bind =3D dm_scan_fdt_dev, + .probe =3D stm32_dsi_probe, + .ops =3D &stm32_dsi_ops, + .priv_auto_alloc_size =3D sizeof(struct stm32_dsi_priv), + .platdata_auto_alloc_size =3D sizeof(struct dw_mipi_dsi_plat_data), +}; --=20 1.9.1