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From: <boyuan.zhang-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Boyuan Zhang <boyuan.zhang-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 2/5] drm/amdgpu: add system interrupt mask for jrbc
Date: Wed, 18 Jul 2018 16:39:12 -0400	[thread overview]
Message-ID: <1531946355-17488-2-git-send-email-boyuan.zhang@amd.com> (raw)
In-Reply-To: <1531946355-17488-1-git-send-email-boyuan.zhang-5C7GfCeVMHo@public.gmane.org>

From: Boyuan Zhang <boyuan.zhang@amd.com>

Add new mask for enabling system interrupt for jrbc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
index d6ba269..124383d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
@@ -982,6 +982,8 @@
 #define UVD_MASTINT_EN__VCPU_EN_MASK                                                                          0x00000002L
 #define UVD_MASTINT_EN__SYS_EN_MASK                                                                           0x00000004L
 #define UVD_MASTINT_EN__INT_OVERRUN_MASK                                                                      0x007FFFF0L
+//UVD_SYS_INT_EN
+#define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK                                                                      0x00000010L
 //JPEG_CGC_CTRL
 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                  0x0
 #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT                                                                      0x1
-- 
2.7.4

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  parent reply	other threads:[~2018-07-18 20:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-18 20:39 [PATCH 1/5] drm/amdgpu: add system interrupt register offset header boyuan.zhang-5C7GfCeVMHo
     [not found] ` <1531946355-17488-1-git-send-email-boyuan.zhang-5C7GfCeVMHo@public.gmane.org>
2018-07-18 20:39   ` boyuan.zhang-5C7GfCeVMHo [this message]
2018-07-18 20:39   ` [PATCH 3/5] drm/amdgpu: enable system interrupt for jrbc boyuan.zhang-5C7GfCeVMHo
     [not found]     ` <1531946355-17488-3-git-send-email-boyuan.zhang-5C7GfCeVMHo@public.gmane.org>
2018-07-19 18:13       ` Leo Liu
     [not found]         ` <7ff97103-bd17-3011-103d-a4e2e77099a6-5C7GfCeVMHo@public.gmane.org>
2018-07-19 18:46           ` Zhang, Boyuan
2018-07-19 18:51       ` Alex Deucher
     [not found]         ` <CADnq5_NFgHpv4Z_2scvRC8y6EYPqUtnsvGXF6g2mD4yEKuQGOw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-07-23 19:53           ` Boyuan Zhang
     [not found]             ` <763a42d3-c83b-2272-ec01-e11a14bdaf43-5C7GfCeVMHo@public.gmane.org>
2018-07-24 12:50               ` Christian König
     [not found]                 ` <720bdbc9-eed9-42de-2547-654713e0d20b-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-07-25 14:01                   ` Boyuan Zhang
     [not found]                     ` <7b6ce506-ec36-6f91-cdef-3e0b21969018-5C7GfCeVMHo@public.gmane.org>
2018-07-25 15:05                       ` Alex Deucher
     [not found]                         ` <CADnq5_NoOnf2211EuaPB4vbgSt92seoJViArJtPmc72W=e7a8Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-08-09 15:52                           ` Boyuan Zhang
2018-07-18 20:39   ` [PATCH 4/5] drm/amdgpu: add emit trap for vcn jpeg boyuan.zhang-5C7GfCeVMHo
2018-07-18 20:39   ` [PATCH 5/5] drm/amdgpu: fix emit frame size and comments for jpeg boyuan.zhang-5C7GfCeVMHo

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