diff for duplicates of <1532338347-4317-1-git-send-email-cl@rock-chips.com> diff --git a/a/1.txt b/N1/1.txt index 2e857f2..7012ec2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -54,7 +54,7 @@ index 0000000..5e15aee + #address-cells = <2>; + #size-cells = <0>; + -+ cpu0: cpu@0 { ++ cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x0>; @@ -66,7 +66,7 @@ index 0000000..5e15aee + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + -+ cpu1: cpu@1 { ++ cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x1>; @@ -74,7 +74,7 @@ index 0000000..5e15aee + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; -+ cpu2: cpu@2 { ++ cpu2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x2>; @@ -82,7 +82,7 @@ index 0000000..5e15aee + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; -+ cpu3: cpu@3 { ++ cpu3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x3>; @@ -206,7 +206,7 @@ index 0000000..5e15aee + clock-output-names = "xin32k"; + }; + -+ pmu: power-management@ff000000 { ++ pmu: power-management at ff000000 { + compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff000000 0x0 0x1000>; + @@ -217,20 +217,20 @@ index 0000000..5e15aee + #size-cells = <0>; + + /* These power domains are grouped by VD_LOGIC */ -+ pd_usb@PX30_PD_USB { ++ pd_usb at PX30_PD_USB { + reg = <PX30_PD_USB>; + clocks = <&cru HCLK_HOST>, + <&cru HCLK_OTG>, + <&cru SCLK_OTG_ADP>; + pm_qos = <&qos_usb_host>, <&qos_usb_otg>; + }; -+ pd_sdcard@PX30_PD_SDCARD { ++ pd_sdcard at PX30_PD_SDCARD { + reg = <PX30_PD_SDCARD>; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sdmmc>; + }; -+ pd_gmac@PX30_PD_GMAC { ++ pd_gmac at PX30_PD_GMAC { + reg = <PX30_PD_GMAC>; + clocks = <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>, @@ -238,7 +238,7 @@ index 0000000..5e15aee + <&cru SCLK_GMAC_RX_TX>; + pm_qos = <&qos_gmac>; + }; -+ pd_mmc_nand@PX30_PD_MMC_NAND { ++ pd_mmc_nand at PX30_PD_MMC_NAND { + reg = <PX30_PD_MMC_NAND>; + clocks = <&cru HCLK_NANDC>, + <&cru HCLK_EMMC>, @@ -251,14 +251,14 @@ index 0000000..5e15aee + pm_qos = <&qos_emmc>, <&qos_nand>, + <&qos_sdio>, <&qos_sfc>; + }; -+ pd_vpu@PX30_PD_VPU { ++ pd_vpu at PX30_PD_VPU { + reg = <PX30_PD_VPU>; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>, + <&cru SCLK_CORE_VPU>; + pm_qos = <&qos_vpu>, <&qos_vpu_r128>; + }; -+ pd_vo@PX30_PD_VO { ++ pd_vo at PX30_PD_VO { + reg = <PX30_PD_VO>; + clocks = <&cru ACLK_RGA>, + <&cru ACLK_VOPB>, @@ -274,7 +274,7 @@ index 0000000..5e15aee + pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, + <&qos_vop_m0>, <&qos_vop_m1>; + }; -+ pd_vi@PX30_PD_VI { ++ pd_vi at PX30_PD_VI { + reg = <PX30_PD_VI>; + clocks = <&cru ACLK_CIF>, + <&cru ACLK_ISP>, @@ -285,7 +285,7 @@ index 0000000..5e15aee + <&qos_isp_wr>, <&qos_isp_m1>, + <&qos_vip>; + }; -+ pd_gpu@PX30_PD_GPU { ++ pd_gpu at PX30_PD_GPU { + reg = <PX30_PD_GPU>; + clocks = <&cru SCLK_GPU>; + pm_qos = <&qos_gpu>; @@ -293,7 +293,7 @@ index 0000000..5e15aee + }; + }; + -+ pmugrf: syscon@ff010000 { ++ pmugrf: syscon at ff010000 { + compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xff010000 0x0 0x1000>; + #address-cells = <1>; @@ -315,7 +315,7 @@ index 0000000..5e15aee + }; + }; + -+ uart0: serial@ff030000 { ++ uart0: serial at ff030000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff030000 0x0 0x100>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -330,7 +330,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ i2s1_2ch: i2s@ff070000 { ++ i2s1_2ch: i2s at ff070000 { + compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff070000 0x0 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; @@ -346,7 +346,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ i2s2_2ch: i2s@ff080000 { ++ i2s2_2ch: i2s at ff080000 { + compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff080000 0x0 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -362,7 +362,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ gic: interrupt-controller@ff131000 { ++ gic: interrupt-controller at ff131000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; @@ -375,7 +375,7 @@ index 0000000..5e15aee + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + -+ grf: syscon@ff140000 { ++ grf: syscon at ff140000 { + compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff140000 0x0 0x1000>; + #address-cells = <1>; @@ -387,7 +387,7 @@ index 0000000..5e15aee + }; + }; + -+ uart1: serial@ff158000 { ++ uart1: serial at ff158000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff158000 0x0 0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; @@ -402,7 +402,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ uart2: serial@ff160000 { ++ uart2: serial at ff160000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff160000 0x0 0x100>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; @@ -417,7 +417,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ uart3: serial@ff168000 { ++ uart3: serial at ff168000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff168000 0x0 0x100>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; @@ -432,7 +432,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ uart4: serial@ff170000 { ++ uart4: serial at ff170000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff170000 0x0 0x100>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -447,7 +447,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ uart5: serial@ff178000 { ++ uart5: serial at ff178000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff178000 0x0 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -462,7 +462,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ i2c0: i2c@ff180000 { ++ i2c0: i2c at ff180000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff180000 0x0 0x1000>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; @@ -475,7 +475,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ i2c1: i2c@ff190000 { ++ i2c1: i2c at ff190000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff190000 0x0 0x1000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; @@ -488,7 +488,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ i2c2: i2c@ff1a0000 { ++ i2c2: i2c at ff1a0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff1a0000 0x0 0x1000>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; @@ -501,7 +501,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ i2c3: i2c@ff1b0000 { ++ i2c3: i2c at ff1b0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff1b0000 0x0 0x1000>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; @@ -514,7 +514,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ spi0: spi@ff1d0000 { ++ spi0: spi at ff1d0000 { + compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1d0000 0x0 0x1000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; @@ -531,7 +531,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ spi1: spi@ff1d8000 { ++ spi1: spi at ff1d8000 { + compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1d8000 0x0 0x1000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; @@ -548,7 +548,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ wdt: watchdog@ff1e0000 { ++ wdt: watchdog at ff1e0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff1e0000 0x0 0x100>; + clocks = <&cru PCLK_WDT_NS>; @@ -556,7 +556,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm0: pwm@ff200000 { ++ pwm0: pwm at ff200000 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200000 0x0 0x10>; + #pwm-cells = <3>; @@ -567,7 +567,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm1: pwm@ff200010 { ++ pwm1: pwm at ff200010 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200010 0x0 0x10>; + #pwm-cells = <3>; @@ -578,7 +578,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm2: pwm@ff200020 { ++ pwm2: pwm at ff200020 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200020 0x0 0x10>; + #pwm-cells = <3>; @@ -589,7 +589,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm3: pwm@ff200030 { ++ pwm3: pwm at ff200030 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200030 0x0 0x10>; + #pwm-cells = <3>; @@ -600,7 +600,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm4: pwm@ff208000 { ++ pwm4: pwm at ff208000 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208000 0x0 0x10>; + #pwm-cells = <3>; @@ -611,7 +611,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm5: pwm@ff208010 { ++ pwm5: pwm at ff208010 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208010 0x0 0x10>; + #pwm-cells = <3>; @@ -622,7 +622,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm6: pwm@ff208020 { ++ pwm6: pwm at ff208020 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208020 0x0 0x10>; + #pwm-cells = <3>; @@ -633,7 +633,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ pwm7: pwm@ff208030 { ++ pwm7: pwm at ff208030 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208030 0x0 0x10>; + #pwm-cells = <3>; @@ -644,7 +644,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ rktimer: rktimer@ff210000 { ++ rktimer: rktimer at ff210000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x0 0xff210000 0x0 0x1000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; @@ -658,7 +658,7 @@ index 0000000..5e15aee + #size-cells = <2>; + ranges; + -+ dmac: dmac@ff240000 { ++ dmac: dmac at ff240000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff240000 0x0 0x4000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, @@ -670,7 +670,7 @@ index 0000000..5e15aee + }; + }; + -+ saradc: saradc@ff288000 { ++ saradc: saradc at ff288000 { + compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff288000 0x0 0x100>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -682,7 +682,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ cru: clock-controller@ff2b0000 { ++ cru: clock-controller at ff2b0000 { + compatible = "rockchip,px30-cru"; + reg = <0x0 0xff2b0000 0x0 0x1000>; + rockchip,grf = <&grf>; @@ -693,7 +693,7 @@ index 0000000..5e15aee + assigned-clock-rates = <1188000000>; + }; + -+ pmucru: clock-controller@ff2bc000 { ++ pmucru: clock-controller at ff2bc000 { + compatible = "rockchip,px30-pmucru"; + reg = <0x0 0xff2bc000 0x0 0x1000>; + rockchip,grf = <&grf>; @@ -714,7 +714,7 @@ index 0000000..5e15aee + <100000000>, <200000000>; + }; + -+ usb20_otg: usb@ff300000 { ++ usb20_otg: usb at ff300000 { + compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff300000 0x0 0x40000>; @@ -731,7 +731,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ usb_host0_ehci: usb@ff340000 { ++ usb_host0_ehci: usb at ff340000 { + compatible = "generic-ehci"; + reg = <0x0 0xff340000 0x0 0x10000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -742,7 +742,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ usb_host0_ohci: usb@ff350000 { ++ usb_host0_ohci: usb at ff350000 { + compatible = "generic-ohci"; + reg = <0x0 0xff350000 0x0 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; @@ -753,7 +753,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ gmac: ethernet@ff360000 { ++ gmac: ethernet at ff360000 { + compatible = "rockchip,px30-gmac"; + reg = <0x0 0xff360000 0x0 0x10000>; + rockchip,grf = <&grf>; @@ -776,7 +776,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ sdmmc: dwmmc@ff370000 { ++ sdmmc: dwmmc at ff370000 { + compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff370000 0x0 0x4000>; + max-frequency = <150000000>; @@ -791,7 +791,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ sdio: dwmmc@ff380000 { ++ sdio: dwmmc at ff380000 { + compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff380000 0x0 0x4000>; + max-frequency = <150000000>; @@ -806,7 +806,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ emmc: dwmmc@ff390000 { ++ emmc: dwmmc at ff390000 { + compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff390000 0x0 0x4000>; + max-frequency = <150000000>; @@ -819,7 +819,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ vopb: vop@ff460000 { ++ vopb: vop at ff460000 { + compatible = "rockchip,px30-vop-big"; + reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; + rockchip,grf = <&grf>; @@ -833,7 +833,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ vopb_mmu: iommu@ff460f00 { ++ vopb_mmu: iommu at ff460f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff460f00 0x0 0x100>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -845,7 +845,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ vopl: vop@ff470000 { ++ vopl: vop at ff470000 { + compatible = "rockchip,px30-vop-lit"; + reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; + rockchip,grf = <&grf>; @@ -859,7 +859,7 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ vopl_mmu: iommu@ff470f00 { ++ vopl_mmu: iommu at ff470f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff470f00 0x0 0x100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; @@ -871,102 +871,102 @@ index 0000000..5e15aee + status = "disabled"; + }; + -+ qos_gmac: qos@ff518000 { ++ qos_gmac: qos at ff518000 { + compatible = "syscon"; + reg = <0x0 0xff518000 0x0 0x20>; + }; + -+ qos_gpu: qos@ff520000 { ++ qos_gpu: qos at ff520000 { + compatible = "syscon"; + reg = <0x0 0xff520000 0x0 0x20>; + }; + -+ qos_sdmmc: qos@ff52c000 { ++ qos_sdmmc: qos at ff52c000 { + compatible = "syscon"; + reg = <0x0 0xff52c000 0x0 0x20>; + }; + -+ qos_emmc: qos@ff538000 { ++ qos_emmc: qos at ff538000 { + compatible = "syscon"; + reg = <0x0 0xff538000 0x0 0x20>; + }; + -+ qos_nand: qos@ff538080 { ++ qos_nand: qos at ff538080 { + compatible = "syscon"; + reg = <0x0 0xff538080 0x0 0x20>; + }; + -+ qos_sdio: qos@ff538100 { ++ qos_sdio: qos at ff538100 { + compatible = "syscon"; + reg = <0x0 0xff538100 0x0 0x20>; + }; + -+ qos_sfc: qos@ff538180 { ++ qos_sfc: qos at ff538180 { + compatible = "syscon"; + reg = <0x0 0xff538180 0x0 0x20>; + }; + -+ qos_usb_host: qos@ff540000 { ++ qos_usb_host: qos at ff540000 { + compatible = "syscon"; + reg = <0x0 0xff540000 0x0 0x20>; + }; + -+ qos_usb_otg: qos@ff540080 { ++ qos_usb_otg: qos at ff540080 { + compatible = "syscon"; + reg = <0x0 0xff540080 0x0 0x20>; + }; + -+ qos_isp_128: qos@ff548000 { ++ qos_isp_128: qos at ff548000 { + compatible = "syscon"; + reg = <0x0 0xff548000 0x0 0x20>; + }; + -+ qos_isp_rd: qos@ff548080 { ++ qos_isp_rd: qos at ff548080 { + compatible = "syscon"; + reg = <0x0 0xff548080 0x0 0x20>; + }; + -+ qos_isp_wr: qos@ff548100 { ++ qos_isp_wr: qos at ff548100 { + compatible = "syscon"; + reg = <0x0 0xff548100 0x0 0x20>; + }; + -+ qos_isp_m1: qos@ff548180 { ++ qos_isp_m1: qos at ff548180 { + compatible = "syscon"; + reg = <0x0 0xff548180 0x0 0x20>; + }; + -+ qos_vip: qos@ff548200 { ++ qos_vip: qos at ff548200 { + compatible = "syscon"; + reg = <0x0 0xff548200 0x0 0x20>; + }; + -+ qos_rga_rd: qos@ff550000 { ++ qos_rga_rd: qos at ff550000 { + compatible = "syscon"; + reg = <0x0 0xff550000 0x0 0x20>; + }; + -+ qos_rga_wr: qos@ff550080 { ++ qos_rga_wr: qos at ff550080 { + compatible = "syscon"; + reg = <0x0 0xff550080 0x0 0x20>; + }; + -+ qos_vop_m0: qos@ff550100 { ++ qos_vop_m0: qos at ff550100 { + compatible = "syscon"; + reg = <0x0 0xff550100 0x0 0x20>; + }; + -+ qos_vop_m1: qos@ff550180 { ++ qos_vop_m1: qos at ff550180 { + compatible = "syscon"; + reg = <0x0 0xff550180 0x0 0x20>; + }; + -+ qos_vpu: qos@ff558000 { ++ qos_vpu: qos at ff558000 { + compatible = "syscon"; + reg = <0x0 0xff558000 0x0 0x20>; + }; + -+ qos_vpu_r128: qos@ff558080 { ++ qos_vpu_r128: qos at ff558080 { + compatible = "syscon"; + reg = <0x0 0xff558080 0x0 0x20>; + }; @@ -979,7 +979,7 @@ index 0000000..5e15aee + #size-cells = <2>; + ranges; + -+ gpio0: gpio0@ff040000 { ++ gpio0: gpio0 at ff040000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff040000 0x0 0x100>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -991,7 +991,7 @@ index 0000000..5e15aee + #interrupt-cells = <2>; + }; + -+ gpio1: gpio1@ff250000 { ++ gpio1: gpio1 at ff250000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff250000 0x0 0x100>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -1003,7 +1003,7 @@ index 0000000..5e15aee + #interrupt-cells = <2>; + }; + -+ gpio2: gpio2@ff260000 { ++ gpio2: gpio2 at ff260000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -1015,7 +1015,7 @@ index 0000000..5e15aee + #interrupt-cells = <2>; + }; + -+ gpio3: gpio3@ff270000 { ++ gpio3: gpio3 at ff270000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff270000 0x0 0x100>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index d4fe774..d945852 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,38 +1,8 @@ "ref\01532337924-4185-1-git-send-email-cl@rock-chips.com\0" - "From\0<cl@rock-chips.com>\0" + "From\0cl@rock-chips.com (cl at rock-chips.com)\0" "Subject\0[PATCH v2 5/6] arm64: dts: rockchip: add core dtsi file for PX30 SoCs\0" "Date\0Mon, 23 Jul 2018 17:32:27 +0800\0" - "To\0heiko@sntech.de\0" - "Cc\0robh+dt@kernel.org" - mark.rutland@arm.com - klaus.goger@theobroma-systems.com - hjc@rock-chips.com - jagan@amarulasolutions.com - djw@t-chip.com.cn - jacob-chen@iotwrt.com - devicetree@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-rockchip@lists.infradead.org - linux-kernel@vger.kernel.org - ulf.hansson@linaro.org - linux-mmc@vger.kernel.org - frank.wang@rock-chips.com - lgirdwood@gmail.com - broonie@kernel.org - alsa-devel@alsa-project.org - gregkh@linuxfoundation.org - catalin.marinas@arm.com - will.deacon@arm.com - yamada.masahiro@socionext.com - arnd@arndb.de - zhangqing@rock-chips.com - shawn.lin@rock-chips.com - kever.yang@rock-chips.com - david.wu@rock-chips.com - huangtao@rock-chips.com - tony.xie@rock-chips.com - sugar.zhang@rock-chips.com - " huibin.hong@rock-chips.com\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "From: Liang Chen <cl@rock-chips.com>\n" @@ -91,7 +61,7 @@ "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu0: cpu@0 {\n" + "+\t\tcpu0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a35\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x0>;\n" @@ -103,7 +73,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu1: cpu@1 {\n" + "+\t\tcpu1: cpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a35\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x1>;\n" @@ -111,7 +81,7 @@ "+\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n" "+\t\t\tcpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;\n" "+\t\t};\n" - "+\t\tcpu2: cpu@2 {\n" + "+\t\tcpu2: cpu at 2 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a35\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x2>;\n" @@ -119,7 +89,7 @@ "+\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n" "+\t\t\tcpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;\n" "+\t\t};\n" - "+\t\tcpu3: cpu@3 {\n" + "+\t\tcpu3: cpu at 3 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a35\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x3>;\n" @@ -243,7 +213,7 @@ "+\t\tclock-output-names = \"xin32k\";\n" "+\t};\n" "+\n" - "+\tpmu: power-management@ff000000 {\n" + "+\tpmu: power-management at ff000000 {\n" "+\t\tcompatible = \"rockchip,px30-pmu\", \"syscon\", \"simple-mfd\";\n" "+\t\treg = <0x0 0xff000000 0x0 0x1000>;\n" "+\n" @@ -254,20 +224,20 @@ "+\t\t\t#size-cells = <0>;\n" "+\n" "+\t\t\t/* These power domains are grouped by VD_LOGIC */\n" - "+\t\t\tpd_usb@PX30_PD_USB {\n" + "+\t\t\tpd_usb at PX30_PD_USB {\n" "+\t\t\t\treg = <PX30_PD_USB>;\n" "+\t\t\t\tclocks = <&cru HCLK_HOST>,\n" "+\t\t\t\t\t <&cru HCLK_OTG>,\n" "+\t\t\t\t\t <&cru SCLK_OTG_ADP>;\n" "+\t\t\t\tpm_qos = <&qos_usb_host>, <&qos_usb_otg>;\n" "+\t\t\t};\n" - "+\t\t\tpd_sdcard@PX30_PD_SDCARD {\n" + "+\t\t\tpd_sdcard at PX30_PD_SDCARD {\n" "+\t\t\t\treg = <PX30_PD_SDCARD>;\n" "+\t\t\t\tclocks = <&cru HCLK_SDMMC>,\n" "+\t\t\t\t\t <&cru SCLK_SDMMC>;\n" "+\t\t\t\tpm_qos = <&qos_sdmmc>;\n" "+\t\t\t};\n" - "+\t\t\tpd_gmac@PX30_PD_GMAC {\n" + "+\t\t\tpd_gmac at PX30_PD_GMAC {\n" "+\t\t\t\treg = <PX30_PD_GMAC>;\n" "+\t\t\t\tclocks = <&cru ACLK_GMAC>,\n" "+\t\t\t\t\t <&cru PCLK_GMAC>,\n" @@ -275,7 +245,7 @@ "+\t\t\t\t\t <&cru SCLK_GMAC_RX_TX>;\n" "+\t\t\t\tpm_qos = <&qos_gmac>;\n" "+\t\t\t};\n" - "+\t\t\tpd_mmc_nand@PX30_PD_MMC_NAND {\n" + "+\t\t\tpd_mmc_nand at PX30_PD_MMC_NAND {\n" "+\t\t\t\treg = <PX30_PD_MMC_NAND>;\n" "+\t\t\t\tclocks = <&cru HCLK_NANDC>,\n" "+\t\t\t\t\t <&cru HCLK_EMMC>,\n" @@ -288,14 +258,14 @@ "+\t\t\t\tpm_qos = <&qos_emmc>, <&qos_nand>,\n" "+\t\t\t\t\t <&qos_sdio>, <&qos_sfc>;\n" "+\t\t\t};\n" - "+\t\t\tpd_vpu@PX30_PD_VPU {\n" + "+\t\t\tpd_vpu at PX30_PD_VPU {\n" "+\t\t\t\treg = <PX30_PD_VPU>;\n" "+\t\t\t\tclocks = <&cru ACLK_VPU>,\n" "+\t\t\t\t\t <&cru HCLK_VPU>,\n" "+\t\t\t\t\t <&cru SCLK_CORE_VPU>;\n" "+\t\t\t\tpm_qos = <&qos_vpu>, <&qos_vpu_r128>;\n" "+\t\t\t};\n" - "+\t\t\tpd_vo@PX30_PD_VO {\n" + "+\t\t\tpd_vo at PX30_PD_VO {\n" "+\t\t\t\treg = <PX30_PD_VO>;\n" "+\t\t\t\tclocks = <&cru ACLK_RGA>,\n" "+\t\t\t\t\t <&cru ACLK_VOPB>,\n" @@ -311,7 +281,7 @@ "+\t\t\t\tpm_qos = <&qos_rga_rd>, <&qos_rga_wr>,\n" "+\t\t\t\t\t <&qos_vop_m0>, <&qos_vop_m1>;\n" "+\t\t\t};\n" - "+\t\t\tpd_vi@PX30_PD_VI {\n" + "+\t\t\tpd_vi at PX30_PD_VI {\n" "+\t\t\t\treg = <PX30_PD_VI>;\n" "+\t\t\t\tclocks = <&cru ACLK_CIF>,\n" "+\t\t\t\t\t <&cru ACLK_ISP>,\n" @@ -322,7 +292,7 @@ "+\t\t\t\t\t <&qos_isp_wr>, <&qos_isp_m1>,\n" "+\t\t\t\t\t <&qos_vip>;\n" "+\t\t\t};\n" - "+\t\t\tpd_gpu@PX30_PD_GPU {\n" + "+\t\t\tpd_gpu at PX30_PD_GPU {\n" "+\t\t\t\treg = <PX30_PD_GPU>;\n" "+\t\t\t\tclocks = <&cru SCLK_GPU>;\n" "+\t\t\t\tpm_qos = <&qos_gpu>;\n" @@ -330,7 +300,7 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tpmugrf: syscon@ff010000 {\n" + "+\tpmugrf: syscon at ff010000 {\n" "+\t\tcompatible = \"rockchip,px30-pmugrf\", \"syscon\", \"simple-mfd\";\n" "+\t\treg = <0x0 0xff010000 0x0 0x1000>;\n" "+\t\t#address-cells = <1>;\n" @@ -352,7 +322,7 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tuart0: serial@ff030000 {\n" + "+\tuart0: serial at ff030000 {\n" "+\t\tcompatible = \"rockchip,px30-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff030000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -367,7 +337,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2s1_2ch: i2s@ff070000 {\n" + "+\ti2s1_2ch: i2s at ff070000 {\n" "+\t\tcompatible = \"rockchip,px30-i2s\", \"rockchip,rk3066-i2s\";\n" "+\t\treg = <0x0 0xff070000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -383,7 +353,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2s2_2ch: i2s@ff080000 {\n" + "+\ti2s2_2ch: i2s at ff080000 {\n" "+\t\tcompatible = \"rockchip,px30-i2s\", \"rockchip,rk3066-i2s\";\n" "+\t\treg = <0x0 0xff080000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -399,7 +369,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tgic: interrupt-controller@ff131000 {\n" + "+\tgic: interrupt-controller at ff131000 {\n" "+\t\tcompatible = \"arm,gic-400\";\n" "+\t\t#interrupt-cells = <3>;\n" "+\t\t#address-cells = <0>;\n" @@ -412,7 +382,7 @@ "+\t\t (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "+\t};\n" "+\n" - "+\tgrf: syscon@ff140000 {\n" + "+\tgrf: syscon at ff140000 {\n" "+\t\tcompatible = \"rockchip,px30-grf\", \"syscon\", \"simple-mfd\";\n" "+\t\treg = <0x0 0xff140000 0x0 0x1000>;\n" "+\t\t#address-cells = <1>;\n" @@ -424,7 +394,7 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tuart1: serial@ff158000 {\n" + "+\tuart1: serial at ff158000 {\n" "+\t\tcompatible = \"rockchip,px30-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff158000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -439,7 +409,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart2: serial@ff160000 {\n" + "+\tuart2: serial at ff160000 {\n" "+\t\tcompatible = \"rockchip,px30-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff160000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -454,7 +424,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart3: serial@ff168000 {\n" + "+\tuart3: serial at ff168000 {\n" "+\t\tcompatible = \"rockchip,px30-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff168000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -469,7 +439,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart4: serial@ff170000 {\n" + "+\tuart4: serial at ff170000 {\n" "+\t\tcompatible = \"rockchip,px30-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff170000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -484,7 +454,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart5: serial@ff178000 {\n" + "+\tuart5: serial at ff178000 {\n" "+\t\tcompatible = \"rockchip,px30-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff178000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -499,7 +469,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c0: i2c@ff180000 {\n" + "+\ti2c0: i2c at ff180000 {\n" "+\t\tcompatible = \"rockchip,rk3399-i2c\";\n" "+\t\treg = <0x0 0xff180000 0x0 0x1000>;\n" "+\t\tclocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;\n" @@ -512,7 +482,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c1: i2c@ff190000 {\n" + "+\ti2c1: i2c at ff190000 {\n" "+\t\tcompatible = \"rockchip,rk3399-i2c\";\n" "+\t\treg = <0x0 0xff190000 0x0 0x1000>;\n" "+\t\tclocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;\n" @@ -525,7 +495,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c2: i2c@ff1a0000 {\n" + "+\ti2c2: i2c at ff1a0000 {\n" "+\t\tcompatible = \"rockchip,rk3399-i2c\";\n" "+\t\treg = <0x0 0xff1a0000 0x0 0x1000>;\n" "+\t\tclocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;\n" @@ -538,7 +508,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c3: i2c@ff1b0000 {\n" + "+\ti2c3: i2c at ff1b0000 {\n" "+\t\tcompatible = \"rockchip,rk3399-i2c\";\n" "+\t\treg = <0x0 0xff1b0000 0x0 0x1000>;\n" "+\t\tclocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;\n" @@ -551,7 +521,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tspi0: spi@ff1d0000 {\n" + "+\tspi0: spi at ff1d0000 {\n" "+\t\tcompatible = \"rockchip,px30-spi\", \"rockchip,rk3066-spi\";\n" "+\t\treg = <0x0 0xff1d0000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -568,7 +538,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tspi1: spi@ff1d8000 {\n" + "+\tspi1: spi at ff1d8000 {\n" "+\t\tcompatible = \"rockchip,px30-spi\", \"rockchip,rk3066-spi\";\n" "+\t\treg = <0x0 0xff1d8000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -585,7 +555,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\twdt: watchdog@ff1e0000 {\n" + "+\twdt: watchdog at ff1e0000 {\n" "+\t\tcompatible = \"snps,dw-wdt\";\n" "+\t\treg = <0x0 0xff1e0000 0x0 0x100>;\n" "+\t\tclocks = <&cru PCLK_WDT_NS>;\n" @@ -593,7 +563,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm0: pwm@ff200000 {\n" + "+\tpwm0: pwm at ff200000 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff200000 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -604,7 +574,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm1: pwm@ff200010 {\n" + "+\tpwm1: pwm at ff200010 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff200010 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -615,7 +585,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm2: pwm@ff200020 {\n" + "+\tpwm2: pwm at ff200020 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff200020 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -626,7 +596,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm3: pwm@ff200030 {\n" + "+\tpwm3: pwm at ff200030 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff200030 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -637,7 +607,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm4: pwm@ff208000 {\n" + "+\tpwm4: pwm at ff208000 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff208000 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -648,7 +618,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm5: pwm@ff208010 {\n" + "+\tpwm5: pwm at ff208010 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff208010 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -659,7 +629,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm6: pwm@ff208020 {\n" + "+\tpwm6: pwm at ff208020 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff208020 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -670,7 +640,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpwm7: pwm@ff208030 {\n" + "+\tpwm7: pwm at ff208030 {\n" "+\t\tcompatible = \"rockchip,px30-pwm\", \"rockchip,rk3328-pwm\";\n" "+\t\treg = <0x0 0xff208030 0x0 0x10>;\n" "+\t\t#pwm-cells = <3>;\n" @@ -681,7 +651,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\trktimer: rktimer@ff210000 {\n" + "+\trktimer: rktimer at ff210000 {\n" "+\t\tcompatible = \"rockchip,rk3288-timer\";\n" "+\t\treg = <0x0 0xff210000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -695,7 +665,7 @@ "+\t\t#size-cells = <2>;\n" "+\t\tranges;\n" "+\n" - "+\t\tdmac: dmac@ff240000 {\n" + "+\t\tdmac: dmac at ff240000 {\n" "+\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n" "+\t\t\treg = <0x0 0xff240000 0x0 0x4000>;\n" "+\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -707,7 +677,7 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tsaradc: saradc@ff288000 {\n" + "+\tsaradc: saradc at ff288000 {\n" "+\t\tcompatible = \"rockchip,px30-saradc\", \"rockchip,rk3399-saradc\";\n" "+\t\treg = <0x0 0xff288000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -719,7 +689,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tcru: clock-controller@ff2b0000 {\n" + "+\tcru: clock-controller at ff2b0000 {\n" "+\t\tcompatible = \"rockchip,px30-cru\";\n" "+\t\treg = <0x0 0xff2b0000 0x0 0x1000>;\n" "+\t\trockchip,grf = <&grf>;\n" @@ -730,7 +700,7 @@ "+\t\tassigned-clock-rates = <1188000000>;\n" "+\t};\n" "+\n" - "+\tpmucru: clock-controller@ff2bc000 {\n" + "+\tpmucru: clock-controller at ff2bc000 {\n" "+\t\tcompatible = \"rockchip,px30-pmucru\";\n" "+\t\treg = <0x0 0xff2bc000 0x0 0x1000>;\n" "+\t\trockchip,grf = <&grf>;\n" @@ -751,7 +721,7 @@ "+\t\t\t<100000000>, <200000000>;\n" "+\t};\n" "+\n" - "+\tusb20_otg: usb@ff300000 {\n" + "+\tusb20_otg: usb at ff300000 {\n" "+\t\tcompatible = \"rockchip,px30-usb\", \"rockchip,rk3066-usb\",\n" "+\t\t\t \"snps,dwc2\";\n" "+\t\treg = <0x0 0xff300000 0x0 0x40000>;\n" @@ -768,7 +738,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tusb_host0_ehci: usb@ff340000 {\n" + "+\tusb_host0_ehci: usb at ff340000 {\n" "+\t\tcompatible = \"generic-ehci\";\n" "+\t\treg = <0x0 0xff340000 0x0 0x10000>;\n" "+\t\tinterrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -779,7 +749,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tusb_host0_ohci: usb@ff350000 {\n" + "+\tusb_host0_ohci: usb at ff350000 {\n" "+\t\tcompatible = \"generic-ohci\";\n" "+\t\treg = <0x0 0xff350000 0x0 0x10000>;\n" "+\t\tinterrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -790,7 +760,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tgmac: ethernet@ff360000 {\n" + "+\tgmac: ethernet at ff360000 {\n" "+\t\tcompatible = \"rockchip,px30-gmac\";\n" "+\t\treg = <0x0 0xff360000 0x0 0x10000>;\n" "+\t\trockchip,grf = <&grf>;\n" @@ -813,7 +783,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tsdmmc: dwmmc@ff370000 {\n" + "+\tsdmmc: dwmmc at ff370000 {\n" "+\t\tcompatible = \"rockchip,px30-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "+\t\treg = <0x0 0xff370000 0x0 0x4000>;\n" "+\t\tmax-frequency = <150000000>;\n" @@ -828,7 +798,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tsdio: dwmmc@ff380000 {\n" + "+\tsdio: dwmmc at ff380000 {\n" "+\t\tcompatible = \"rockchip,px30-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "+\t\treg = <0x0 0xff380000 0x0 0x4000>;\n" "+\t\tmax-frequency = <150000000>;\n" @@ -843,7 +813,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\temmc: dwmmc@ff390000 {\n" + "+\temmc: dwmmc at ff390000 {\n" "+\t\tcompatible = \"rockchip,px30-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "+\t\treg = <0x0 0xff390000 0x0 0x4000>;\n" "+\t\tmax-frequency = <150000000>;\n" @@ -856,7 +826,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tvopb: vop@ff460000 {\n" + "+\tvopb: vop at ff460000 {\n" "+\t\tcompatible = \"rockchip,px30-vop-big\";\n" "+\t\treg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>;\n" "+\t\trockchip,grf = <&grf>;\n" @@ -870,7 +840,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tvopb_mmu: iommu@ff460f00 {\n" + "+\tvopb_mmu: iommu at ff460f00 {\n" "+\t\tcompatible = \"rockchip,iommu\";\n" "+\t\treg = <0x0 0xff460f00 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -882,7 +852,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tvopl: vop@ff470000 {\n" + "+\tvopl: vop at ff470000 {\n" "+\t\tcompatible = \"rockchip,px30-vop-lit\";\n" "+\t\treg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>;\n" "+\t\trockchip,grf = <&grf>;\n" @@ -896,7 +866,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tvopl_mmu: iommu@ff470f00 {\n" + "+\tvopl_mmu: iommu at ff470f00 {\n" "+\t\tcompatible = \"rockchip,iommu\";\n" "+\t\treg = <0x0 0xff470f00 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -908,102 +878,102 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tqos_gmac: qos@ff518000 {\n" + "+\tqos_gmac: qos at ff518000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff518000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_gpu: qos@ff520000 {\n" + "+\tqos_gpu: qos at ff520000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff520000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_sdmmc: qos@ff52c000 {\n" + "+\tqos_sdmmc: qos at ff52c000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff52c000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_emmc: qos@ff538000 {\n" + "+\tqos_emmc: qos at ff538000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff538000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_nand: qos@ff538080 {\n" + "+\tqos_nand: qos at ff538080 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff538080 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_sdio: qos@ff538100 {\n" + "+\tqos_sdio: qos at ff538100 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff538100 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_sfc: qos@ff538180 {\n" + "+\tqos_sfc: qos at ff538180 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff538180 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_usb_host: qos@ff540000 {\n" + "+\tqos_usb_host: qos at ff540000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff540000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_usb_otg: qos@ff540080 {\n" + "+\tqos_usb_otg: qos at ff540080 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff540080 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_isp_128: qos@ff548000 {\n" + "+\tqos_isp_128: qos at ff548000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff548000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_isp_rd: qos@ff548080 {\n" + "+\tqos_isp_rd: qos at ff548080 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff548080 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_isp_wr: qos@ff548100 {\n" + "+\tqos_isp_wr: qos at ff548100 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff548100 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_isp_m1: qos@ff548180 {\n" + "+\tqos_isp_m1: qos at ff548180 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff548180 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_vip: qos@ff548200 {\n" + "+\tqos_vip: qos at ff548200 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff548200 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_rga_rd: qos@ff550000 {\n" + "+\tqos_rga_rd: qos at ff550000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff550000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_rga_wr: qos@ff550080 {\n" + "+\tqos_rga_wr: qos at ff550080 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff550080 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_vop_m0: qos@ff550100 {\n" + "+\tqos_vop_m0: qos at ff550100 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff550100 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_vop_m1: qos@ff550180 {\n" + "+\tqos_vop_m1: qos at ff550180 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff550180 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_vpu: qos@ff558000 {\n" + "+\tqos_vpu: qos at ff558000 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff558000 0x0 0x20>;\n" "+\t};\n" "+\n" - "+\tqos_vpu_r128: qos@ff558080 {\n" + "+\tqos_vpu_r128: qos at ff558080 {\n" "+\t\tcompatible = \"syscon\";\n" "+\t\treg = <0x0 0xff558080 0x0 0x20>;\n" "+\t};\n" @@ -1016,7 +986,7 @@ "+\t\t#size-cells = <2>;\n" "+\t\tranges;\n" "+\n" - "+\t\tgpio0: gpio0@ff040000 {\n" + "+\t\tgpio0: gpio0 at ff040000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff040000 0x0 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1028,7 +998,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio1: gpio1@ff250000 {\n" + "+\t\tgpio1: gpio1 at ff250000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff250000 0x0 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1040,7 +1010,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio2: gpio2@ff260000 {\n" + "+\t\tgpio2: gpio2 at ff260000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff260000 0x0 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1052,7 +1022,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio3: gpio3@ff270000 {\n" + "+\t\tgpio3: gpio3 at ff270000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff270000 0x0 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -2097,4 +2067,4 @@ "-- \n" 1.9.1 -1007097b06ea844e01360f8eb646d6537d2b60ca993a9c5490624a2b475c0b72 +f344cd2d3f46938591976e731e1b996152d480e3c8f2a80f97c1821947e77253
diff --git a/a/content_digest b/N2/content_digest index d4fe774..5f29c69 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -32,7 +32,10 @@ huangtao@rock-chips.com tony.xie@rock-chips.com sugar.zhang@rock-chips.com - " huibin.hong@rock-chips.com\0" + huibin.hong@rock-chips.com + william.wu@rock-chips.com + sandy.huang@rock-chips.com + " Liang Chen <cl@rock-chips.com>\0" "\00:1\0" "b\0" "From: Liang Chen <cl@rock-chips.com>\n" @@ -2097,4 +2100,4 @@ "-- \n" 1.9.1 -1007097b06ea844e01360f8eb646d6537d2b60ca993a9c5490624a2b475c0b72 +0bb8a35c87331db505585e2dc5e2229a1048619e945e137c91e0d0b80eb39bef
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