diff for duplicates of <1532461998.20066.5.camel@gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index 219b3d0..13381d0 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,148 +1,87 @@
-Hi Alex,
-
-On Tue, 2018-07-24@10:14 -0600, Alex Williamson wrote:
-> The Samsung SM961/PM961 (960 EVO) sometimes fails to return from FLR
-> with the PCI config space reading back as -1.??A reproducible instance
-> of this behavior is resolved by clearing the enable bit in the NVMe
-> configuration register and waiting for the ready status to clear
-> (disabling the NVMe controller) prior to FLR.
-> 
-> Signed-off-by: Alex Williamson <alex.williamson at redhat.com>
-> ---
-> ?drivers/pci/quirks.c |???83
-> ++++++++++++++++++++++++++++++++++++++++++++++++++
-> ?1 file changed, 83 insertions(+)
-> 
-> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-> index e72c8742aafa..3899cdd2514b 100644
-> --- a/drivers/pci/quirks.c
-> +++ b/drivers/pci/quirks.c
-> @@ -28,6 +28,7 @@
-> ?#include <linux/platform_data/x86/apple.h>
-> ?#include <linux/pm_runtime.h>
-> ?#include <linux/switchtec.h>
-> +#include <linux/nvme.h>
-> ?#include <asm/dma.h>	/* isa_dma_bridge_buggy */
-> ?#include "pci.h"
-> ?
-> @@ -3669,6 +3670,87 @@ static int reset_chelsio_generic_dev(struct pci_dev
-> *dev, int probe)
-> ?#define PCI_DEVICE_ID_INTEL_IVB_M_VGA??????0x0156
-> ?#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA?????0x0166
-> ?
-> +/*
-> + * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
-> + * FLR where config space reads from the device return -1.??We seem to be
-> + * able to avoid this condition if we disable the NVMe controller prior to
-> + * FLR.??This quirk is generic for any NVMe class device requiring similar
-> + * assistance to quiesce the device prior to FLR.
-> + *
-> + * NVMe specification: https://nvmexpress.org/resources/specifications/
-> + * Revision 1.0e:
-
-It seems too old version of NVMe specification. ?Do you have any special reason
-to comment the specified 1.0 version instead of 1.3 or something newer?
-
-> + *????Chapter 2: Required and optional PCI config registers
-> + *????Chapter 3: NVMe control registers
-> + *????Chapter 7.3: Reset behavior
-> + */
-> +static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
-
-The name of this function seems able to be started with 'reset_' prefix just
-like other quirks for reset.
-What about reset_samsung_pm961 or something?
-
-> +{
-> +	void __iomem *bar;
-> +	u16 cmd;
-> +	u32 cfg;
-> +
-> +	if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
-> +	????!pcie_has_flr(dev) || !pci_resource_start(dev, 0))
-> +		return -ENOTTY;
-> +
-> +	if (probe)
-> +		return 0;
-> +
-> +	bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
-> +	if (!bar)
-> +		return -ENOTTY;
-> +
-> +	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-> +	pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
-> +
-> +	cfg = readl(bar + NVME_REG_CC);
-> +
-> +	/* Disable controller if enabled */
-> +	if (cfg & NVME_CC_ENABLE) {
-> +		u64 cap = readq(bar + NVME_REG_CAP);
-> +		unsigned long timeout;
-> +
-> +		/*
-> +		?* Per nvme_disable_ctrl() skip shutdown notification as it
-> +		?* could complete commands to the admin queue.??We only
-> intend
-> +		?* to quiesce the device before reset.
-> +		?*/
-> +		cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
-> +
-> +		writel(cfg, bar + NVME_REG_CC);
-> +
-> +		/*
-> +		?* Some controllers require an additional delay here, see
-> +		?* NVME_QUIRK_DELAY_BEFORE_CHK_RDY.??None of those are yet
-> +		?* supported by this quirk.
-> +		?*/
-> +
-> +		/* Cap register provides max timeout in 500ms increments */
-> +		timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
-> +
-> +		for (;;) {
-> +			u32 status = readl(bar + NVME_REG_CSTS);
-> +
-> +			/* Ready status becomes zero on disable complete */
-> +			if (!(status & NVME_CSTS_RDY))
-> +				break;
-> +
-> +			msleep(100);
-> +
-> +			if (time_after(jiffies, timeout)) {
-> +				pci_warn(dev, "Timeout waiting for NVMe ready
-> status to clear after disable\n");
-> +				break;
-> +			}
-> +		}
-> +	}
-> +
-> +	pci_iounmap(dev, bar);
-> +
-> +	pcie_flr(dev);
-> +
-> +	return 0;
-> +}
-> +
-> ?static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
-> ?	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
-> ?		?reset_intel_82599_sfp_virtfn },
-> @@ -3676,6 +3758,7 @@ static const struct pci_dev_reset_methods
-> pci_dev_reset_methods[] = {
-> ?		reset_ivb_igd },
-> ?	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
-> ?		reset_ivb_igd },
-> +	{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
-
-Why don't we just define a macro just like other DEVICE_IDs. (e.g.
-PCIE_DEVICE_ID_INTEL_82599_SFP_VF).
-
-#define PCI_DEVICE_ID_SAMSUNG_PM961 ?0xa804
-
-> ?	{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
-> ?		reset_chelsio_generic_dev },
-> ?	{ 0 }
-> 
-> 
-> _______________________________________________
-> Linux-nvme mailing list
-> Linux-nvme at lists.infradead.org
-> http://lists.infradead.org/mailman/listinfo/linux-nvme
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diff --git a/a/content_digest b/N1/content_digest
index c592d42..d21ace2 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,157 +1,100 @@
  "ref\020180724160440.2729.75178.stgit@gimli.home\0"
  "ref\020180724161440.2729.89835.stgit@gimli.home\0"
- "From\0minwoo.im.dev@gmail.com (Minwoo Im)\0"
- "Subject\0[PATCH v3 2/3] PCI: Samsung SM961/PM961 NVMe disable before FLR quirk\0"
+ "From\0Minwoo Im <minwoo.im.dev@gmail.com>\0"
+ "Subject\0Re: [PATCH v3 2/3] PCI: Samsung SM961/PM961 NVMe disable before FLR quirk\0"
  "Date\0Wed, 25 Jul 2018 04:53:18 +0900\0"
+ "To\0Alex Williamson <alex.williamson@redhat.com>"
+ " linux-pci@vger.kernel.org\0"
+ "Cc\0linux-kernel@vger.kernel.org"
+ " linux-nvme@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
- "Hi Alex,\n"
- "\n"
- "On Tue, 2018-07-24@10:14 -0600, Alex Williamson wrote:\n"
- "> The Samsung SM961/PM961 (960 EVO) sometimes fails to return from FLR\n"
- "> with the PCI config space reading back as -1.??A reproducible instance\n"
- "> of this behavior is resolved by clearing the enable bit in the NVMe\n"
- "> configuration register and waiting for the ready status to clear\n"
- "> (disabling the NVMe controller) prior to FLR.\n"
- "> \n"
- "> Signed-off-by: Alex Williamson <alex.williamson at redhat.com>\n"
- "> ---\n"
- "> ?drivers/pci/quirks.c |???83\n"
- "> ++++++++++++++++++++++++++++++++++++++++++++++++++\n"
- "> ?1 file changed, 83 insertions(+)\n"
- "> \n"
- "> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n"
- "> index e72c8742aafa..3899cdd2514b 100644\n"
- "> --- a/drivers/pci/quirks.c\n"
- "> +++ b/drivers/pci/quirks.c\n"
- "> @@ -28,6 +28,7 @@\n"
- "> ?#include <linux/platform_data/x86/apple.h>\n"
- "> ?#include <linux/pm_runtime.h>\n"
- "> ?#include <linux/switchtec.h>\n"
- "> +#include <linux/nvme.h>\n"
- "> ?#include <asm/dma.h>\t/* isa_dma_bridge_buggy */\n"
- "> ?#include \"pci.h\"\n"
- "> ?\n"
- "> @@ -3669,6 +3670,87 @@ static int reset_chelsio_generic_dev(struct pci_dev\n"
- "> *dev, int probe)\n"
- "> ?#define PCI_DEVICE_ID_INTEL_IVB_M_VGA??????0x0156\n"
- "> ?#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA?????0x0166\n"
- "> ?\n"
- "> +/*\n"
- "> + * The Samsung SM961/PM961 controller can sometimes enter a fatal state after\n"
- "> + * FLR where config space reads from the device return -1.??We seem to be\n"
- "> + * able to avoid this condition if we disable the NVMe controller prior to\n"
- "> + * FLR.??This quirk is generic for any NVMe class device requiring similar\n"
- "> + * assistance to quiesce the device prior to FLR.\n"
- "> + *\n"
- "> + * NVMe specification: https://nvmexpress.org/resources/specifications/\n"
- "> + * Revision 1.0e:\n"
- "\n"
- "It seems too old version of NVMe specification. ?Do you have any special reason\n"
- "to comment the specified 1.0 version instead of 1.3 or something newer?\n"
- "\n"
- "> + *????Chapter 2: Required and optional PCI config registers\n"
- "> + *????Chapter 3: NVMe control registers\n"
- "> + *????Chapter 7.3: Reset behavior\n"
- "> + */\n"
- "> +static int nvme_disable_and_flr(struct pci_dev *dev, int probe)\n"
- "\n"
- "The name of this function seems able to be started with 'reset_' prefix just\n"
- "like other quirks for reset.\n"
- "What about reset_samsung_pm961 or something?\n"
- "\n"
- "> +{\n"
- "> +\tvoid __iomem *bar;\n"
- "> +\tu16 cmd;\n"
- "> +\tu32 cfg;\n"
- "> +\n"
- "> +\tif (dev->class != PCI_CLASS_STORAGE_EXPRESS ||\n"
- "> +\t????!pcie_has_flr(dev) || !pci_resource_start(dev, 0))\n"
- "> +\t\treturn -ENOTTY;\n"
- "> +\n"
- "> +\tif (probe)\n"
- "> +\t\treturn 0;\n"
- "> +\n"
- "> +\tbar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));\n"
- "> +\tif (!bar)\n"
- "> +\t\treturn -ENOTTY;\n"
- "> +\n"
- "> +\tpci_read_config_word(dev, PCI_COMMAND, &cmd);\n"
- "> +\tpci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);\n"
- "> +\n"
- "> +\tcfg = readl(bar + NVME_REG_CC);\n"
- "> +\n"
- "> +\t/* Disable controller if enabled */\n"
- "> +\tif (cfg & NVME_CC_ENABLE) {\n"
- "> +\t\tu64 cap = readq(bar + NVME_REG_CAP);\n"
- "> +\t\tunsigned long timeout;\n"
- "> +\n"
- "> +\t\t/*\n"
- "> +\t\t?* Per nvme_disable_ctrl() skip shutdown notification as it\n"
- "> +\t\t?* could complete commands to the admin queue.??We only\n"
- "> intend\n"
- "> +\t\t?* to quiesce the device before reset.\n"
- "> +\t\t?*/\n"
- "> +\t\tcfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);\n"
- "> +\n"
- "> +\t\twritel(cfg, bar + NVME_REG_CC);\n"
- "> +\n"
- "> +\t\t/*\n"
- "> +\t\t?* Some controllers require an additional delay here, see\n"
- "> +\t\t?* NVME_QUIRK_DELAY_BEFORE_CHK_RDY.??None of those are yet\n"
- "> +\t\t?* supported by this quirk.\n"
- "> +\t\t?*/\n"
- "> +\n"
- "> +\t\t/* Cap register provides max timeout in 500ms increments */\n"
- "> +\t\ttimeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;\n"
- "> +\n"
- "> +\t\tfor (;;) {\n"
- "> +\t\t\tu32 status = readl(bar + NVME_REG_CSTS);\n"
- "> +\n"
- "> +\t\t\t/* Ready status becomes zero on disable complete */\n"
- "> +\t\t\tif (!(status & NVME_CSTS_RDY))\n"
- "> +\t\t\t\tbreak;\n"
- "> +\n"
- "> +\t\t\tmsleep(100);\n"
- "> +\n"
- "> +\t\t\tif (time_after(jiffies, timeout)) {\n"
- "> +\t\t\t\tpci_warn(dev, \"Timeout waiting for NVMe ready\n"
- "> status to clear after disable\\n\");\n"
- "> +\t\t\t\tbreak;\n"
- "> +\t\t\t}\n"
- "> +\t\t}\n"
- "> +\t}\n"
- "> +\n"
- "> +\tpci_iounmap(dev, bar);\n"
- "> +\n"
- "> +\tpcie_flr(dev);\n"
- "> +\n"
- "> +\treturn 0;\n"
- "> +}\n"
- "> +\n"
- "> ?static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {\n"
- "> ?\t{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,\n"
- "> ?\t\t?reset_intel_82599_sfp_virtfn },\n"
- "> @@ -3676,6 +3758,7 @@ static const struct pci_dev_reset_methods\n"
- "> pci_dev_reset_methods[] = {\n"
- "> ?\t\treset_ivb_igd },\n"
- "> ?\t{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,\n"
- "> ?\t\treset_ivb_igd },\n"
- "> +\t{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },\n"
- "\n"
- "Why don't we just define a macro just like other DEVICE_IDs. (e.g.\n"
- "PCIE_DEVICE_ID_INTEL_82599_SFP_VF).\n"
- "\n"
- "#define PCI_DEVICE_ID_SAMSUNG_PM961 ?0xa804\n"
- "\n"
- "> ?\t{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,\n"
- "> ?\t\treset_chelsio_generic_dev },\n"
- "> ?\t{ 0 }\n"
- "> \n"
- "> \n"
- "> _______________________________________________\n"
- "> Linux-nvme mailing list\n"
- "> Linux-nvme at lists.infradead.org\n"
- > http://lists.infradead.org/mailman/listinfo/linux-nvme
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