From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 Date: Wed, 25 Jul 2018 09:39:28 +0800 Message-ID: <1532482768.9280.4.camel@mtksdaap41> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stu Hsieh Cc: srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFN0dToKCkl0IGxvb2tzIGxpa2UgdGhlIHNlcmllcyBpcyBhIGJ1ZyBmaXggb2YgWzFdLiBJ biBbMV0sIHlvdSBjcmVhdGUgdGhpcmQKY3J0YyBidXQgaXQgZG9lcyBub3Qgd29yayB1bmxlc3Mg YXBwbHkgdGhpcyBzZXJpZXMuIFNvIGZvciBhbGwgdGhlCnBhdGNoZXMgaW4gdGhpcyBzZXJpZXMs IHlvdSBzaG91bGQgcmVmZXIgdG8gWzJdIHRvIGFkZCAnRml4ZXM6JyBhbmQKJ0NjOicgaW4gY29t bWl0IG1lc3NhZ2UuCgoKWzFdCmh0dHBzOi8vZ2l0Lmtlcm5lbC5vcmcvcHViL3NjbS9saW51eC9r ZXJuZWwvZ2l0L25leHQvbGludXgtbmV4dC5naXQvY29tbWl0Lz9pZD1lNmFiMDg3YTIyNGZkN2Jj ZjcxMmRiNjk4ZmJhZGU2NzNjYzlhZGRkClsyXQpodHRwczovL2dpdC5rZXJuZWwub3JnL3B1Yi9z Y20vbGludXgva2VybmVsL2dpdC9uZXh0L2xpbnV4LW5leHQuZ2l0L2NvbW1pdC8/aWQ9ODNiYTYy YmM3MDBiYWI3MTBiMjJiZTNhMWJmNmNmOTczZjc1NDI3MwoKUmVnYXJkcywKQ0sKCk9uIFR1ZSwg MjAxOC0wNy0yNCBhdCAxNjoxNyArMDgwMCwgU3R1IEhzaWVoIHdyb3RlOgo+IFRoaXMgcGF0Y2gg c2VyaWVzIGFkZCBSRE1BIG1lbW9yeSBtb2RlIHN1cHBvcnQgZm9yIG1lZGlhdGVrIFNPQyBNVDI3 MTIuCj4gTVQyNzEyIGhhcyB0aHJlZSBkaXNwbGF5IGRhdGEgcGF0aCwgaW5jbHVkaW5nIHRocmVl IEhXIGVuZ2luZSwKPiB0d28gT1ZMIGFuZCBvbmUgUkRNQS4KPiAKPiBUaGUgUkRNQSB1c2VkIGlu IHRoaXJkIGRkcCBhbmQgaXQgbmVlZCB0byBiZSBzZXQgbWVtb3J5IG1vZGUsCj4gdGhlbiBSRE1B IGNvdWxkIHJlYWQgZGF0YSBmcm9tIG1lbW9yeSBhbmQgb3V0cHV0IHRvIHBhbmVsLgo+IAo+IFN0 dSBIc2llaCAoMTUpOgo+ICAgZHJtL21lZGlhdGVrOiBhZGQgY29ubmVjdGlvbiBmcm9tIFJETUEw IHRvIERQSTEKPiAgIGRybS9tZWRpYXRlazogYWRkIGNvbm5lY3Rpb24gZnJvbSBSRE1BMCB0byBE U0kxCj4gICBkcm0vbWVkaWF0ZWs6IGFkZCBjb25uZWN0aW9uIGZyb20gUkRNQTEgdG8gRFNJMAo+ ICAgZHJtL21lZGlhdGVrOiBhZGQgY29ubmVjdGlvbiBmcm9tIFJETUEyIHRvIERTSTAKPiAgIGRy bS9tZWRpYXRlazogYWRkIFJETUEgbWVtb3J5IG1vZGUgZm9yIGNydGMgY3JlYXRlZAo+ICAgZHJt L21lZGlhdGVrOiBhZGQgbWVtb3J5IG1vZGUgZm9yIFJETUEKPiAgIGRybS9tZWRpYXRlazogYWRk IGxheWVyIGNvbmZpZyB0byBzZXQgUkRNQSBmb3IgcGxhbmUgc2V0dGluZwo+ICAgZHJtL21lZGlh dGVrOiBhZGQgUkdCIGNvbG9yIGZvcm1hdCBzdXBwb3J0IGZvciBSRE1BCj4gICBkcm0vbWVkaWF0 ZWs6IGFkZCBZVVlWL1VZVlkgY29sb3IgZm9ybWF0IHN1cHBvcnQgZm9yIFJETUEKPiAgIGRybS9t ZWRpYXRlazogYWRkIGRybV9kZXZpY2UgaW4gUkRNQSBmb3IgbWFtb3J5IG1vZGUgdG8gcmVhcXVl c3QKPiAgICAgYnVmZmVyCj4gICBkcm0vbWVkaWF0ZWs6IGFkZCBkdW1teSBidWZmZXIgZm9yIFJE TUEgbWVtb3J5IG1vZGUKPiAgIGRybS9tZWRpYXRlazogYWRkIGxheWVyIG51bWJlciBjb25kaXRp b24gZm9yIFJETUEgdG8gY29udHJvbCBwbGFuZQo+ICAgZHJtL21lZGlhdGVrOiBVcGRhdGUgc29t ZSB2YXJpYWJsZSBuYW1lIGZyb20gb3ZsIHRvIGNvbXAKPiAgIGRybS9tZWRpYXRlazogZml4ZWQg dGhlIGVycm9yIHZhbHVlIGZvciBhZGQgRFNJMSBpbiBtdXRleAo+ICAgZHJtL21lZGlhdGVrOiBm aXhlZCBjb25uZWN0aW9uIGZyb20gUkRNQTIgdG8gRFNJMQo+IAo+ICBkcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2Rpc3BfcmRtYS5jICAgIHwgMTIyICsrKysrKysrKysrKysrKysrKysrKysr KysrKy0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fY3J0Yy5jICAgICB8ICA1 OSArKysrKysrKystLS0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9jcnRj LmggICAgIHwgICA0ICstCj4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5j ICAgICAgfCAgMjAgKysrKy0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRw X2NvbXAuaCB8ICAgMiArCj4gIDUgZmlsZXMgY2hhbmdlZCwgMTgxIGluc2VydGlvbnMoKyksIDI2 IGRlbGV0aW9ucygtKQo+IAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNr dG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2Ry aS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: ck.hu@mediatek.com (CK Hu) Date: Wed, 25 Jul 2018 09:39:28 +0800 Subject: [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 In-Reply-To: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> Message-ID: <1532482768.9280.4.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Stu: It looks like the series is a bug fix of [1]. In [1], you create third crtc but it does not work unless apply this series. So for all the patches in this series, you should refer to [2] to add 'Fixes:' and 'Cc:' in commit message. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e6ab087a224fd7bcf712db698fbade673cc9addd [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=83ba62bc700bab710b22be3a1bf6cf973f754273 Regards, CK On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote: > This patch series add RDMA memory mode support for mediatek SOC MT2712. > MT2712 has three display data path, including three HW engine, > two OVL and one RDMA. > > The RDMA used in third ddp and it need to be set memory mode, > then RDMA could read data from memory and output to panel. > > Stu Hsieh (15): > drm/mediatek: add connection from RDMA0 to DPI1 > drm/mediatek: add connection from RDMA0 to DSI1 > drm/mediatek: add connection from RDMA1 to DSI0 > drm/mediatek: add connection from RDMA2 to DSI0 > drm/mediatek: add RDMA memory mode for crtc created > drm/mediatek: add memory mode for RDMA > drm/mediatek: add layer config to set RDMA for plane setting > drm/mediatek: add RGB color format support for RDMA > drm/mediatek: add YUYV/UYVY color format support for RDMA > drm/mediatek: add drm_device in RDMA for mamory mode to reaquest > buffer > drm/mediatek: add dummy buffer for RDMA memory mode > drm/mediatek: add layer number condition for RDMA to control plane > drm/mediatek: Update some variable name from ovl to comp > drm/mediatek: fixed the error value for add DSI1 in mutex > drm/mediatek: fixed connection from RDMA2 to DSI1 > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 122 +++++++++++++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 59 +++++++++----- > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 20 ++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 + > 5 files changed, 181 insertions(+), 26 deletions(-) > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 515DDC28CF6 for ; Wed, 25 Jul 2018 01:39:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F189F20852 for ; Wed, 25 Jul 2018 01:39:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F189F20852 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388578AbeGYCs6 (ORCPT ); Tue, 24 Jul 2018 22:48:58 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:33778 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2388461AbeGYCs6 (ORCPT ); Tue, 24 Jul 2018 22:48:58 -0400 X-UUID: 65f62d0907274f7eaee9518dbdc878e9-20180725 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 810408221; Wed, 25 Jul 2018 09:39:30 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 25 Jul 2018 09:39:28 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 25 Jul 2018 09:39:28 +0800 Message-ID: <1532482768.9280.4.camel@mtksdaap41> Subject: Re: [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 From: CK Hu To: Stu Hsieh CC: Philipp Zabel , David Airlie , Matthias Brugger , , , , , Date: Wed, 25 Jul 2018 09:39:28 +0800 In-Reply-To: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Stu: It looks like the series is a bug fix of [1]. In [1], you create third crtc but it does not work unless apply this series. So for all the patches in this series, you should refer to [2] to add 'Fixes:' and 'Cc:' in commit message. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e6ab087a224fd7bcf712db698fbade673cc9addd [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=83ba62bc700bab710b22be3a1bf6cf973f754273 Regards, CK On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote: > This patch series add RDMA memory mode support for mediatek SOC MT2712. > MT2712 has three display data path, including three HW engine, > two OVL and one RDMA. > > The RDMA used in third ddp and it need to be set memory mode, > then RDMA could read data from memory and output to panel. > > Stu Hsieh (15): > drm/mediatek: add connection from RDMA0 to DPI1 > drm/mediatek: add connection from RDMA0 to DSI1 > drm/mediatek: add connection from RDMA1 to DSI0 > drm/mediatek: add connection from RDMA2 to DSI0 > drm/mediatek: add RDMA memory mode for crtc created > drm/mediatek: add memory mode for RDMA > drm/mediatek: add layer config to set RDMA for plane setting > drm/mediatek: add RGB color format support for RDMA > drm/mediatek: add YUYV/UYVY color format support for RDMA > drm/mediatek: add drm_device in RDMA for mamory mode to reaquest > buffer > drm/mediatek: add dummy buffer for RDMA memory mode > drm/mediatek: add layer number condition for RDMA to control plane > drm/mediatek: Update some variable name from ovl to comp > drm/mediatek: fixed the error value for add DSI1 in mutex > drm/mediatek: fixed connection from RDMA2 to DSI1 > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 122 +++++++++++++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 59 +++++++++----- > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 20 ++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 + > 5 files changed, 181 insertions(+), 26 deletions(-) >