From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stu Hsieh Subject: Re: [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 Date: Thu, 2 Aug 2018 19:29:22 +0800 Message-ID: <1533209362.11190.54.camel@mtksdccf07> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> <1532482768.9280.4.camel@mtksdaap41> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532482768.9280.4.camel@mtksdaap41> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: CK Hu Cc: srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIENLOgoKT24gV2VkLCAyMDE4LTA3LTI1IGF0IDA5OjM5ICswODAwLCBDSyBIdSB3cm90ZToK PiBIaSwgU3R1Ogo+IAo+IEl0IGxvb2tzIGxpa2UgdGhlIHNlcmllcyBpcyBhIGJ1ZyBmaXggb2Yg WzFdLiBJbiBbMV0sIHlvdSBjcmVhdGUgdGhpcmQKPiBjcnRjIGJ1dCBpdCBkb2VzIG5vdCB3b3Jr IHVubGVzcyBhcHBseSB0aGlzIHNlcmllcy4gU28gZm9yIGFsbCB0aGUKPiBwYXRjaGVzIGluIHRo aXMgc2VyaWVzLCB5b3Ugc2hvdWxkIHJlZmVyIHRvIFsyXSB0byBhZGQgJ0ZpeGVzOicgYW5kCj4g J0NjOicgaW4gY29tbWl0IG1lc3NhZ2UuCj4gCj4gCj4gWzFdCj4gaHR0cHM6Ly9naXQua2VybmVs Lm9yZy9wdWIvc2NtL2xpbnV4L2tlcm5lbC9naXQvbmV4dC9saW51eC1uZXh0LmdpdC9jb21taXQv P2lkPWU2YWIwODdhMjI0ZmQ3YmNmNzEyZGI2OThmYmFkZTY3M2NjOWFkZGQKPiBbMl0KPiBodHRw czovL2dpdC5rZXJuZWwub3JnL3B1Yi9zY20vbGludXgva2VybmVsL2dpdC9uZXh0L2xpbnV4LW5l eHQuZ2l0L2NvbW1pdC8/aWQ9ODNiYTYyYmM3MDBiYWI3MTBiMjJiZTNhMWJmNmNmOTczZjc1NDI3 Mwo+IAo+IFJlZ2FyZHMsCj4gQ0sKPiAKCk9LCgpSZWdhcmRzLApTdHUKCj4gT24gVHVlLCAyMDE4 LTA3LTI0IGF0IDE2OjE3ICswODAwLCBTdHUgSHNpZWggd3JvdGU6Cj4gPiBUaGlzIHBhdGNoIHNl cmllcyBhZGQgUkRNQSBtZW1vcnkgbW9kZSBzdXBwb3J0IGZvciBtZWRpYXRlayBTT0MgTVQyNzEy Lgo+ID4gTVQyNzEyIGhhcyB0aHJlZSBkaXNwbGF5IGRhdGEgcGF0aCwgaW5jbHVkaW5nIHRocmVl IEhXIGVuZ2luZSwKPiA+IHR3byBPVkwgYW5kIG9uZSBSRE1BLgo+ID4gCj4gPiBUaGUgUkRNQSB1 c2VkIGluIHRoaXJkIGRkcCBhbmQgaXQgbmVlZCB0byBiZSBzZXQgbWVtb3J5IG1vZGUsCj4gPiB0 aGVuIFJETUEgY291bGQgcmVhZCBkYXRhIGZyb20gbWVtb3J5IGFuZCBvdXRwdXQgdG8gcGFuZWwu Cj4gPiAKPiA+IFN0dSBIc2llaCAoMTUpOgo+ID4gICBkcm0vbWVkaWF0ZWs6IGFkZCBjb25uZWN0 aW9uIGZyb20gUkRNQTAgdG8gRFBJMQo+ID4gICBkcm0vbWVkaWF0ZWs6IGFkZCBjb25uZWN0aW9u IGZyb20gUkRNQTAgdG8gRFNJMQo+ID4gICBkcm0vbWVkaWF0ZWs6IGFkZCBjb25uZWN0aW9uIGZy b20gUkRNQTEgdG8gRFNJMAo+ID4gICBkcm0vbWVkaWF0ZWs6IGFkZCBjb25uZWN0aW9uIGZyb20g UkRNQTIgdG8gRFNJMAo+ID4gICBkcm0vbWVkaWF0ZWs6IGFkZCBSRE1BIG1lbW9yeSBtb2RlIGZv ciBjcnRjIGNyZWF0ZWQKPiA+ICAgZHJtL21lZGlhdGVrOiBhZGQgbWVtb3J5IG1vZGUgZm9yIFJE TUEKPiA+ICAgZHJtL21lZGlhdGVrOiBhZGQgbGF5ZXIgY29uZmlnIHRvIHNldCBSRE1BIGZvciBw bGFuZSBzZXR0aW5nCj4gPiAgIGRybS9tZWRpYXRlazogYWRkIFJHQiBjb2xvciBmb3JtYXQgc3Vw cG9ydCBmb3IgUkRNQQo+ID4gICBkcm0vbWVkaWF0ZWs6IGFkZCBZVVlWL1VZVlkgY29sb3IgZm9y bWF0IHN1cHBvcnQgZm9yIFJETUEKPiA+ICAgZHJtL21lZGlhdGVrOiBhZGQgZHJtX2RldmljZSBp biBSRE1BIGZvciBtYW1vcnkgbW9kZSB0byByZWFxdWVzdAo+ID4gICAgIGJ1ZmZlcgo+ID4gICBk cm0vbWVkaWF0ZWs6IGFkZCBkdW1teSBidWZmZXIgZm9yIFJETUEgbWVtb3J5IG1vZGUKPiA+ICAg ZHJtL21lZGlhdGVrOiBhZGQgbGF5ZXIgbnVtYmVyIGNvbmRpdGlvbiBmb3IgUkRNQSB0byBjb250 cm9sIHBsYW5lCj4gPiAgIGRybS9tZWRpYXRlazogVXBkYXRlIHNvbWUgdmFyaWFibGUgbmFtZSBm cm9tIG92bCB0byBjb21wCj4gPiAgIGRybS9tZWRpYXRlazogZml4ZWQgdGhlIGVycm9yIHZhbHVl IGZvciBhZGQgRFNJMSBpbiBtdXRleAo+ID4gICBkcm0vbWVkaWF0ZWs6IGZpeGVkIGNvbm5lY3Rp b24gZnJvbSBSRE1BMiB0byBEU0kxCj4gPiAKPiA+ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsv bXRrX2Rpc3BfcmRtYS5jICAgIHwgMTIyICsrKysrKysrKysrKysrKysrKysrKysrKysrKy0KPiA+ ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9jcnRjLmMgICAgIHwgIDU5ICsrKysr KysrKy0tLS0tCj4gPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fY3J0Yy5oICAg ICB8ICAgNCArLQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5jICAg ICAgfCAgMjAgKysrKy0KPiA+ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBf Y29tcC5oIHwgICAyICsKPiA+ICA1IGZpbGVzIGNoYW5nZWQsIDE4MSBpbnNlcnRpb25zKCspLCAy NiBkZWxldGlvbnMoLSkKPiA+IAo+IAo+IAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: stu.hsieh@mediatek.com (Stu Hsieh) Date: Thu, 2 Aug 2018 19:29:22 +0800 Subject: [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 In-Reply-To: <1532482768.9280.4.camel@mtksdaap41> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> <1532482768.9280.4.camel@mtksdaap41> Message-ID: <1533209362.11190.54.camel@mtksdccf07> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, CK: On Wed, 2018-07-25 at 09:39 +0800, CK Hu wrote: > Hi, Stu: > > It looks like the series is a bug fix of [1]. In [1], you create third > crtc but it does not work unless apply this series. So for all the > patches in this series, you should refer to [2] to add 'Fixes:' and > 'Cc:' in commit message. > > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e6ab087a224fd7bcf712db698fbade673cc9addd > [2] > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=83ba62bc700bab710b22be3a1bf6cf973f754273 > > Regards, > CK > OK Regards, Stu > On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote: > > This patch series add RDMA memory mode support for mediatek SOC MT2712. > > MT2712 has three display data path, including three HW engine, > > two OVL and one RDMA. > > > > The RDMA used in third ddp and it need to be set memory mode, > > then RDMA could read data from memory and output to panel. > > > > Stu Hsieh (15): > > drm/mediatek: add connection from RDMA0 to DPI1 > > drm/mediatek: add connection from RDMA0 to DSI1 > > drm/mediatek: add connection from RDMA1 to DSI0 > > drm/mediatek: add connection from RDMA2 to DSI0 > > drm/mediatek: add RDMA memory mode for crtc created > > drm/mediatek: add memory mode for RDMA > > drm/mediatek: add layer config to set RDMA for plane setting > > drm/mediatek: add RGB color format support for RDMA > > drm/mediatek: add YUYV/UYVY color format support for RDMA > > drm/mediatek: add drm_device in RDMA for mamory mode to reaquest > > buffer > > drm/mediatek: add dummy buffer for RDMA memory mode > > drm/mediatek: add layer number condition for RDMA to control plane > > drm/mediatek: Update some variable name from ovl to comp > > drm/mediatek: fixed the error value for add DSI1 in mutex > > drm/mediatek: fixed connection from RDMA2 to DSI1 > > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 122 +++++++++++++++++++++++++++- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 59 +++++++++----- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 20 ++++- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 + > > 5 files changed, 181 insertions(+), 26 deletions(-) > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4A8EC43142 for ; Thu, 2 Aug 2018 11:29:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8093F214F1 for ; Thu, 2 Aug 2018 11:29:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8093F214F1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732251AbeHBNUP (ORCPT ); Thu, 2 Aug 2018 09:20:15 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:29427 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731083AbeHBNUO (ORCPT ); Thu, 2 Aug 2018 09:20:14 -0400 X-UUID: 17c4ff6aa2d84c0580c6e3d8ae3c330f-20180802 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1234062202; Thu, 02 Aug 2018 19:29:24 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 2 Aug 2018 19:29:22 +0800 Received: from [172.21.84.99] (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 2 Aug 2018 19:29:22 +0800 Message-ID: <1533209362.11190.54.camel@mtksdccf07> Subject: Re: [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 From: Stu Hsieh To: CK Hu CC: Philipp Zabel , David Airlie , Matthias Brugger , , , , , Date: Thu, 2 Aug 2018 19:29:22 +0800 In-Reply-To: <1532482768.9280.4.camel@mtksdaap41> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> <1532482768.9280.4.camel@mtksdaap41> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, CK: On Wed, 2018-07-25 at 09:39 +0800, CK Hu wrote: > Hi, Stu: > > It looks like the series is a bug fix of [1]. In [1], you create third > crtc but it does not work unless apply this series. So for all the > patches in this series, you should refer to [2] to add 'Fixes:' and > 'Cc:' in commit message. > > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e6ab087a224fd7bcf712db698fbade673cc9addd > [2] > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=83ba62bc700bab710b22be3a1bf6cf973f754273 > > Regards, > CK > OK Regards, Stu > On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote: > > This patch series add RDMA memory mode support for mediatek SOC MT2712. > > MT2712 has three display data path, including three HW engine, > > two OVL and one RDMA. > > > > The RDMA used in third ddp and it need to be set memory mode, > > then RDMA could read data from memory and output to panel. > > > > Stu Hsieh (15): > > drm/mediatek: add connection from RDMA0 to DPI1 > > drm/mediatek: add connection from RDMA0 to DSI1 > > drm/mediatek: add connection from RDMA1 to DSI0 > > drm/mediatek: add connection from RDMA2 to DSI0 > > drm/mediatek: add RDMA memory mode for crtc created > > drm/mediatek: add memory mode for RDMA > > drm/mediatek: add layer config to set RDMA for plane setting > > drm/mediatek: add RGB color format support for RDMA > > drm/mediatek: add YUYV/UYVY color format support for RDMA > > drm/mediatek: add drm_device in RDMA for mamory mode to reaquest > > buffer > > drm/mediatek: add dummy buffer for RDMA memory mode > > drm/mediatek: add layer number condition for RDMA to control plane > > drm/mediatek: Update some variable name from ovl to comp > > drm/mediatek: fixed the error value for add DSI1 in mutex > > drm/mediatek: fixed connection from RDMA2 to DSI1 > > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 122 +++++++++++++++++++++++++++- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 59 +++++++++----- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 20 ++++- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 + > > 5 files changed, 181 insertions(+), 26 deletions(-) > > > >