diff for duplicates of <1535406078.3416.9.camel@intel.com> diff --git a/a/1.txt b/N1/1.txt index 03188ea..926a3ac 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,116 +1,208 @@ -T24gTW9uLCAyMDE4LTA4LTI3IGF0IDIxOjUzICswMzAwLCBKYXJra28gU2Fra2luZW4gd3JvdGU6 -DQo+IEZyb206IFNlYW4gQ2hyaXN0b3BoZXJzb24gPHNlYW4uai5jaHJpc3RvcGhlcnNvbkBpbnRl -bC5jb20+DQo+IA0KPiBBZGQgYSBmdW5jdGlvbiB0byBwZXJmb3JtIEVOQ0xTKEVJTklUKSwgd2hp -Y2ggaW5pdGlhbGl6ZXMgYW4gZW5jbGF2ZSwNCj4gd2hpY2ggY2FuIGJlIHVzZWQgYnkgYSBkcml2 -ZXIgZm9yIHJ1bm5pbmcgZW5jbGF2ZXMgYW5kIFZNTXMuDQo+IA0KPiBXcml0aW5nIHRoZSBMRSBo -YXNoIE1TUnMgaXMgZXh0cmFvcmRpbmFyaWx5IGV4cGVuc2l2ZSwgZS5nLiAzLTR4DQo+IHNsb3dl -cg0KPiB0aGFuIG5vcm1hbCBNU1JzLCBzbyB3ZSB1c2UgYSBwZXItY3B1IGNhY2hlIHRvIHRyYWNr -IHRoZSBsYXN0IGtub3duDQo+IHZhbHVlDQo+IG9mIHRoZSBNU1JzIHRvIGF2b2lkIHVubmVjZXNz -YXJpbHkgd3JpdGluZyB0aGUgTVNScyB3aXRoIHRoZSBjdXJyZW50DQo+IHZhbHVlLg0KPiANCj4g -U2lnbmVkLW9mZi1ieTogU2VhbiBDaHJpc3RvcGhlcnNvbiA8c2Vhbi5qLmNocmlzdG9waGVyc29u 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-X0VSUih0c2spKSB7DQo+IC0JCXNneF9wYWdlX2NhY2hlX3RlYXJkb3duKCk7DQo+IC0JCXJldHVy -biBQVFJfRVJSKHRzayk7DQo+ICsJCXJldCA9IFBUUl9FUlIodHNrKTsNCj4gKwkJZ290byBvdXRf -cGNhY2hlOw0KPiAgCX0NCj4gIAlrc2d4c3dhcGRfdHNrID0gdHNrOw0KPiAgDQo+ICAJc2d4X2Vu -YWJsZWQgPSB0cnVlOw0KPiAgCXNneF9sY19lbmFibGVkID0gISEoZmMgJiBGRUFUVVJFX0NPTlRS -T0xfU0dYX0xFX1dSKTsNCj4gIAlyZXR1cm4gMDsNCj4gK291dF9wY2FjaGU6DQo+ICsJc2d4X3Bh -Z2VfY2FjaGVfdGVhcmRvd24oKTsNCg0KSSBkb24ndCB0aGluayB0aGlzIHBhcnRpY3VsYXIgMiBs -aW5lcyBvZiBjb2RlIG9mICdvdXRfcGNhY2hlJyBjYXNlDQpzaG91bGQgYmUgaW4gdGhpcyBwYXRj -aD8NCg0KVGhhbmtzLA0KLUthaQ0KDQo+ICtvdXRfcG06DQo+ICsJdW5yZWdpc3Rlcl9wbV9ub3Rp -Zmllcigmc2d4X3BtX25vdGlmaWVyKTsNCj4gKwlyZXR1cm4gcmV0Ow0KPiAgfQ0KPiAgDQo+ICBh -cmNoX2luaXRjYWxsKHNneF9pbml0KTs= +On Mon, 2018-08-27 at 21:53 +0300, Jarkko Sakkinen wrote: +> From: Sean Christopherson <sean.j.christopherson@intel.com> +> +> Add a function to perform ENCLS(EINIT), which initializes an enclave, +> which can be used by a driver for running enclaves and VMMs. +> +> Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x +> slower +> than normal MSRs, so we use a per-cpu cache to track the last known +> value +> of the MSRs to avoid unnecessarily writing the MSRs with the current +> value. +> +> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> +> Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> +> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> +> --- +> arch/x86/include/asm/sgx.h | 2 + +> arch/x86/kernel/cpu/intel_sgx.c | 86 +> +++++++++++++++++++++++++++++++-- +> 2 files changed, 85 insertions(+), 3 deletions(-) +> +> diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h +> index baf30d49b71f..c15c156436be 100644 +> --- a/arch/x86/include/asm/sgx.h +> +++ b/arch/x86/include/asm/sgx.h +> @@ -108,6 +108,8 @@ void sgx_free_page(struct sgx_epc_page *page); +> void sgx_page_reclaimable(struct sgx_epc_page *page); +> struct page *sgx_get_backing(struct file *file, pgoff_t index); +> void sgx_put_backing(struct page *backing_page, bool write); +> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken +> *token, +> + struct sgx_epc_page *secs_page, u64 lepubkeyhash[4]); +> +> #define ENCLS_FAULT_FLAG 0x40000000UL +> #define ENCLS_FAULT_FLAG_ASM "$0x40000000" +> diff --git a/arch/x86/kernel/cpu/intel_sgx.c +> b/arch/x86/kernel/cpu/intel_sgx.c +> index 1046478a3ab9..fe25e6805680 100644 +> --- a/arch/x86/kernel/cpu/intel_sgx.c +> +++ b/arch/x86/kernel/cpu/intel_sgx.c +> @@ -9,6 +9,7 @@ +> #include <linux/sched/signal.h> +> #include <linux/shmem_fs.h> +> #include <linux/slab.h> +> +#include <linux/suspend.h> +> #include <asm/sgx.h> +> #include <asm/sgx_pr.h> +> +> @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list); +> static DEFINE_SPINLOCK(sgx_active_page_list_lock); +> static struct task_struct *ksgxswapd_tsk; +> static DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq); +> +static struct notifier_block sgx_pm_notifier; +> +static u64 sgx_pm_cnt; +> + +> +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx MSRs +> for each +> + * CPU. The entries are initialized when they are first used by +> sgx_einit(). +> + */ +> +struct sgx_lepubkeyhash { +> + u64 msrs[4]; +> + u64 pm_cnt; + +May I ask why do we need pm_cnt here? In fact why do we need suspend +staff (namely, sgx_pm_cnt above, and related code in this patch) here +in this patch? From the patch commit message I don't see why we need PM +staff here. Please give comment why you need PM staff, or you may +consider to split the PM staff to another patch. + +> +}; +> + +> +static DEFINE_PER_CPU(struct sgx_lepubkeyhash *, +> sgx_lepubkeyhash_cache); +> +> /** +> * sgx_reclaim_pages - reclaim EPC pages from the consumers +> @@ -328,6 +341,54 @@ void sgx_put_backing(struct page *backing_page, +> bool write) +> } +> EXPORT_SYMBOL_GPL(sgx_put_backing); +> +> +/** +> + * sgx_einit - initialize an enclave +> + * @sigstruct: a pointer to the SIGSTRUCT +> + * @token: a pointer to the EINITTOKEN +> + * @secs_page: a pointer to the SECS EPC page +> + * @lepubkeyhash: the desired value for IA32_SGXLEPUBKEYHASHx +> MSRs +> + * +> + * Try to perform EINIT operation. If the MSRs are writable, they +> are updated +> + * according to @lepubkeyhash. +> + * +> + * Return: +> + * 0 on success, +> + * -errno on failure +> + * SGX error code if EINIT fails +> + */ +> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken +> *token, +> + struct sgx_epc_page *secs_page, u64 lepubkeyhash[4]) +> +{ +> + struct sgx_lepubkeyhash __percpu *cache; +> + bool cache_valid; +> + int i, ret; +> + +> + if (!sgx_lc_enabled) +> + return __einit(sigstruct, token, +> sgx_epc_addr(secs_page)); +> + +> + cache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id()); +> + if (!cache) { +> + cache = kzalloc(sizeof(struct sgx_lepubkeyhash), +> GFP_KERNEL); +> + if (!cache) +> + return -ENOMEM; +> + } + +It seems per-cpu variable is a pointer to struct sgx_lepubkeyhash, and +the actual structure is allocated at the first time the function is +called. May I ask when will it be freed? It seems the free is not in +this patch. Or I am misunderstanding something? + +> + +> + cache_valid = cache->pm_cnt == sgx_pm_cnt; +> + cache->pm_cnt = sgx_pm_cnt; +> + preempt_disable(); +> + for (i = 0; i < 4; i++) { +> + if (cache_valid && lepubkeyhash[i] == cache- +> >msrs[i]) +> + continue; +> + +> + wrmsrl(MSR_IA32_SGXLEPUBKEYHASH0 + i, +> lepubkeyhash[i]); +> + cache->msrs[i] = lepubkeyhash[i]; +> + } +> + ret = __einit(sigstruct, token, sgx_epc_addr(secs_page)); +> + preempt_enable(); +> + return ret; +> +} +> +EXPORT_SYMBOL(sgx_einit); +> + +> static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned +> long index, +> struct sgx_epc_bank *bank) +> { +> @@ -426,6 +487,15 @@ static __init int sgx_page_cache_init(void) +> return 0; +> } +> +> +static int sgx_pm_notifier_cb(struct notifier_block *nb, unsigned +> long action, +> + void *data) +> +{ +> + if (action == PM_SUSPEND_PREPARE || action == +> PM_HIBERNATION_PREPARE) +> + sgx_pm_cnt++; +> + +> + return NOTIFY_DONE; +> +} +> + +> static __init int sgx_init(void) +> { +> struct task_struct *tsk; +> @@ -452,20 +522,30 @@ static __init int sgx_init(void) +> if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) +> pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not +> writable\n"); +> +> - ret = sgx_page_cache_init(); +> + sgx_pm_notifier.notifier_call = sgx_pm_notifier_cb; +> + ret = register_pm_notifier(&sgx_pm_notifier); +> if (ret) +> return ret; +> +> + ret = sgx_page_cache_init(); +> + if (ret) +> + goto out_pm; +> + +> tsk = kthread_run(ksgxswapd, NULL, "ksgxswapd"); +> if (IS_ERR(tsk)) { +> - sgx_page_cache_teardown(); +> - return PTR_ERR(tsk); +> + ret = PTR_ERR(tsk); +> + goto out_pcache; +> } +> ksgxswapd_tsk = tsk; +> +> sgx_enabled = true; +> sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR); +> return 0; +> +out_pcache: +> + sgx_page_cache_teardown(); + +I don't think this particular 2 lines of code of 'out_pcache' case +should be in this patch? + +Thanks, +-Kai + +> +out_pm: +> + unregister_pm_notifier(&sgx_pm_notifier); +> + return ret; +> } +> +> arch_initcall(sgx_init); diff --git a/a/content_digest b/N1/content_digest index efb573d..485e953 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,7 @@ "ref\020180827185507.17087-11-jarkko.sakkinen@linux.intel.com\0" "From\0Huang, Kai <kai.huang@intel.com>\0" "Subject\0Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves\0" - "Date\0Mon, 27 Aug 2018 14:41:22 -0700\0" + "Date\0Mon, 27 Aug 2018 21:41:22 +0000\0" "To\0jarkko.sakkinen@linux.intel.com <jarkko.sakkinen@linux.intel.com>" platform-driver-x86@vger.kernel.org <platform-driver-x86@vger.kernel.org> " x86@kernel.org <x86@kernel.org>\0" @@ -22,121 +22,213 @@ " Dave <dave.hansen@intel.com>\0" "\00:1\0" "b\0" - "T24gTW9uLCAyMDE4LTA4LTI3IGF0IDIxOjUzICswMzAwLCBKYXJra28gU2Fra2luZW4gd3JvdGU6\n" - "DQo+IEZyb206IFNlYW4gQ2hyaXN0b3BoZXJzb24gPHNlYW4uai5jaHJpc3RvcGhlcnNvbkBpbnRl\n" - "bC5jb20+DQo+IA0KPiBBZGQgYSBmdW5jdGlvbiB0byBwZXJmb3JtIEVOQ0xTKEVJTklUKSwgd2hp\n" - "Y2ggaW5pdGlhbGl6ZXMgYW4gZW5jbGF2ZSwNCj4gd2hpY2ggY2FuIGJlIHVzZWQgYnkgYSBkcml2\n" - "ZXIgZm9yIHJ1bm5pbmcgZW5jbGF2ZXMgYW5kIFZNTXMuDQo+IA0KPiBXcml0aW5nIHRoZSBMRSBo\n" - "YXNoIE1TUnMgaXMgZXh0cmFvcmRpbmFyaWx5IGV4cGVuc2l2ZSwgZS5nLiAzLTR4DQo+IHNsb3dl\n" - "cg0KPiB0aGFuIG5vcm1hbCBNU1JzLCBzbyB3ZSB1c2UgYSBwZXItY3B1IGNhY2hlIHRvIHRyYWNr\n" - "IHRoZSBsYXN0IGtub3duDQo+IHZhbHVlDQo+IG9mIHRoZSBNU1JzIHRvIGF2b2lkIHVubmVjZXNz\n" - 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"aW5lcyBvZiBjb2RlIG9mICdvdXRfcGNhY2hlJyBjYXNlDQpzaG91bGQgYmUgaW4gdGhpcyBwYXRj\n" - "aD8NCg0KVGhhbmtzLA0KLUthaQ0KDQo+ICtvdXRfcG06DQo+ICsJdW5yZWdpc3Rlcl9wbV9ub3Rp\n" - "Zmllcigmc2d4X3BtX25vdGlmaWVyKTsNCj4gKwlyZXR1cm4gcmV0Ow0KPiAgfQ0KPiAgDQo+ICBh\n" - cmNoX2luaXRjYWxsKHNneF9pbml0KTs= + "On Mon, 2018-08-27 at 21:53 +0300, Jarkko Sakkinen wrote:\n" + "> From: Sean Christopherson <sean.j.christopherson@intel.com>\n" + "> \n" + "> Add a function to perform ENCLS(EINIT), which initializes an enclave,\n" + "> which can be used by a driver for running enclaves and VMMs.\n" + "> \n" + "> Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x\n" + "> slower\n" + "> than normal MSRs, so we use a per-cpu cache to track the last known\n" + "> value\n" + "> of the MSRs to avoid unnecessarily writing the MSRs with the current\n" + "> value.\n" + "> \n" + "> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>\n" + "> Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>\n" + "> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>\n" + "> ---\n" + "> arch/x86/include/asm/sgx.h | 2 +\n" + "> arch/x86/kernel/cpu/intel_sgx.c | 86\n" + "> +++++++++++++++++++++++++++++++--\n" + "> 2 files changed, 85 insertions(+), 3 deletions(-)\n" + "> \n" + "> diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h\n" + "> index baf30d49b71f..c15c156436be 100644\n" + "> --- a/arch/x86/include/asm/sgx.h\n" + "> +++ b/arch/x86/include/asm/sgx.h\n" + "> @@ -108,6 +108,8 @@ void sgx_free_page(struct sgx_epc_page *page);\n" + "> void sgx_page_reclaimable(struct sgx_epc_page *page);\n" + "> struct page *sgx_get_backing(struct file *file, pgoff_t index);\n" + "> void sgx_put_backing(struct page *backing_page, bool write);\n" + "> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken\n" + "> *token,\n" + "> +\t struct sgx_epc_page *secs_page, u64 lepubkeyhash[4]);\n" + "> \n" + "> #define ENCLS_FAULT_FLAG 0x40000000UL\n" + "> #define ENCLS_FAULT_FLAG_ASM \"$0x40000000\"\n" + "> diff --git a/arch/x86/kernel/cpu/intel_sgx.c\n" + "> b/arch/x86/kernel/cpu/intel_sgx.c\n" + "> index 1046478a3ab9..fe25e6805680 100644\n" + "> --- a/arch/x86/kernel/cpu/intel_sgx.c\n" + "> +++ b/arch/x86/kernel/cpu/intel_sgx.c\n" + "> @@ -9,6 +9,7 @@\n" + "> #include <linux/sched/signal.h>\n" + "> #include <linux/shmem_fs.h>\n" + "> #include <linux/slab.h>\n" + "> +#include <linux/suspend.h>\n" + "> #include <asm/sgx.h>\n" + "> #include <asm/sgx_pr.h>\n" + "> \n" + "> @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);\n" + "> static DEFINE_SPINLOCK(sgx_active_page_list_lock);\n" + "> static struct task_struct *ksgxswapd_tsk;\n" + "> static DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);\n" + "> +static struct notifier_block sgx_pm_notifier;\n" + "> +static u64 sgx_pm_cnt;\n" + "> +\n" + "> +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx MSRs\n" + "> for each\n" + "> + * CPU. The entries are initialized when they are first used by\n" + "> sgx_einit().\n" + "> + */\n" + "> +struct sgx_lepubkeyhash {\n" + "> +\tu64 msrs[4];\n" + "> +\tu64 pm_cnt;\n" + "\n" + "May I ask why do we need pm_cnt here? In fact why do we need suspend\n" + "staff (namely, sgx_pm_cnt above, and related code in this patch) here\n" + "in this patch? From the patch commit message I don't see why we need PM\n" + "staff here. Please give comment why you need PM staff, or you may\n" + "consider to split the PM staff to another patch.\n" + "\n" + "> +};\n" + "> +\n" + "> +static DEFINE_PER_CPU(struct sgx_lepubkeyhash *,\n" + "> sgx_lepubkeyhash_cache);\n" + "> \n" + "> /**\n" + "> * sgx_reclaim_pages - reclaim EPC pages from the consumers\n" + "> @@ -328,6 +341,54 @@ void sgx_put_backing(struct page *backing_page,\n" + "> bool write)\n" + "> }\n" + "> EXPORT_SYMBOL_GPL(sgx_put_backing);\n" + "> \n" + "> +/**\n" + "> + * sgx_einit - initialize an enclave\n" + "> + * @sigstruct:\t\ta pointer to the SIGSTRUCT\n" + "> + * @token:\t\ta pointer to the EINITTOKEN\n" + "> + * @secs_page:\t\ta pointer to the SECS EPC page\n" + "> + * @lepubkeyhash:\tthe desired value for IA32_SGXLEPUBKEYHASHx\n" + "> MSRs\n" + "> + *\n" + "> + * Try to perform EINIT operation. If the MSRs are writable, they\n" + "> are updated\n" + "> + * according to @lepubkeyhash.\n" + "> + *\n" + "> + * Return:\n" + "> + * 0 on success,\n" + "> + * -errno on failure\n" + "> + * SGX error code if EINIT fails\n" + "> + */\n" + "> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken\n" + "> *token,\n" + "> +\t struct sgx_epc_page *secs_page, u64 lepubkeyhash[4])\n" + "> +{\n" + "> +\tstruct sgx_lepubkeyhash __percpu *cache;\n" + "> +\tbool cache_valid;\n" + "> +\tint i, ret;\n" + "> +\n" + "> +\tif (!sgx_lc_enabled)\n" + "> +\t\treturn __einit(sigstruct, token,\n" + "> sgx_epc_addr(secs_page));\n" + "> +\n" + "> +\tcache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id());\n" + "> +\tif (!cache) {\n" + "> +\t\tcache = kzalloc(sizeof(struct sgx_lepubkeyhash),\n" + "> GFP_KERNEL);\n" + "> +\t\tif (!cache)\n" + "> +\t\t\treturn -ENOMEM;\n" + "> +\t}\n" + "\n" + "It seems per-cpu variable is a pointer to struct sgx_lepubkeyhash, and\n" + "the actual structure is allocated at the first time the function is\n" + "called. May I ask when will it be freed? It seems the free is not in\n" + "this patch. Or I am misunderstanding something?\n" + "\n" + "> +\n" + "> +\tcache_valid = cache->pm_cnt == sgx_pm_cnt;\n" + "> +\tcache->pm_cnt = sgx_pm_cnt;\n" + "> +\tpreempt_disable();\n" + "> +\tfor (i = 0; i < 4; i++) {\n" + "> +\t\tif (cache_valid && lepubkeyhash[i] == cache-\n" + "> >msrs[i])\n" + "> +\t\t\tcontinue;\n" + "> +\n" + "> +\t\twrmsrl(MSR_IA32_SGXLEPUBKEYHASH0 + i,\n" + "> lepubkeyhash[i]);\n" + "> +\t\tcache->msrs[i] = lepubkeyhash[i];\n" + "> +\t}\n" + "> +\tret = __einit(sigstruct, token, sgx_epc_addr(secs_page));\n" + "> +\tpreempt_enable();\n" + "> +\treturn ret;\n" + "> +}\n" + "> +EXPORT_SYMBOL(sgx_einit);\n" + "> +\n" + "> static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned\n" + "> long index,\n" + "> \t\t\t\t struct sgx_epc_bank *bank)\n" + "> {\n" + "> @@ -426,6 +487,15 @@ static __init int sgx_page_cache_init(void)\n" + "> \treturn 0;\n" + "> }\n" + "> \n" + "> +static int sgx_pm_notifier_cb(struct notifier_block *nb, unsigned\n" + "> long action,\n" + "> +\t\t\t void *data)\n" + "> +{\n" + "> +\tif (action == PM_SUSPEND_PREPARE || action ==\n" + "> PM_HIBERNATION_PREPARE)\n" + "> +\t\tsgx_pm_cnt++;\n" + "> +\n" + "> +\treturn NOTIFY_DONE;\n" + "> +}\n" + "> +\n" + "> static __init int sgx_init(void)\n" + "> {\n" + "> \tstruct task_struct *tsk;\n" + "> @@ -452,20 +522,30 @@ static __init int sgx_init(void)\n" + "> \tif (!(fc & FEATURE_CONTROL_SGX_LE_WR))\n" + "> \t\tpr_info(\"IA32_SGXLEPUBKEYHASHn MSRs are not\n" + "> writable\\n\");\n" + "> \n" + "> -\tret = sgx_page_cache_init();\n" + "> +\tsgx_pm_notifier.notifier_call = sgx_pm_notifier_cb;\n" + "> +\tret = register_pm_notifier(&sgx_pm_notifier);\n" + "> \tif (ret)\n" + "> \t\treturn ret;\n" + "> \n" + "> +\tret = sgx_page_cache_init();\n" + "> +\tif (ret)\n" + "> +\t\tgoto out_pm;\n" + "> +\n" + "> \ttsk = kthread_run(ksgxswapd, NULL, \"ksgxswapd\");\n" + "> \tif (IS_ERR(tsk)) {\n" + "> -\t\tsgx_page_cache_teardown();\n" + "> -\t\treturn PTR_ERR(tsk);\n" + "> +\t\tret = PTR_ERR(tsk);\n" + "> +\t\tgoto out_pcache;\n" + "> \t}\n" + "> \tksgxswapd_tsk = tsk;\n" + "> \n" + "> \tsgx_enabled = true;\n" + "> \tsgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);\n" + "> \treturn 0;\n" + "> +out_pcache:\n" + "> +\tsgx_page_cache_teardown();\n" + "\n" + "I don't think this particular 2 lines of code of 'out_pcache' case\n" + "should be in this patch?\n" + "\n" + "Thanks,\n" + "-Kai\n" + "\n" + "> +out_pm:\n" + "> +\tunregister_pm_notifier(&sgx_pm_notifier);\n" + "> +\treturn ret;\n" + "> }\n" + "> \n" + > arch_initcall(sgx_init); -5973786dea7c8ed305bcb60117580cb5edde4736aa6f407b30865c9cef00ccb0 +6efac09c2c5389002e713d9ad8ccb9b5720d3275093634dfaa8983f125312ca3
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