diff for duplicates of <1535646055.26689.10.camel@intel.com> diff --git a/a/content_digest b/N1/content_digest index 2fceef2..b5db983 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -26,7 +26,10 @@ Mike Kravetz <mike.kravetz@oracle.com> Nadav Amit <nadav.amit@gmail.com> Oleg Nesterov <oleg@redhat.com> - " Pavel Machek <pave>\0" + Pavel Machek <pavel@ucw.cz> + Peter Zijlstra <peterz@infradead.org> + ravi.v.shankar@intel.com + " vedvyas.shanbhogue@intel.com\0" "\00:1\0" "b\0" "On Thu, 2018-08-30 at 18:10 +0200, Jann Horn wrote:\n" @@ -75,4 +78,4 @@ "\n" Yu-cheng -ef9e1a4755da3b399192e54887d9ed7d39c7b5b88f613befb206a6c0c22d1221 +7c8e5d61f367b9c90ff9c083483e54e3c5cc4605cbee4da3e20ce1b87b0e5703
diff --git a/a/1.txt b/N2/1.txt index 1a1ed35..b97d6f4 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -5,7 +5,7 @@ On Thu, 2018-08-30 at 18:10 +0200, Jann Horn wrote: > > > > This patch adds basic shadow stack enabling/disabling routines. > > A task's shadow stack is allocated from memory with VM_SHSTK -> > flag set and read-only protection. The shadow stack is +> > flag set and read-only protection.A A The shadow stack is > > allocated to a fixed size of RLIMIT_STACK. > > > > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> @@ -13,18 +13,18 @@ On Thu, 2018-08-30 at 18:10 +0200, Jann Horn wrote: > > > > +static int set_shstk_ptr(unsigned long addr) > > +{ -> > + u64 r; +> > +A A A A A A A u64 r; > > + -> > + if (!cpu_feature_enabled(X86_FEATURE_SHSTK)) -> > + return -1; +> > +A A A A A A A if (!cpu_feature_enabled(X86_FEATURE_SHSTK)) +> > +A A A A A A A A A A A A A A A return -1; > > + -> > + if ((addr >= TASK_SIZE_MAX) || (!IS_ALIGNED(addr, 4))) -> > + return -1; +> > +A A A A A A A if ((addr >= TASK_SIZE_MAX) || (!IS_ALIGNED(addr, 4))) +> > +A A A A A A A A A A A A A A A return -1; > > + -> > + rdmsrl(MSR_IA32_U_CET, r); -> > + wrmsrl(MSR_IA32_PL3_SSP, addr); -> > + wrmsrl(MSR_IA32_U_CET, r | MSR_IA32_CET_SHSTK_EN); -> > + return 0; +> > +A A A A A A A rdmsrl(MSR_IA32_U_CET, r); +> > +A A A A A A A wrmsrl(MSR_IA32_PL3_SSP, addr); +> > +A A A A A A A wrmsrl(MSR_IA32_U_CET, r | MSR_IA32_CET_SHSTK_EN); +> > +A A A A A A A return 0; > > +} > Here's a really stupid question: Where is the logic for switching > those MSRs on task switch? MSR_IA32_PL3_SSP contains a userspace @@ -35,10 +35,10 @@ On Thu, 2018-08-30 at 18:10 +0200, Jann Horn wrote: > only > see set_shstk_ptr(), which is called from: > -> - cet_setup_shstk() (called from arch_setup_features(), which is +> A - cet_setup_shstk() (called from arch_setup_features(), which is > called from load_elf_binary()) -> - cet_restore_signal() (called on signal handler return) -> - cet_setup_signal() (called from signal handling code) +> A - cet_restore_signal() (called on signal handler return) +> A - cet_setup_signal() (called from signal handling code) The MSR is in the XSAVES buffer and switched by XSAVES/XRSTORS. diff --git a/a/content_digest b/N2/content_digest index 2fceef2..56700b4 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -26,7 +26,10 @@ Mike Kravetz <mike.kravetz@oracle.com> Nadav Amit <nadav.amit@gmail.com> Oleg Nesterov <oleg@redhat.com> - " Pavel Machek <pave>\0" + Pavel Machek <pavel@ucw.cz> + Peter Zijlstra <peterz@infradead.org> + ravi.v.shankar@intel.com + " vedvyas.shanbhogue@intel.com\0" "\00:1\0" "b\0" "On Thu, 2018-08-30 at 18:10 +0200, Jann Horn wrote:\n" @@ -36,7 +39,7 @@ "> > \n" "> > This patch adds basic shadow stack enabling/disabling routines.\n" "> > A task's shadow stack is allocated from memory with VM_SHSTK\n" - "> > flag set and read-only protection.\302\240\302\240The shadow stack is\n" + "> > flag set and read-only protection.A A The shadow stack is\n" "> > allocated to a fixed size of RLIMIT_STACK.\n" "> > \n" "> > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>\n" @@ -44,18 +47,18 @@ "> > \n" "> > +static int set_shstk_ptr(unsigned long addr)\n" "> > +{\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u64 r;\n" + "> > +A A A A A A A u64 r;\n" "> > +\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!cpu_feature_enabled(X86_FEATURE_SHSTK))\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -1;\n" + "> > +A A A A A A A if (!cpu_feature_enabled(X86_FEATURE_SHSTK))\n" + "> > +A A A A A A A A A A A A A A A return -1;\n" "> > +\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if ((addr >= TASK_SIZE_MAX) || (!IS_ALIGNED(addr, 4)))\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -1;\n" + "> > +A A A A A A A if ((addr >= TASK_SIZE_MAX) || (!IS_ALIGNED(addr, 4)))\n" + "> > +A A A A A A A A A A A A A A A return -1;\n" "> > +\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240rdmsrl(MSR_IA32_U_CET, r);\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240wrmsrl(MSR_IA32_PL3_SSP, addr);\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240wrmsrl(MSR_IA32_U_CET, r | MSR_IA32_CET_SHSTK_EN);\n" - "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" + "> > +A A A A A A A rdmsrl(MSR_IA32_U_CET, r);\n" + "> > +A A A A A A A wrmsrl(MSR_IA32_PL3_SSP, addr);\n" + "> > +A A A A A A A wrmsrl(MSR_IA32_U_CET, r | MSR_IA32_CET_SHSTK_EN);\n" + "> > +A A A A A A A return 0;\n" "> > +}\n" "> Here's a really stupid question: Where is the logic for switching\n" "> those MSRs on task switch? MSR_IA32_PL3_SSP contains a userspace\n" @@ -66,13 +69,13 @@ "> only\n" "> see set_shstk_ptr(), which is called from:\n" "> \n" - "> \302\240- cet_setup_shstk() (called from arch_setup_features(), which is\n" + "> A - cet_setup_shstk() (called from arch_setup_features(), which is\n" "> called from load_elf_binary())\n" - "> \302\240- cet_restore_signal() (called on signal handler return)\n" - "> \302\240- cet_setup_signal() (called from signal handling code)\n" + "> A - cet_restore_signal() (called on signal handler return)\n" + "> A - cet_setup_signal() (called from signal handling code)\n" "\n" "The MSR is in the XSAVES buffer and switched by XSAVES/XRSTORS.\n" "\n" Yu-cheng -ef9e1a4755da3b399192e54887d9ed7d39c7b5b88f613befb206a6c0c22d1221 +f944e404a99f9080e399da8e0b26813bd6edb7dceb7bf9bfa6ba6fbd49793535
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