From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v3 04/12] drm/mediatek: add clock factor for different IC Date: Fri, 21 Sep 2018 17:03:49 +0800 Message-ID: <1537520629.20660.3.camel@mtksdaap41> References: <20180921032822.30771-1-bibby.hsieh@mediatek.com> <20180921032822.30771-5-bibby.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180921032822.30771-5-bibby.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Bibby Hsieh Cc: linux-kernel@vger.kernel.org, Sascha Hauer , chunhui dai , David Airlie , Daniel Vetter , Cawa Cheng , dri-devel@lists.freedesktop.org, Mao Huang , Thierry Reding , linux-mediatek@lists.infradead.org, Matthias Brugger , Yingjoe Chen , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIEJpYmJ5OgoKT24gRnJpLCAyMDE4LTA5LTIxIGF0IDExOjI4ICswODAwLCBCaWJieSBIc2ll aCB3cm90ZToKPiBGcm9tOiBjaHVuaHVpIGRhaSA8Y2h1bmh1aS5kYWlAbWVkaWF0ZWsuY29tPgo+ IAo+IGRpZmZlcmVudCBJQyBoYXMgZGlmZmVyZW50IGNsb2NrIGRlc2lnbmVkIGluIEhETUksIHRo ZSBmYWN0b3IgZm9yCj4gY2FsY3VsYXRlIGNsb2NrIHNob3VsZCBiZSBkaWZmZXJlbnQuIFVzaW5u ZyB0aGUgZGF0YSBpbiBvZl9ub2RlCj4gdG8gZmluZCB0aGlzIGZhY3Rvci4KPiAKClJldmlld2Vk LWJ5OiBDSyBIdSA8Y2suaHVAbWVkaWF0ZWsuY29tPgoKPiBTaWduZWQtb2ZmLWJ5OiBjaHVuaHVp IGRhaSA8Y2h1bmh1aS5kYWlAbWVkaWF0ZWsuY29tPgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2RwaS5jIHwgMjQgKysrKysrKysrKysrKysrLS0tLS0tLS0tCj4gIDEgZmls ZSBjaGFuZ2VkLCAxNSBpbnNlcnRpb25zKCspLCA5IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1n aXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RwaS5jIGIvZHJpdmVycy9ncHUvZHJt L21lZGlhdGVrL210a19kcGkuYwo+IGluZGV4IDFlNzM2OWUwZDkxYy4uMDIyY2NlYzQ5Y2VhIDEw MDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHBpLmMKPiArKysgYi9k cml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RwaS5jCj4gQEAgLTEyMCw2ICsxMjAsNyBAQCBz dHJ1Y3QgbXRrX2RwaV95Y19saW1pdCB7Cj4gIH07Cj4gIAo+ICBzdHJ1Y3QgbXRrX2RwaV9jb25m IHsKPiArCXVuc2lnbmVkIGludCAoKmNhbF9mYWN0b3IpKGludCBjbG9jayk7Cj4gIAl1MzIgcmVn X2hfZnJlX2NvbjsKPiAgCWJvb2wgZWRnZV9zZWxfZW47Cj4gIH07Cj4gQEAgLTQ2MCwxNSArNDYx LDcgQEAgc3RhdGljIGludCBtdGtfZHBpX3NldF9kaXNwbGF5X21vZGUoc3RydWN0IG10a19kcGkg KmRwaSwKPiAgCXVuc2lnbmVkIGludCBmYWN0b3I7Cj4gIAo+ICAJLyogbGV0IHBsbF9yYXRlIGNh biBmaXggdGhlIHZhbGlkIHJhbmdlIG9mIHR2ZHBsbCAoMUd+MkdIeikgKi8KPiAtCj4gLQlpZiAo bW9kZS0+Y2xvY2sgPD0gMjcwMDApCj4gLQkJZmFjdG9yID0gMyA8PCA0Owo+IC0JZWxzZSBpZiAo bW9kZS0+Y2xvY2sgPD0gODQwMDApCj4gLQkJZmFjdG9yID0gMyA8PCAzOwo+IC0JZWxzZSBpZiAo bW9kZS0+Y2xvY2sgPD0gMTY3MDAwKQo+IC0JCWZhY3RvciA9IDMgPDwgMjsKPiAtCWVsc2UKPiAt CQlmYWN0b3IgPSAzIDw8IDE7Cj4gKwlmYWN0b3IgPSBkcGktPmNvbmYtPmNhbF9mYWN0b3IobW9k ZS0+Y2xvY2spOwo+ICAJZHJtX2Rpc3BsYXlfbW9kZV90b192aWRlb21vZGUobW9kZSwgJnZtKTsK PiAgCXBsbF9yYXRlID0gdm0ucGl4ZWxjbG9jayAqIGZhY3RvcjsKPiAgCj4gQEAgLTY4Miw3ICs2 NzUsMjAgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBjb21wb25lbnRfb3BzIG10a19kcGlfY29tcG9u ZW50X29wcyA9IHsKPiAgCS51bmJpbmQgPSBtdGtfZHBpX3VuYmluZCwKPiAgfTsKPiAgCj4gK3N0 YXRpYyB1bnNpZ25lZCBpbnQgbXQ4MTczX2NhbGN1bGF0ZV9mYWN0b3IoaW50IGNsb2NrKQo+ICt7 Cj4gKwlpZiAoY2xvY2sgPD0gMjcwMDApCj4gKwkJcmV0dXJuIDMgPDwgNDsKPiArCWVsc2UgaWYg KGNsb2NrIDw9IDg0MDAwKQo+ICsJCXJldHVybiAzIDw8IDM7Cj4gKwllbHNlIGlmIChjbG9jayA8 PSAxNjcwMDApCj4gKwkJcmV0dXJuIDMgPDwgMjsKPiArCWVsc2UKPiArCQlyZXR1cm4gMyA8PCAx Owo+ICt9Cj4gKwo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kcGlfY29uZiBtdDgxNzNfY29u ZiA9IHsKPiArCS5jYWxfZmFjdG9yID0gbXQ4MTczX2NhbGN1bGF0ZV9mYWN0b3IsCj4gIAkucmVn X2hfZnJlX2NvbiA9IDB4ZTAsCj4gIH07Cj4gIAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxp c3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: ck.hu@mediatek.com (CK Hu) Date: Fri, 21 Sep 2018 17:03:49 +0800 Subject: [PATCH v3 04/12] drm/mediatek: add clock factor for different IC In-Reply-To: <20180921032822.30771-5-bibby.hsieh@mediatek.com> References: <20180921032822.30771-1-bibby.hsieh@mediatek.com> <20180921032822.30771-5-bibby.hsieh@mediatek.com> Message-ID: <1537520629.20660.3.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Bibby: On Fri, 2018-09-21 at 11:28 +0800, Bibby Hsieh wrote: > From: chunhui dai > > different IC has different clock designed in HDMI, the factor for > calculate clock should be different. Usinng the data in of_node > to find this factor. > Reviewed-by: CK Hu > Signed-off-by: chunhui dai > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 24 +++++++++++++++--------- > 1 file changed, 15 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 1e7369e0d91c..022ccec49cea 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { > }; > > struct mtk_dpi_conf { > + unsigned int (*cal_factor)(int clock); > u32 reg_h_fre_con; > bool edge_sel_en; > }; > @@ -460,15 +461,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > unsigned int factor; > > /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ > - > - if (mode->clock <= 27000) > - factor = 3 << 4; > - else if (mode->clock <= 84000) > - factor = 3 << 3; > - else if (mode->clock <= 167000) > - factor = 3 << 2; > - else > - factor = 3 << 1; > + factor = dpi->conf->cal_factor(mode->clock); > drm_display_mode_to_videomode(mode, &vm); > pll_rate = vm.pixelclock * factor; > > @@ -682,7 +675,20 @@ static const struct component_ops mtk_dpi_component_ops = { > .unbind = mtk_dpi_unbind, > }; > > +static unsigned int mt8173_calculate_factor(int clock) > +{ > + if (clock <= 27000) > + return 3 << 4; > + else if (clock <= 84000) > + return 3 << 3; > + else if (clock <= 167000) > + return 3 << 2; > + else > + return 3 << 1; > +} > + > static const struct mtk_dpi_conf mt8173_conf = { > + .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > }; > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F64FECE562 for ; Fri, 21 Sep 2018 09:04:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A2B621523 for ; Fri, 21 Sep 2018 09:04:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1A2B621523 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389467AbeIUOvw (ORCPT ); Fri, 21 Sep 2018 10:51:52 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:52758 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389022AbeIUOvv (ORCPT ); Fri, 21 Sep 2018 10:51:51 -0400 X-UUID: 21d796796a664612a18823d1f99dea12-20180921 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 800977900; Fri, 21 Sep 2018 17:03:51 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Sep 2018 17:03:49 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Sep 2018 17:03:49 +0800 Message-ID: <1537520629.20660.3.camel@mtksdaap41> Subject: Re: [PATCH v3 04/12] drm/mediatek: add clock factor for different IC From: CK Hu To: Bibby Hsieh CC: David Airlie , Matthias Brugger , Daniel Vetter , , , Yingjoe Chen , Cawa Cheng , Daniel Kurtz , "Philipp Zabel" , YT Shen , "Thierry Reding" , Mao Huang , , , "Sascha Hauer" , chunhui dai Date: Fri, 21 Sep 2018 17:03:49 +0800 In-Reply-To: <20180921032822.30771-5-bibby.hsieh@mediatek.com> References: <20180921032822.30771-1-bibby.hsieh@mediatek.com> <20180921032822.30771-5-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bibby: On Fri, 2018-09-21 at 11:28 +0800, Bibby Hsieh wrote: > From: chunhui dai > > different IC has different clock designed in HDMI, the factor for > calculate clock should be different. Usinng the data in of_node > to find this factor. > Reviewed-by: CK Hu > Signed-off-by: chunhui dai > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 24 +++++++++++++++--------- > 1 file changed, 15 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 1e7369e0d91c..022ccec49cea 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { > }; > > struct mtk_dpi_conf { > + unsigned int (*cal_factor)(int clock); > u32 reg_h_fre_con; > bool edge_sel_en; > }; > @@ -460,15 +461,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > unsigned int factor; > > /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ > - > - if (mode->clock <= 27000) > - factor = 3 << 4; > - else if (mode->clock <= 84000) > - factor = 3 << 3; > - else if (mode->clock <= 167000) > - factor = 3 << 2; > - else > - factor = 3 << 1; > + factor = dpi->conf->cal_factor(mode->clock); > drm_display_mode_to_videomode(mode, &vm); > pll_rate = vm.pixelclock * factor; > > @@ -682,7 +675,20 @@ static const struct component_ops mtk_dpi_component_ops = { > .unbind = mtk_dpi_unbind, > }; > > +static unsigned int mt8173_calculate_factor(int clock) > +{ > + if (clock <= 27000) > + return 3 << 4; > + else if (clock <= 84000) > + return 3 << 3; > + else if (clock <= 167000) > + return 3 << 2; > + else > + return 3 << 1; > +} > + > static const struct mtk_dpi_conf mt8173_conf = { > + .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > }; >