From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeniy Paltsev To: "marek.vasut@gmail.com" , "linux-mtd@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , "linux-snps-arc@lists.infradead.org" , Alexey Brodkin , "boris.brezillon@bootlin.com" , Vineet Gupta , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "richard@nod.at" Subject: Re: [PATCH v2 1/2] mtd: spi-nor: Add support of sst26wf* flash ICs protection ops Date: Mon, 24 Sep 2018 09:55:49 +0000 Message-ID: <1537782946.4902.6.camel@synopsys.com> References: <20180910114628.19156-1-Eugeniy.Paltsev@synopsys.com> <20180910114628.19156-2-Eugeniy.Paltsev@synopsys.com> In-Reply-To: <20180910114628.19156-2-Eugeniy.Paltsev@synopsys.com> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-ID: <9B14D78872C8004AA1D3FB8D9737BA19@internal.synopsys.com> Content-Transfer-Encoding: base64 MIME-Version: 1.0 List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , SGkgTWFyZWssDQoNCk1heWJlIHlvdSBoYXZlIGFueSBjb21tZW50cyBvciByZW1hcmtzIGFib3V0 IHRoaXMgcGF0Y2g/IEFuZCBpZiB5b3UgZG9uJ3QgY291bGQgeW91IHBsZWFzZSBhcHBseSBpdC4N ClRoYW5rcyENCg0KT24gTW9uLCAyMDE4LTA5LTEwIGF0IDE0OjQ2ICswMzAwLCBFdWdlbml5IFBh bHRzZXYgd3JvdGU6DQo+IHNzdDI2d2YgZmxhc2ggc2VyaWVzIGJsb2NrIHByb3RlY3Rpb24gaW1w bGVtZW50YXRpb24gZGlmZmVycw0KPiBmcm9tIG90aGVyIFNTVCBzZXJpZXMsIHNvIGFkZCBzcGVj aWZpYyBpbXBsZW1lbnRhdGlvbg0KPiBmbGFzaF9sb2NrL2ZsYXNoX3VubG9jay9mbGFzaF9pc19s b2NrZWQgZnVuY3Rpb25zIGZvciBzc3QyNndmDQo+IGZsYXNoIElDcy4NCj4gDQo+IE5PVEU6DQo+ IHRoaXMgcGF0Y2ggaXMgYmFzaWNhbGx5IGZvbGxvd2luZyBtaW5lIHUtYm9vdCBjb21taXQgcG9y dDoNCj4gaHR0cDovL2dpdC5kZW54LmRlLz9wPXUtYm9vdC5naXQ7YT1jb21taXRkaWZmO2g9M2Q0 ZmVkODdhNWZhM2ZmZWRmNjRmZjI4MTFjZDk1YzVhYzQ1MDNhYw0KPiANCj4gU2lnbmVkLW9mZi1i eTogRXVnZW5peSBQYWx0c2V2IDxFdWdlbml5LlBhbHRzZXZAc3lub3BzeXMuY29tPg0KPiAtLS0N Cj4gQ2hhbmdlcyB2MS0+djI6DQo+ICAqIENoZWNrIHJldHVybiB2YWx1ZSBvZiB7cmVhZCB8IHdy aXRlfV9yZWcgY2FsbGJhY2tzLg0KPiANCj4gIGRyaXZlcnMvbXRkL3NwaS1ub3Ivc3BpLW5vci5j IHwgMTc3ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKw0KPiAgaW5j bHVkZS9saW51eC9tdGQvc3BpLW5vci5oICAgfCAgIDQgKw0KPiAgMiBmaWxlcyBjaGFuZ2VkLCAx ODEgaW5zZXJ0aW9ucygrKQ0KPiANCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbXRkL3NwaS1ub3Iv c3BpLW5vci5jIGIvZHJpdmVycy9tdGQvc3BpLW5vci9zcGktbm9yLmMNCj4gaW5kZXggZDljMzY4 YzQ0MTk0Li5kMGU3Yzg1YjYwMDIgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvbXRkL3NwaS1ub3Iv c3BpLW5vci5jDQo+ICsrKyBiL2RyaXZlcnMvbXRkL3NwaS1ub3Ivc3BpLW5vci5jDQo+IEBAIC01 OTgsNiArNTk4LDE3NyBAQCBzdGF0aWMgaW50IHdyaXRlX3NyX2FuZF9jaGVjayhzdHJ1Y3Qgc3Bp X25vciAqbm9yLCB1OCBzdGF0dXNfbmV3LCB1OCBtYXNrKQ0KPiAgCXJldHVybiAoKHJldCAmIG1h c2spICE9IChzdGF0dXNfbmV3ICYgbWFzaykpID8gLUVJTyA6IDA7DQo+ICB9DQo+ICANCj4gKy8q DQo+ICsgKiBzc3QyNndmMDE2L3NzdDI2d2YwMzIvc3N0MjZ3ZjA2NCBoYXZlIG5leHQgYmxvY2sg cHJvdGVjdGlvbjoNCj4gKyAqIDR4ICAgLSA4ICBLQnl0ZSBibG9ja3MgLSByZWFkICYgd3JpdGUg cHJvdGVjdGlvbiBiaXRzIC0gdXBwZXIgYWRkcmVzc2VzDQo+ICsgKiAxeCAgIC0gMzIgS0J5dGUg YmxvY2tzIC0gd3JpdGUgcHJvdGVjdGlvbiBiaXRzDQo+ICsgKiByZXN0IC0gNjQgS0J5dGUgYmxv Y2tzIC0gd3JpdGUgcHJvdGVjdGlvbiBiaXRzDQo+ICsgKiAxeCAgIC0gMzIgS0J5dGUgYmxvY2tz IC0gd3JpdGUgcHJvdGVjdGlvbiBiaXRzDQo+ICsgKiA0eCAgIC0gOCAgS0J5dGUgYmxvY2tzIC0g cmVhZCAmIHdyaXRlIHByb3RlY3Rpb24gYml0cyAtIGxvd2VyIGFkZHJlc3Nlcw0KPiArICoNCj4g KyAqIFdlJ2xsIHN1cHBvcnQgb25seSBwZXIgNjRrIGxvY2svdW5sb2NrIHNvIGxvd2VyIGFuZCB1 cHBlciA2NCBLQnl0ZSByZWdpb24NCj4gKyAqIHdpbGwgYmUgdHJlYXRlZCBhcyBzaW5nbGUgYmxv Y2suDQo+ICsgKi8NCj4gKyNkZWZpbmUgU1NUMjZfQlBSXzhLX05VTQkJNA0KPiArI2RlZmluZSBT U1QyNl9NQVhfQlBSX1JFR19MRU4JCSgxOCArIDEpDQo+ICsjZGVmaW5lIFNTVDI2X0JPVU5EX1JF R19TSVpFCQkoKDMyICsgU1NUMjZfQlBSXzhLX05VTSAqIDgpICogU1pfMUspDQo+ICsNCj4gK2Vu dW0gbG9ja19jdGwgew0KPiArCVNTVDI2X0NUTF9MT0NLLA0KPiArCVNTVDI2X0NUTF9VTkxPQ0ss DQo+ICsJU1NUMjZfQ1RMX0NIRUNLDQo+ICt9Ow0KPiArDQo+ICtzdGF0aWMgYm9vbCBzc3QyNl9w cm9jZXNzX2Jwcih1MzIgYnByX3NpemUsIHU4ICpjbWQsIHUzMiBiaXQsIGVudW0gbG9ja19jdGwg Y3RsKQ0KPiArew0KPiArCXN3aXRjaCAoY3RsKSB7DQo+ICsJY2FzZSBTU1QyNl9DVExfTE9DSzoN Cj4gKwkJY21kW2Jwcl9zaXplIC0gKGJpdCAvIDgpIC0gMV0gfD0gQklUKGJpdCAlIDgpOw0KPiAr CQlicmVhazsNCj4gKwljYXNlIFNTVDI2X0NUTF9VTkxPQ0s6DQo+ICsJCWNtZFticHJfc2l6ZSAt IChiaXQgLyA4KSAtIDFdICY9IH5CSVQoYml0ICUgOCk7DQo+ICsJCWJyZWFrOw0KPiArCWNhc2Ug U1NUMjZfQ1RMX0NIRUNLOg0KPiArCQlyZXR1cm4gISEoY21kW2Jwcl9zaXplIC0gKGJpdCAvIDgp IC0gMV0gJiBCSVQoYml0ICUgOCkpOw0KPiArCX0NCj4gKw0KPiArCXJldHVybiBmYWxzZTsNCj4g K30NCj4gKw0KPiArLyoNCj4gKyAqIExvY2ssIHVubG9jayBvciBjaGVjayBsb2NrIHN0YXR1cyBv ZiB0aGUgZmxhc2ggcmVnaW9uIG9mIHRoZSBmbGFzaCAoZGVwZW5kaW5nDQo+ICsgKiBvbiB0aGUg bG9ja19jdGwgdmFsdWUpDQo+ICsgKi8NCj4gK3N0YXRpYyBpbnQgc3N0MjZfbG9ja19jdGwoc3Ry dWN0IHNwaV9ub3IgKm5vciwgbG9mZl90IG9mcywgdWludDY0X3QgbGVuLCBlbnVtIGxvY2tfY3Rs IGN0bCkNCj4gK3sNCj4gKwlzdHJ1Y3QgbXRkX2luZm8gKm10ZCA9ICZub3ItPm10ZDsNCj4gKwl1 MzIgaSwgYnByX3B0ciwgcnB0cl82NGssIGxwdHJfNjRrLCBicHJfc2l6ZTsNCj4gKwlib29sIGxv d2VyXzY0ayA9IGZhbHNlLCB1cHBlcl82NGsgPSBmYWxzZTsNCj4gKwl1OCBicHJfYnVmZltTU1Qy Nl9NQVhfQlBSX1JFR19MRU5dID0ge307DQo+ICsJaW50IHJldDsNCj4gKw0KPiArCS8qIENoZWNr IGxlbmd0aCBhbmQgb2Zmc2V0IGZvciA2NGsgYWxpZ25tZW50ICovDQo+ICsJaWYgKChvZnMgJiAo U1pfNjRLIC0gMSkpIHx8IChsZW4gJiAoU1pfNjRLIC0gMSkpKSB7DQo+ICsJCWRldl9lcnIobm9y LT5kZXYsICJsZW5ndGggb3Igb2Zmc2V0IGlzIG5vdCA2NEtpQiBhbGxpZ2huZWRcbiIpOw0KPiAr CQlyZXR1cm4gLUVJTlZBTDsNCj4gKwl9DQo+ICsNCj4gKwlpZiAob2ZzICsgbGVuID4gbXRkLT5z aXplKSB7DQo+ICsJCWRldl9lcnIobm9yLT5kZXYsICJyYW5nZSBpcyBtb3JlIHRoYW4gZGV2aWNl IHNpemU6ICUjbGx4ICsgJSNsbHggPiAlI2xseFxuIiwNCj4gKwkJCW9mcywgbGVuLCBtdGQtPnNp emUpOw0KPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gKwl9DQo+ICsNCj4gKwkvKiBTU1QyNiBmYW1p bHkgaGFzIG9ubHkgMTYgTWJpdCwgMzIgTWJpdCBhbmQgNjQgTWJpdCBJQyAqLw0KPiArCWlmICht dGQtPnNpemUgIT0gU1pfMk0gJiYNCj4gKwkgICAgbXRkLT5zaXplICE9IFNaXzRNICYmDQo+ICsJ ICAgIG10ZC0+c2l6ZSAhPSBTWl84TSkNCj4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ICsNCj4gKwli cHJfc2l6ZSA9IDIgKyAobXRkLT5zaXplIC8gU1pfNjRLIC8gOCk7DQo+ICsNCj4gKwlyZXQgPSBu b3ItPnJlYWRfcmVnKG5vciwgU1BJTk9SX09QX1JFQURfQlBSLCBicHJfYnVmZiwgYnByX3NpemUp Ow0KPiArCWlmIChyZXQgPCAwKSB7DQo+ICsJCWRldl9lcnIobm9yLT5kZXYsICJmYWlsIHRvIHJl YWQgYmxvY2stcHJvdGVjdGlvbiByZWdpc3RlclxuIik7DQo+ICsJCXJldHVybiByZXQ7DQo+ICsJ fQ0KPiArDQo+ICsJcnB0cl82NGsgPSBtaW5fdCh1MzIsIG9mcyArIGxlbiwgbXRkLT5zaXplIC0g U1NUMjZfQk9VTkRfUkVHX1NJWkUpOw0KPiArCWxwdHJfNjRrID0gbWF4X3QodTMyLCBvZnMsIFNT VDI2X0JPVU5EX1JFR19TSVpFKTsNCj4gKw0KPiArCXVwcGVyXzY0ayA9ICgob2ZzICsgbGVuKSA+ IChtdGQtPnNpemUgLSBTU1QyNl9CT1VORF9SRUdfU0laRSkpOw0KPiArCWxvd2VyXzY0ayA9IChv ZnMgPCBTU1QyNl9CT1VORF9SRUdfU0laRSk7DQo+ICsNCj4gKwkvKiBMb3dlciBiaXRzIGluIGJs b2NrLXByb3RlY3Rpb24gcmVnaXN0ZXIgYXJlIGFib3V0IDY0ayByZWdpb24gKi8NCj4gKwlicHJf cHRyID0gbHB0cl82NGsgLyBTWl82NEsgLSAxOw0KPiArDQo+ICsJLyogUHJvY2VzcyA2NEsgYmxv Y2tzIHJlZ2lvbiAqLw0KPiArCXdoaWxlIChscHRyXzY0ayA8IHJwdHJfNjRrKSB7DQo+ICsJCWlm IChzc3QyNl9wcm9jZXNzX2JwcihicHJfc2l6ZSwgYnByX2J1ZmYsIGJwcl9wdHIsIGN0bCkpDQo+ ICsJCQlyZXR1cm4gRUFDQ0VTOw0KPiArDQo+ICsJCWJwcl9wdHIrKzsNCj4gKwkJbHB0cl82NGsg Kz0gU1pfNjRLOw0KPiArCX0NCj4gKw0KPiArCS8qIDMySyBhbmQgOEsgcmVnaW9uIGJpdHMgaW4g QlBSIGFyZSBhZnRlciA2NGsgcmVnaW9uIGJpdHMgKi8NCj4gKwlicHJfcHRyID0gKG10ZC0+c2l6 ZSAtIDIgKiBTU1QyNl9CT1VORF9SRUdfU0laRSkgLyBTWl82NEs7DQo+ICsNCj4gKwkvKiBQcm9j ZXNzIGxvd2VyIDMySyBibG9jayByZWdpb24gKi8NCj4gKwlpZiAobG93ZXJfNjRrKQ0KPiArCQlp ZiAoc3N0MjZfcHJvY2Vzc19icHIoYnByX3NpemUsIGJwcl9idWZmLCBicHJfcHRyLCBjdGwpKQ0K PiArCQkJcmV0dXJuIEVBQ0NFUzsNCj4gKw0KPiArCWJwcl9wdHIrKzsNCj4gKw0KPiArCS8qIFBy b2Nlc3MgdXBwZXIgMzJLIGJsb2NrIHJlZ2lvbiAqLw0KPiArCWlmICh1cHBlcl82NGspDQo+ICsJ CWlmIChzc3QyNl9wcm9jZXNzX2JwcihicHJfc2l6ZSwgYnByX2J1ZmYsIGJwcl9wdHIsIGN0bCkp DQo+ICsJCQlyZXR1cm4gRUFDQ0VTOw0KPiArDQo+ICsJYnByX3B0cisrOw0KPiArDQo+ICsJLyog UHJvY2VzcyBsb3dlciA4SyBibG9jayByZWdpb25zICovDQo+ICsJZm9yIChpID0gMDsgaSA8IFNT VDI2X0JQUl84S19OVU07IGkrKykgew0KPiArCQlpZiAobG93ZXJfNjRrKQ0KPiArCQkJaWYgKHNz dDI2X3Byb2Nlc3NfYnByKGJwcl9zaXplLCBicHJfYnVmZiwgYnByX3B0ciwgY3RsKSkNCj4gKwkJ CQlyZXR1cm4gRUFDQ0VTOw0KPiArDQo+ICsJCS8qIEluIDhLIGFyZWEgQlBSIGhhcyBib3RoIHJl YWQgYW5kIHdyaXRlIHByb3RlY3Rpb24gYml0cyAqLw0KPiArCQlicHJfcHRyICs9IDI7DQo+ICsJ fQ0KPiArDQo+ICsJLyogUHJvY2VzcyB1cHBlciA4SyBibG9jayByZWdpb25zICovDQo+ICsJZm9y IChpID0gMDsgaSA8IFNTVDI2X0JQUl84S19OVU07IGkrKykgew0KPiArCQlpZiAodXBwZXJfNjRr KQ0KPiArCQkJaWYgKHNzdDI2X3Byb2Nlc3NfYnByKGJwcl9zaXplLCBicHJfYnVmZiwgYnByX3B0 ciwgY3RsKSkNCj4gKwkJCQlyZXR1cm4gRUFDQ0VTOw0KPiArDQo+ICsJCS8qIEluIDhLIGFyZWEg QlBSIGhhcyBib3RoIHJlYWQgYW5kIHdyaXRlIHByb3RlY3Rpb24gYml0cyAqLw0KPiArCQlicHJf cHRyICs9IDI7DQo+ICsJfQ0KPiArDQo+ICsJLyogSWYgd2UgY2hlY2sgcmVnaW9uIHN0YXR1cyB3 ZSBkb24ndCBuZWVkIHRvIHdyaXRlIEJQUiBiYWNrICovDQo+ICsJaWYgKGN0bCA9PSBTU1QyNl9D VExfQ0hFQ0spDQo+ICsJCXJldHVybiAwOw0KPiArDQo+ICsJcmV0ID0gbm9yLT53cml0ZV9yZWco bm9yLCBTUElOT1JfT1BfV1JJVEVfQlBSLCBicHJfYnVmZiwgYnByX3NpemUpOw0KPiArCWlmIChy ZXQgPCAwKSB7DQo+ICsJCWRldl9lcnIobm9yLT5kZXYsICJmYWlsIHRvIHdyaXRlIGJsb2NrLXBy b3RlY3Rpb24gcmVnaXN0ZXJcbiIpOw0KPiArCQlyZXR1cm4gcmV0Ow0KPiArCX0NCj4gKw0KPiAr CXJldHVybiAwOw0KPiArfQ0KPiArDQo+ICtzdGF0aWMgaW50IHNzdDI2X3VubG9jayhzdHJ1Y3Qg c3BpX25vciAqbm9yLCBsb2ZmX3Qgb2ZzLCB1aW50NjRfdCBsZW4pDQo+ICt7DQo+ICsJcmV0dXJu IHNzdDI2X2xvY2tfY3RsKG5vciwgb2ZzLCBsZW4sIFNTVDI2X0NUTF9VTkxPQ0spOw0KPiArfQ0K PiArDQo+ICtzdGF0aWMgaW50IHNzdDI2X2xvY2soc3RydWN0IHNwaV9ub3IgKm5vciwgbG9mZl90 IG9mcywgdWludDY0X3QgbGVuKQ0KPiArew0KPiArCXJldHVybiBzc3QyNl9sb2NrX2N0bChub3Is IG9mcywgbGVuLCBTU1QyNl9DVExfTE9DSyk7DQo+ICt9DQo+ICsNCj4gKy8qDQo+ICsgKiBSZXR1 cm5zIEVBQ0NFUyAocG9zaXRpdmUgdmFsdWUpIGlmIHJlZ2lvbiBpcyBsb2NrZWQsIDAgaWYgcmVn aW9uIGlzIHVubG9ja2VkLA0KPiArICogYW5kIG5lZ2F0aXZlIG9uIGVycm9ycy4NCj4gKyAqLw0K PiArc3RhdGljIGludCBzc3QyNl9pc19sb2NrZWQoc3RydWN0IHNwaV9ub3IgKm5vciwgbG9mZl90 IG9mcywgdWludDY0X3QgbGVuKQ0KPiArew0KPiArCS8qDQo+ICsJICogaXNfbG9ja2VkIGZ1bmN0 aW9uIGlzIHVzZWQgZm9yIGNoZWNrIGJlZm9yZSByZWFkaW5nIG9yIGVyYXNpbmcgZmxhc2gNCj4g KwkgKiByZWdpb24sIHNvIG9mZnNldCBhbmQgbGVuZ3RoIG1pZ2h0IGJlIG5vdCA2NGsgYWxsaWdo bmVkLCBzbyBhZGp1c3QNCj4gKwkgKiB0aGVtIHRvIGJlIDY0ayBhbGxpZ2huZWQgYXMgc3N0MjZf bG9ja19jdGwgd29ya3Mgb25seSB3aXRoIDY0aw0KPiArCSAqIGFsbGlnaG5lZCByZWdpb25zLg0K PiArCSAqLw0KPiArCW9mcyAtPSBvZnMgJiAoU1pfNjRLIC0gMSk7DQo+ICsJbGVuID0gbGVuICYg KFNaXzY0SyAtIDEpID8gKGxlbiAmIH4oU1pfNjRLIC0gMSkpICsgU1pfNjRLIDogbGVuOw0KPiAr DQo+ICsJcmV0dXJuIHNzdDI2X2xvY2tfY3RsKG5vciwgb2ZzLCBsZW4sIFNTVDI2X0NUTF9DSEVD Syk7DQo+ICt9DQo+ICsNCj4gIHN0YXRpYyB2b2lkIHN0bV9nZXRfbG9ja2VkX3JhbmdlKHN0cnVj dCBzcGlfbm9yICpub3IsIHU4IHNyLCBsb2ZmX3QgKm9mcywNCj4gIAkJCQkgdWludDY0X3QgKmxl bikNCj4gIHsNCj4gQEAgLTI4NzIsNiArMzA0MywxMiBAQCBpbnQgc3BpX25vcl9zY2FuKHN0cnVj dCBzcGlfbm9yICpub3IsIGNvbnN0IGNoYXIgKm5hbWUsDQo+ICAJCW5vci0+Zmxhc2hfaXNfbG9j a2VkID0gc3RtX2lzX2xvY2tlZDsNCj4gIAl9DQo+ICANCj4gKwlpZiAoSkVERUNfTUZSKGluZm8p ID09IFNOT1JfTUZSX1NTVCAmJiBpbmZvLT5pZFsxXSA9PSAweDI2KSB7DQo+ICsJCW5vci0+Zmxh c2hfbG9jayA9IHNzdDI2X2xvY2s7DQo+ICsJCW5vci0+Zmxhc2hfdW5sb2NrID0gc3N0MjZfdW5s b2NrOw0KPiArCQlub3ItPmZsYXNoX2lzX2xvY2tlZCA9IHNzdDI2X2lzX2xvY2tlZDsNCj4gKwl9 DQo+ICsNCj4gIAlpZiAobm9yLT5mbGFzaF9sb2NrICYmIG5vci0+Zmxhc2hfdW5sb2NrICYmIG5v ci0+Zmxhc2hfaXNfbG9ja2VkKSB7DQo+ICAJCW10ZC0+X2xvY2sgPSBzcGlfbm9yX2xvY2s7DQo+ ICAJCW10ZC0+X3VubG9jayA9IHNwaV9ub3JfdW5sb2NrOw0KPiBkaWZmIC0tZ2l0IGEvaW5jbHVk ZS9saW51eC9tdGQvc3BpLW5vci5oIGIvaW5jbHVkZS9saW51eC9tdGQvc3BpLW5vci5oDQo+IGlu ZGV4IGU2MGRhMGQzNGNjMS4uMjQ2MDE0YTczZjgzIDEwMDY0NA0KPiAtLS0gYS9pbmNsdWRlL2xp bnV4L210ZC9zcGktbm9yLmgNCj4gKysrIGIvaW5jbHVkZS9saW51eC9tdGQvc3BpLW5vci5oDQo+ IEBAIC05Myw2ICs5MywxMCBAQA0KPiAgI2RlZmluZSBTUElOT1JfT1BfV1JESQkJMHgwNAkvKiBX cml0ZSBkaXNhYmxlICovDQo+ICAjZGVmaW5lIFNQSU5PUl9PUF9BQUlfV1AJMHhhZAkvKiBBdXRv IGFkZHJlc3MgaW5jcmVtZW50IHdvcmQgcHJvZ3JhbSAqLw0KPiAgDQo+ICsvKiBVc2VkIGZvciBT U1QyNiogZmxhc2hlcyBvbmx5LiAqLw0KPiArI2RlZmluZSBTUElOT1JfT1BfUkVBRF9CUFIJMHg3 MgkvKiBSZWFkIGJsb2NrIHByb3RlY3Rpb24gcmVnaXN0ZXIgKi8NCj4gKyNkZWZpbmUgU1BJTk9S X09QX1dSSVRFX0JQUgkweDQyCS8qIFdyaXRlIGJsb2NrIHByb3RlY3Rpb24gcmVnaXN0ZXIgKi8N Cj4gKw0KPiAgLyogVXNlZCBmb3IgUzNBTiBmbGFzaGVzIG9ubHkgKi8NCj4gICNkZWZpbmUgU1BJ Tk9SX09QX1hTRQkJMHg1MAkvKiBTZWN0b3IgZXJhc2UgKi8NCj4gICNkZWZpbmUgU1BJTk9SX09Q X1hQUAkJMHg4MgkvKiBQYWdlIHByb2dyYW0gKi8NCi0tIA0KIEV1Z2VuaXkgUGFsdHNldg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: eugeniy.paltsev@synopsys.com (Eugeniy Paltsev) Date: Mon, 24 Sep 2018 09:55:49 +0000 Subject: [PATCH v2 1/2] mtd: spi-nor: Add support of sst26wf* flash ICs protection ops In-Reply-To: <20180910114628.19156-2-Eugeniy.Paltsev@synopsys.com> References: <20180910114628.19156-1-Eugeniy.Paltsev@synopsys.com> <20180910114628.19156-2-Eugeniy.Paltsev@synopsys.com> List-ID: Message-ID: <1537782946.4902.6.camel@synopsys.com> To: linux-snps-arc@lists.infradead.org Hi Marek, Maybe you have any comments or remarks about this patch? And if you don't could you please apply it. Thanks! On Mon, 2018-09-10@14:46 +0300, Eugeniy Paltsev wrote: > sst26wf flash series block protection implementation differs > from other SST series, so add specific implementation > flash_lock/flash_unlock/flash_is_locked functions for sst26wf > flash ICs. > > NOTE: > this patch is basically following mine u-boot commit port: > http://git.denx.de/?p=u-boot.git;a=commitdiff;h=3d4fed87a5fa3ffedf64ff2811cd95c5ac4503ac > > Signed-off-by: Eugeniy Paltsev > --- > Changes v1->v2: > * Check return value of {read | write}_reg callbacks. > > drivers/mtd/spi-nor/spi-nor.c | 177 ++++++++++++++++++++++++++++++++++++++++++ > include/linux/mtd/spi-nor.h | 4 + > 2 files changed, 181 insertions(+) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index d9c368c44194..d0e7c85b6002 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -598,6 +598,177 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) > return ((ret & mask) != (status_new & mask)) ? -EIO : 0; > } > > +/* > + * sst26wf016/sst26wf032/sst26wf064 have next block protection: > + * 4x - 8 KByte blocks - read & write protection bits - upper addresses > + * 1x - 32 KByte blocks - write protection bits > + * rest - 64 KByte blocks - write protection bits > + * 1x - 32 KByte blocks - write protection bits > + * 4x - 8 KByte blocks - read & write protection bits - lower addresses > + * > + * We'll support only per 64k lock/unlock so lower and upper 64 KByte region > + * will be treated as single block. > + */ > +#define SST26_BPR_8K_NUM 4 > +#define SST26_MAX_BPR_REG_LEN (18 + 1) > +#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K) > + > +enum lock_ctl { > + SST26_CTL_LOCK, > + SST26_CTL_UNLOCK, > + SST26_CTL_CHECK > +}; > + > +static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) > +{ > + switch (ctl) { > + case SST26_CTL_LOCK: > + cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8); > + break; > + case SST26_CTL_UNLOCK: > + cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8); > + break; > + case SST26_CTL_CHECK: > + return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); > + } > + > + return false; > +} > + > +/* > + * Lock, unlock or check lock status of the flash region of the flash (depending > + * on the lock_ctl value) > + */ > +static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl) > +{ > + struct mtd_info *mtd = &nor->mtd; > + u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size; > + bool lower_64k = false, upper_64k = false; > + u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {}; > + int ret; > + > + /* Check length and offset for 64k alignment */ > + if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) { > + dev_err(nor->dev, "length or offset is not 64KiB allighned\n"); > + return -EINVAL; > + } > + > + if (ofs + len > mtd->size) { > + dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n", > + ofs, len, mtd->size); > + return -EINVAL; > + } > + > + /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */ > + if (mtd->size != SZ_2M && > + mtd->size != SZ_4M && > + mtd->size != SZ_8M) > + return -EINVAL; > + > + bpr_size = 2 + (mtd->size / SZ_64K / 8); > + > + ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size); > + if (ret < 0) { > + dev_err(nor->dev, "fail to read block-protection register\n"); > + return ret; > + } > + > + rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE); > + lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE); > + > + upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE)); > + lower_64k = (ofs < SST26_BOUND_REG_SIZE); > + > + /* Lower bits in block-protection register are about 64k region */ > + bpr_ptr = lptr_64k / SZ_64K - 1; > + > + /* Process 64K blocks region */ > + while (lptr_64k < rptr_64k) { > + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) > + return EACCES; > + > + bpr_ptr++; > + lptr_64k += SZ_64K; > + } > + > + /* 32K and 8K region bits in BPR are after 64k region bits */ > + bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K; > + > + /* Process lower 32K block region */ > + if (lower_64k) > + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) > + return EACCES; > + > + bpr_ptr++; > + > + /* Process upper 32K block region */ > + if (upper_64k) > + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) > + return EACCES; > + > + bpr_ptr++; > + > + /* Process lower 8K block regions */ > + for (i = 0; i < SST26_BPR_8K_NUM; i++) { > + if (lower_64k) > + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) > + return EACCES; > + > + /* In 8K area BPR has both read and write protection bits */ > + bpr_ptr += 2; > + } > + > + /* Process upper 8K block regions */ > + for (i = 0; i < SST26_BPR_8K_NUM; i++) { > + if (upper_64k) > + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) > + return EACCES; > + > + /* In 8K area BPR has both read and write protection bits */ > + bpr_ptr += 2; > + } > + > + /* If we check region status we don't need to write BPR back */ > + if (ctl == SST26_CTL_CHECK) > + return 0; > + > + ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size); > + if (ret < 0) { > + dev_err(nor->dev, "fail to write block-protection register\n"); > + return ret; > + } > + > + return 0; > +} > + > +static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) > +{ > + return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK); > +} > + > +static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) > +{ > + return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK); > +} > + > +/* > + * Returns EACCES (positive value) if region is locked, 0 if region is unlocked, > + * and negative on errors. > + */ > +static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) > +{ > + /* > + * is_locked function is used for check before reading or erasing flash > + * region, so offset and length might be not 64k allighned, so adjust > + * them to be 64k allighned as sst26_lock_ctl works only with 64k > + * allighned regions. > + */ > + ofs -= ofs & (SZ_64K - 1); > + len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; > + > + return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK); > +} > + > static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, > uint64_t *len) > { > @@ -2872,6 +3043,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, > nor->flash_is_locked = stm_is_locked; > } > > + if (JEDEC_MFR(info) == SNOR_MFR_SST && info->id[1] == 0x26) { > + nor->flash_lock = sst26_lock; > + nor->flash_unlock = sst26_unlock; > + nor->flash_is_locked = sst26_is_locked; > + } > + > if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { > mtd->_lock = spi_nor_lock; > mtd->_unlock = spi_nor_unlock; > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index e60da0d34cc1..246014a73f83 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -93,6 +93,10 @@ > #define SPINOR_OP_WRDI 0x04 /* Write disable */ > #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ > > +/* Used for SST26* flashes only. */ > +#define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */ > +#define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */ > + > /* Used for S3AN flashes only */ > #define SPINOR_OP_XSE 0x50 /* Sector erase */ > #define SPINOR_OP_XPP 0x82 /* Page program */ -- Eugeniy Paltsev