diff for duplicates of <1537954592.18381.2.camel@mtkswgap22> diff --git a/a/1.txt b/N1/1.txt index d256045..81eda50 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -45,7 +45,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > clock-names = "spi", "wrap"; > > }; > > -> > + mipi_tx0: mipi-dphy@10010000 { +> > + mipi_tx0: mipi-dphy at 10010000 { > > + compatible = "mediatek,mt7623-mipi-tx", > > + "mediatek,mt2701-mipi-tx"; > > + reg = <0 0x10010000 0 0x90>; @@ -55,7 +55,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + #phy-cells = <0>; > > + }; > > + -> > + cec: cec@10012000 { +> > + cec: cec at 10012000 { > > + compatible = "mediatek,mt7623-cec", > > + "mediatek,mt8173-cec"; > > + reg = <0 0x10012000 0 0xbc>; @@ -64,14 +64,14 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "disabled"; > > + }; > > + -> > cir: cir@10013000 { +> > cir: cir at 10013000 { > > compatible = "mediatek,mt7623-cir"; > > reg = <0 0x10013000 0 0x1000>; > > @@ -359,6 +383,18 @@ > > #clock-cells = <1>; > > }; > > -> > + hdmi_phy: phy@10209100 { +> > + hdmi_phy: phy at 10209100 { > > + compatible = "mediatek,mt7623-hdmi-phy", > > + "mediatek,mt2701-hdmi-phy"; > > + reg = <0 0x10209100 0 0x24>; @@ -83,14 +83,14 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "disabled"; > > + }; > > + -> > rng: rng@1020f000 { +> > rng: rng at 1020f000 { > > compatible = "mediatek,mt7623-rng"; > > reg = <0 0x1020f000 0 0x1000>; > > @@ -558,6 +594,16 @@ > > status = "disabled"; > > }; > > -> > + hdmiddc0: i2c@11013000 { +> > + hdmiddc0: i2c at 11013000 { > > + compatible = "mediatek,mt7623-hdmi-ddc", > > + "mediatek,mt8173-hdmi-ddc"; > > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; @@ -100,21 +100,21 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "disabled"; > > + }; > > + -> > nor_flash: spi@11014000 { +> > nor_flash: spi at 11014000 { > > compatible = "mediatek,mt7623-nor", > > "mediatek,mt8173-nor"; > > @@ -732,6 +778,84 @@ > > #clock-cells = <1>; > > }; > > -> > + display_components: dispsys@14000000 { +> > + display_components: dispsys at 14000000 { > > + compatible = "mediatek,mt7623-mmsys", > > + "mediatek,mt2701-mmsys"; > > + reg = <0 0x14000000 0 0x1000>; > > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > > + }; > > + -> > + ovl@14007000 { +> > + ovl at 14007000 { > > + compatible = "mediatek,mt7623-disp-ovl", > > + "mediatek,mt2701-disp-ovl"; > > + reg = <0 0x14007000 0 0x1000>; @@ -124,7 +124,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + mediatek,larb = <&larb0>; > > + }; > > + -> > + rdma0: rdma@14008000 { +> > + rdma0: rdma at 14008000 { > > + compatible = "mediatek,mt7623-disp-rdma", > > + "mediatek,mt2701-disp-rdma"; > > + reg = <0 0x14008000 0 0x1000>; @@ -134,7 +134,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + mediatek,larb = <&larb0>; > > + }; > > + -> > + wdma@14009000 { +> > + wdma at 14009000 { > > + compatible = "mediatek,mt7623-disp-wdma", > > + "mediatek,mt2701-disp-wdma"; > > + reg = <0 0x14009000 0 0x1000>; @@ -144,7 +144,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + mediatek,larb = <&larb0>; > > + }; > > + -> > + bls: pwm@1400a000 { +> > + bls: pwm at 1400a000 { > > + compatible = "mediatek,mt7623-disp-pwm", > > + "mediatek,mt2701-disp-pwm"; > > + reg = <0 0x1400a000 0 0x1000>; @@ -155,7 +155,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "disabled"; > > + }; > > + -> > + color@1400b000 { +> > + color at 1400b000 { > > + compatible = "mediatek,mt7623-disp-color", > > + "mediatek,mt2701-disp-color"; > > + reg = <0 0x1400b000 0 0x1000>; @@ -163,7 +163,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + clocks = <&mmsys CLK_MM_DISP_COLOR>; > > + }; > > + -> > + dsi: dsi@1400c000 { +> > + dsi: dsi at 1400c000 { > > + compatible = "mediatek,mt7623-dsi", > > + "mediatek,mt2701-dsi"; > > + reg = <0 0x1400c000 0 0x1000>; @@ -177,7 +177,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "disabled"; > > + }; > > + -> > + mutex: mutex@1400e000 { +> > + mutex: mutex at 1400e000 { > > + compatible = "mediatek,mt7623-disp-mutex", > > + "mediatek,mt2701-disp-mutex"; > > + reg = <0 0x1400e000 0 0x1000>; @@ -185,14 +185,14 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + clocks = <&mmsys CLK_MM_MUTEX_32K>; > > + }; > > + -> > larb0: larb@14010000 { +> > larb0: larb at 14010000 { > > compatible = "mediatek,mt7623-smi-larb", > > "mediatek,mt2701-smi-larb"; > > @@ -744,6 +868,44 @@ > > power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > > }; > > -> > + rdma1: rdma@14012000 { +> > + rdma1: rdma at 14012000 { > > + compatible = "mediatek,mt7623-disp-rdma", > > + "mediatek,mt2701-disp-rdma"; > > + reg = <0 0x14012000 0 0x1000>; @@ -202,7 +202,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + mediatek,larb = <&larb0>; > > + }; > > + -> > + dpi0: dpi@14014000 { +> > + dpi0: dpi at 14014000 { > > + compatible = "mediatek,mt7623-dpi", > > + "mediatek,mt2701-dpi"; > > + reg = <0 0x14014000 0 0x1000>; @@ -214,7 +214,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "disabled"; > > + }; > > + -> > + hdmi0: hdmi@14015000 { +> > + hdmi0: hdmi at 14015000 { > > + compatible = "mediatek,mt7623-hdmi", > > + "mediatek,mt8173-hdmi"; > > + reg = <0 0x14015000 0 0x400>; @@ -230,7 +230,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "disabled"; > > + }; > > + -> > imgsys: syscon@15000000 { +> > imgsys: syscon at 15000000 { > > compatible = "mediatek,mt7623-imgsys", > > "mediatek,mt2701-imgsys", > > @@ -1071,6 +1233,21 @@ @@ -277,7 +277,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + }; > > + > > cpus { -> > cpu@0 { +> > cpu at 0 { > > proc-supply = <&mt6323_vproc_reg>; > > @@ -114,10 +127,24 @@ > > }; @@ -312,14 +312,14 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + status = "okay"; > > + > > + ports { -> > + port@0 { +> > + port at 0 { > > + reg = <0>; > > + dpi0_out: endpoint { > > + remote-endpoint = <&hdmi0_in>; > > + }; > > + }; > > + -> > + port@1 { +> > + port at 1 { > > + reg = <1>; > > + dpi0_in: endpoint { > > + remote-endpoint = <&bls_out>; @@ -347,14 +347,14 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; -> > + port@0 { +> > + port at 0 { > > + reg = <0>; > > + hdmi0_in: endpoint { > > + remote-endpoint = <&dpi0_out>; > > + }; > > + }; > > + -> > + port@1 { +> > + port at 1 { > > + reg = <1>; > > + hdmi0_out: endpoint { > > + remote-endpoint = <&hdmi_connector_in>; @@ -400,7 +400,7 @@ On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote: > > + }; > > + > > cpus { -> > cpu@0 { +> > cpu at 0 { > > proc-supply = <&mt6323_vproc_reg>; > > @@ -106,10 +119,24 @@ > > }; diff --git a/a/content_digest b/N1/content_digest index c7c1d37..7b34302 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,10 @@ "ref\084011aa94dd7be9239b7a2f944dd30fc70568fbb.1536155449.git.ryder.lee@mediatek.com\0" "ref\07105c341de3525761ad4067ca57c641c7097f773.1536155449.git.ryder.lee@mediatek.com\0" "ref\01537953603.20272.4.camel@mtksdaap41\0" - "From\0Ryder Lee <ryder.lee@mediatek.com>\0" - "Subject\0Re: [Resend PATCH 5/5] arm: dts: mt7623: add display subsystem related device nodes\0" + "From\0ryder.lee@mediatek.com (Ryder Lee)\0" + "Subject\0[Resend PATCH 5/5] arm: dts: mt7623: add display subsystem related device nodes\0" "Date\0Wed, 26 Sep 2018 17:36:32 +0800\0" - "To\0CK Hu <ck.hu@mediatek.com>\0" - "Cc\0Matthias Brugger <matthias.bgg@gmail.com>" - Rob Herring <robh+dt@kernel.org> - Sean Wang <sean.wang@mediatek.com> - Roy Luo <cheng-hao.luo@mediatek.com> - Weijie Gao <weijie.gao@mediatek.com> - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-mediatek@lists.infradead.org - chunhui dai <chunhui.dai@mediatek.com> - " Bibby Hsieh <bibby.hsieh@mediatek.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote:\n" @@ -65,7 +54,7 @@ "> > \t\tclock-names = \"spi\", \"wrap\";\n" "> > \t};\n" "> > \n" - "> > +\tmipi_tx0: mipi-dphy@10010000 {\n" + "> > +\tmipi_tx0: mipi-dphy at 10010000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-mipi-tx\",\n" "> > +\t\t\t \"mediatek,mt2701-mipi-tx\";\n" "> > +\t\treg = <0 0x10010000 0 0x90>;\n" @@ -75,7 +64,7 @@ "> > +\t\t#phy-cells = <0>;\n" "> > +\t};\n" "> > +\n" - "> > +\tcec: cec@10012000 {\n" + "> > +\tcec: cec at 10012000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-cec\",\n" "> > +\t\t\t \"mediatek,mt8173-cec\";\n" "> > +\t\treg = <0 0x10012000 0 0xbc>;\n" @@ -84,14 +73,14 @@ "> > +\t\tstatus = \"disabled\";\n" "> > +\t};\n" "> > +\n" - "> > \tcir: cir@10013000 {\n" + "> > \tcir: cir at 10013000 {\n" "> > \t\tcompatible = \"mediatek,mt7623-cir\";\n" "> > \t\treg = <0 0x10013000 0 0x1000>;\n" "> > @@ -359,6 +383,18 @@\n" "> > \t\t#clock-cells = <1>;\n" "> > \t};\n" "> > \n" - "> > +\thdmi_phy: phy@10209100 {\n" + "> > +\thdmi_phy: phy at 10209100 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-hdmi-phy\",\n" "> > +\t\t\t \"mediatek,mt2701-hdmi-phy\";\n" "> > +\t\treg = <0 0x10209100 0 0x24>;\n" @@ -103,14 +92,14 @@ "> > +\t\tstatus = \"disabled\";\n" "> > +\t};\n" "> > +\n" - "> > \trng: rng@1020f000 {\n" + "> > \trng: rng at 1020f000 {\n" "> > \t\tcompatible = \"mediatek,mt7623-rng\";\n" "> > \t\treg = <0 0x1020f000 0 0x1000>;\n" "> > @@ -558,6 +594,16 @@\n" "> > \t\tstatus = \"disabled\";\n" "> > \t};\n" "> > \n" - "> > +\thdmiddc0: i2c@11013000 {\n" + "> > +\thdmiddc0: i2c at 11013000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-hdmi-ddc\",\n" "> > +\t\t\t \"mediatek,mt8173-hdmi-ddc\";\n" "> > +\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;\n" @@ -120,21 +109,21 @@ "> > +\t\tstatus = \"disabled\";\n" "> > +\t};\n" "> > +\n" - "> > \tnor_flash: spi@11014000 {\n" + "> > \tnor_flash: spi at 11014000 {\n" "> > \t\tcompatible = \"mediatek,mt7623-nor\",\n" "> > \t\t\t \"mediatek,mt8173-nor\";\n" "> > @@ -732,6 +778,84 @@\n" "> > \t\t#clock-cells = <1>;\n" "> > \t};\n" "> > \n" - "> > +\tdisplay_components: dispsys@14000000 {\n" + "> > +\tdisplay_components: dispsys at 14000000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-mmsys\",\n" "> > +\t\t\t \"mediatek,mt2701-mmsys\";\n" "> > +\t\treg = <0 0x14000000 0 0x1000>;\n" "> > +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n" "> > +\t};\n" "> > +\n" - "> > +\tovl@14007000 {\n" + "> > +\tovl at 14007000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-disp-ovl\",\n" "> > +\t\t\t \"mediatek,mt2701-disp-ovl\";\n" "> > +\t\treg = <0 0x14007000 0 0x1000>;\n" @@ -144,7 +133,7 @@ "> > +\t\tmediatek,larb = <&larb0>;\n" "> > +\t};\n" "> > +\n" - "> > +\trdma0: rdma@14008000 {\n" + "> > +\trdma0: rdma at 14008000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-disp-rdma\",\n" "> > +\t\t\t \"mediatek,mt2701-disp-rdma\";\n" "> > +\t\treg = <0 0x14008000 0 0x1000>;\n" @@ -154,7 +143,7 @@ "> > +\t\tmediatek,larb = <&larb0>;\n" "> > +\t};\n" "> > +\n" - "> > +\twdma@14009000 {\n" + "> > +\twdma at 14009000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-disp-wdma\",\n" "> > +\t\t\t \"mediatek,mt2701-disp-wdma\";\n" "> > +\t\treg = <0 0x14009000 0 0x1000>;\n" @@ -164,7 +153,7 @@ "> > +\t\tmediatek,larb = <&larb0>;\n" "> > +\t};\n" "> > +\n" - "> > +\tbls: pwm@1400a000 {\n" + "> > +\tbls: pwm at 1400a000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-disp-pwm\",\n" "> > +\t\t\t \"mediatek,mt2701-disp-pwm\";\n" "> > +\t\treg = <0 0x1400a000 0 0x1000>;\n" @@ -175,7 +164,7 @@ "> > +\t\tstatus = \"disabled\";\n" "> > +\t};\n" "> > +\n" - "> > +\tcolor@1400b000 {\n" + "> > +\tcolor at 1400b000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-disp-color\",\n" "> > +\t\t\t \"mediatek,mt2701-disp-color\";\n" "> > +\t\treg = <0 0x1400b000 0 0x1000>;\n" @@ -183,7 +172,7 @@ "> > +\t\tclocks = <&mmsys CLK_MM_DISP_COLOR>;\n" "> > +\t};\n" "> > +\n" - "> > +\tdsi: dsi@1400c000 {\n" + "> > +\tdsi: dsi at 1400c000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-dsi\",\n" "> > +\t\t\t \"mediatek,mt2701-dsi\";\n" "> > +\t\treg = <0 0x1400c000 0 0x1000>;\n" @@ -197,7 +186,7 @@ "> > +\t\tstatus = \"disabled\";\n" "> > +\t};\n" "> > +\n" - "> > +\tmutex: mutex@1400e000 {\n" + "> > +\tmutex: mutex at 1400e000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-disp-mutex\",\n" "> > +\t\t\t \"mediatek,mt2701-disp-mutex\";\n" "> > +\t\treg = <0 0x1400e000 0 0x1000>;\n" @@ -205,14 +194,14 @@ "> > +\t\tclocks = <&mmsys CLK_MM_MUTEX_32K>;\n" "> > +\t};\n" "> > +\n" - "> > \tlarb0: larb@14010000 {\n" + "> > \tlarb0: larb at 14010000 {\n" "> > \t\tcompatible = \"mediatek,mt7623-smi-larb\",\n" "> > \t\t\t \"mediatek,mt2701-smi-larb\";\n" "> > @@ -744,6 +868,44 @@\n" "> > \t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n" "> > \t};\n" "> > \n" - "> > +\trdma1: rdma@14012000 {\n" + "> > +\trdma1: rdma at 14012000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-disp-rdma\",\n" "> > +\t\t\t \"mediatek,mt2701-disp-rdma\";\n" "> > +\t\treg = <0 0x14012000 0 0x1000>;\n" @@ -222,7 +211,7 @@ "> > +\t\tmediatek,larb = <&larb0>;\n" "> > +\t};\n" "> > +\n" - "> > +\tdpi0: dpi@14014000 {\n" + "> > +\tdpi0: dpi at 14014000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-dpi\",\n" "> > +\t\t\t \"mediatek,mt2701-dpi\";\n" "> > +\t\treg = <0 0x14014000 0 0x1000>;\n" @@ -234,7 +223,7 @@ "> > +\t\tstatus = \"disabled\";\n" "> > +\t};\n" "> > +\n" - "> > +\thdmi0: hdmi@14015000 {\n" + "> > +\thdmi0: hdmi at 14015000 {\n" "> > +\t\tcompatible = \"mediatek,mt7623-hdmi\",\n" "> > +\t\t\t \"mediatek,mt8173-hdmi\";\n" "> > +\t\treg = <0 0x14015000 0 0x400>;\n" @@ -250,7 +239,7 @@ "> > +\t\tstatus = \"disabled\";\n" "> > +\t};\n" "> > +\n" - "> > \timgsys: syscon@15000000 {\n" + "> > \timgsys: syscon at 15000000 {\n" "> > \t\tcompatible = \"mediatek,mt7623-imgsys\",\n" "> > \t\t\t \"mediatek,mt2701-imgsys\",\n" "> > @@ -1071,6 +1233,21 @@\n" @@ -297,7 +286,7 @@ "> > +\t};\n" "> > +\n" "> > \tcpus {\n" - "> > \t\tcpu@0 {\n" + "> > \t\tcpu at 0 {\n" "> > \t\t\tproc-supply = <&mt6323_vproc_reg>;\n" "> > @@ -114,10 +127,24 @@\n" "> > \t};\n" @@ -332,14 +321,14 @@ "> > +\tstatus = \"okay\";\n" "> > +\n" "> > +\tports {\n" - "> > +\t\tport@0 {\n" + "> > +\t\tport at 0 {\n" "> > +\t\t\treg = <0>;\n" "> > +\t\t\tdpi0_out: endpoint {\n" "> > +\t\t\t\tremote-endpoint = <&hdmi0_in>;\n" "> > +\t\t\t};\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tport@1 {\n" + "> > +\t\tport at 1 {\n" "> > +\t\t\treg = <1>;\n" "> > +\t\t\tdpi0_in: endpoint {\n" "> > +\t\t\t\tremote-endpoint = <&bls_out>;\n" @@ -367,14 +356,14 @@ "> > +\tports {\n" "> > +\t\t#address-cells = <1>;\n" "> > +\t\t#size-cells = <0>;\n" - "> > +\t\tport@0 {\n" + "> > +\t\tport at 0 {\n" "> > +\t\t\treg = <0>;\n" "> > +\t\t\thdmi0_in: endpoint {\n" "> > +\t\t\t\tremote-endpoint = <&dpi0_out>;\n" "> > +\t\t\t};\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tport@1 {\n" + "> > +\t\tport at 1 {\n" "> > +\t\t\treg = <1>;\n" "> > +\t\t\thdmi0_out: endpoint {\n" "> > +\t\t\t\tremote-endpoint = <&hdmi_connector_in>;\n" @@ -420,7 +409,7 @@ "> > +\t};\n" "> > +\n" "> > \tcpus {\n" - "> > \t\tcpu@0 {\n" + "> > \t\tcpu at 0 {\n" "> > \t\t\tproc-supply = <&mt6323_vproc_reg>;\n" "> > @@ -106,10 +119,24 @@\n" "> > \t};\n" @@ -446,4 +435,4 @@ "\n" Ryder -36ab678a600b154206efb7ca704d002bd6e9d6aea43b14e2d54a9d1d6b1a5345 +d0d8b8a9df48becb82395e555120a777f6a6eae692a7de8a9bbcb0a418e8fd19
diff --git a/a/content_digest b/N2/content_digest index c7c1d37..de1b274 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -10,10 +10,10 @@ Sean Wang <sean.wang@mediatek.com> Roy Luo <cheng-hao.luo@mediatek.com> Weijie Gao <weijie.gao@mediatek.com> - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-mediatek@lists.infradead.org + <devicetree@vger.kernel.org> + <linux-kernel@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-mediatek@lists.infradead.org> chunhui dai <chunhui.dai@mediatek.com> " Bibby Hsieh <bibby.hsieh@mediatek.com>\0" "\00:1\0" @@ -446,4 +446,4 @@ "\n" Ryder -36ab678a600b154206efb7ca704d002bd6e9d6aea43b14e2d54a9d1d6b1a5345 +4468f1f0e4f5d9744e2b9e0065f34b7d112ed5abefe43ae64c63616098e64efe
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