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From: Trent Piepho <tpiepho@impinj.com>
To: "marc.zyngier@arm.com" <marc.zyngier@arm.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>
Cc: "faiz_abbas@ti.com" <faiz_abbas@ti.com>,
	"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"vigneshr@ti.com" <vigneshr@ti.com>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"joao.pinto@synopsys.com" <joao.pinto@synopsys.com>
Subject: Re: [PATCH] PCI: dwc: Fix interrupt race in when handling MSI
Date: Wed, 7 Nov 2018 18:32:31 +0000	[thread overview]
Message-ID: <1541615551.30311.286.camel@impinj.com> (raw)
In-Reply-To: <725afc4a-ec19-e4e6-7091-f499bfb63652@synopsys.com>

On Wed, 2018-11-07 at 12:57 +0000, Gustavo Pimentel wrote:
> On 06/11/2018 16:00, Marc Zyngier wrote:
> > On 06/11/18 14:53, Lorenzo Pieralisi wrote:
> > > On Sat, Oct 27, 2018 at 12:00:57AM +0000, Trent Piepho wrote:
> > > > 
> > > > This gives the following race scenario:
> > > > 
> > > > 1.  An MSI is received by, and the status bit for the MSI is set in, the
> > > > DWC PCI-e controller.
> > > > 2.  dw_handle_msi_irq() calls a driver's registered interrupt handler
> > > > for the MSI received.
> > > > 3.  At some point, the interrupt handler must decide, correctly, that
> > > > there is no more work to do and return.
> > > > 4.  The hardware generates a new MSI.  As the MSI's status bit is still
> > > > set, this new MSI is ignored.
> > > > 6.  dw_handle_msi_irq() unsets the MSI status bit.
> > > > 
> > > > The MSI received at point 4 will never be acted upon.  It occurred after
> > > > the driver had finished checking the hardware status for interrupt
> > > > conditions to act on.  Since the MSI status was masked, it does not
> > > > generated a new IRQ, neither when it was received nor when the MSI is
> > > > unmasked.
> > > > 

> This status register indicates whether exists or not a MSI interrupt on that
> controller [0..7] to be handle.

While the status for an MSI is set, no new interrupt will be triggered
if another identical MSI is received, correct?

> In theory, we should clear the interrupt flag only after the interrupt has
> actually handled (which can take some time to process on the worst case scenario).

But see above, there is a race if a new MSI arrives while still masked.
 I can see no possible way to solve this in software that does not
involve unmasking the MSI before calling the handler.  To leave the
interrupt masked while calling the handler requires the hardware to
queue an interrupt that arrives while masked.  We have no docs, but the
designware controller doesn't appear to do this in practice.

> However, the Trent's patch allows to acknowledge the flag and handle the
> interrupt later, giving the opportunity to catch a possible new interrupt, which
> will be handle by a new call of this function.
> 
> > 
> > What I'm interested in is the relationship this has with the mask/unmask
> > callbacks, and whether masking the interrupt before acking it would help.
> 
> Although there is the possibility of mask/unmask the interruptions on the
> controller, from what I've seen typically in other dw drivers this is not done.
> Probably we don't get much benefit from using it.
> 
> Gustavo
> 
> > 
> > Gustavo, can you help here?
> > 
> > In any way, moving the action of acknowledging the interrupt to its
> > right spot in the kernel (dw_pci_bottom_ack) would be a good start.
> > 
> > Thanks,
> > 
> > 	M.
> > 
> 
> 

  reply	other threads:[~2018-11-07 18:32 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-27  0:00 [PATCH] PCI: dwc: Fix interrupt race in when handling MSI Trent Piepho
2018-11-05 10:28 ` Vignesh R
2018-11-05 12:08 ` Gustavo Pimentel
2018-11-06 14:53 ` Lorenzo Pieralisi
2018-11-06 16:00   ` Marc Zyngier
2018-11-06 19:40     ` Trent Piepho
2018-11-07 11:07       ` Lorenzo Pieralisi
2018-11-07 12:58         ` Gustavo Pimentel
2018-11-07 18:41       ` Marc Zyngier
2018-11-07 20:17         ` Trent Piepho
2018-11-08  9:49           ` Marc Zyngier
2018-11-08 19:49             ` Trent Piepho
2018-11-09 10:13               ` Lorenzo Pieralisi
2018-11-09 17:17                 ` Vignesh R
2018-11-09 11:34               ` Marc Zyngier
2018-11-09 18:53                 ` Trent Piepho
2018-11-13  0:41                 ` Gustavo Pimentel
2018-11-13  1:18                   ` Trent Piepho
2018-11-13 10:36                     ` Lorenzo Pieralisi
2018-11-13 18:55                       ` Trent Piepho
2018-11-13 14:40                   ` Marc Zyngier
2018-11-07 12:57     ` Gustavo Pimentel
2018-11-07 18:32       ` Trent Piepho [this message]
2018-11-08 11:46         ` Gustavo Pimentel
2018-11-08 20:51           ` Trent Piepho
2018-11-12 16:01             ` Lorenzo Pieralisi
2018-11-13  1:03               ` Gustavo Pimentel
2018-11-14 21:29               ` Trent Piepho
2018-11-12 23:45             ` Gustavo Pimentel
2018-11-07 18:46       ` Marc Zyngier
2018-11-08 11:24         ` Gustavo Pimentel
2018-11-06 18:59   ` Trent Piepho

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