[PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

[Kevin Strasser <kevin.strasser@intel.com>]

64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
  * 90/270 rotation not supported
  * Yf Tiling not supported
  * Frame Buffer Compression not supported
  * Color Keying not supported

The behavior of pixel normalize with non-float formats is currently
undefined. As such, the pixel normalize register is enabled iff the
framebuffer contains floating point pixel data.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
---
 drivers/gpu/drm/i915/i915_reg.h      | 15 ++++++-
 drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 82 +++++++++++++++++++++++++++++++++---
 4 files changed, 143 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe..871d293 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6563,6 +6563,10 @@ enum {
 #define _PLANE_KEYMAX_1_A			0x701a0
 #define _PLANE_KEYMAX_2_A			0x702a0
 #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
+#define _PLANE_PIXEL_NORMALIZE_1_A		0x701a8
+#define _PLANE_PIXEL_NORMALIZE_2_A		0x702a8
+#define   PLANE_PIXEL_NORMALIZE_ENABLE		(1 << 31)
+#define   PLANE_PIXEL_NORMALIZE_FACTOR_MASK	0xffff
 #define _PLANE_AUX_DIST_1_A			0x701c0
 #define _PLANE_AUX_DIST_2_A			0x702c0
 #define _PLANE_AUX_OFFSET_1_A			0x701c4
@@ -6786,7 +6790,16 @@ enum {
 #define PLANE_COLOR_CTL(pipe, plane)	\
 	_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
 
-#/* SKL new cursor registers */
+#define _PLANE_PIXEL_NORMALIZE_1_B	0x711a8
+#define _PLANE_PIXEL_NORMALIZE_2_B	0x712a8
+#define _PLANE_PIXEL_NORMALIZE_1(pipe) \
+	_PIPE(pipe, _PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B)
+#define _PLANE_PIXEL_NORMALIZE_2(pipe) \
+	_PIPE(pipe, _PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
+#define PLANE_PIXEL_NORMALIZE(pipe, plane) \
+	_MMIO_PLANE(plane, _PLANE_PIXEL_NORMALIZE_1(pipe), _PLANE_PIXEL_NORMALIZE_2(pipe))
+
+/* SKL new cursor registers */
 #define _CUR_BUF_CFG_A				0x7017c
 #define _CUR_BUF_CFG_B				0x7117c
 #define CUR_BUF_CFG(pipe)	_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22..cbacb4b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2618,6 +2618,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 		return DRM_FORMAT_RGB565;
 	case PLANE_CTL_FORMAT_NV12:
 		return DRM_FORMAT_NV12;
+	case PLANE_CTL_FORMAT_XRGB_16161616F:
+		if (rgb_order) {
+			if (alpha)
+				return DRM_FORMAT_ABGR16161616H;
+			else
+				return DRM_FORMAT_XBGR16161616H;
+		} else {
+			if (alpha)
+				return DRM_FORMAT_ARGB16161616H;
+			else
+				return DRM_FORMAT_XRGB16161616H;
+		}
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
@@ -3505,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
+	case DRM_FORMAT_XBGR16161616H:
+	case DRM_FORMAT_ABGR16161616H:
+		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+	case DRM_FORMAT_XRGB16161616H:
+	case DRM_FORMAT_ARGB16161616H:
+		return PLANE_CTL_FORMAT_XRGB_16161616F;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -3680,6 +3698,32 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	return plane_color_ctl;
 }
 
+u32 icl_plane_pixel_normalize(uint32_t pixel_format,
+			      enum drm_pixel_normalize_range range)
+{
+	/* 1.0 in half float */
+	u16 half_float_1 = 0x3c00;
+	/* 3.92E-3 in half float */
+	u16 half_float_255 = 0x1c04;
+
+	switch (pixel_format) {
+	case DRM_FORMAT_XRGB16161616H:
+	case DRM_FORMAT_XBGR16161616H:
+	case DRM_FORMAT_ARGB16161616H:
+	case DRM_FORMAT_ABGR16161616H:
+		switch (range) {
+		case DRM_PIXEL_NORMALIZE_RANGE_0_1:
+			return PLANE_PIXEL_NORMALIZE_ENABLE | half_float_1;
+		case DRM_PIXEL_NORMALIZE_RANGE_0_255:
+			return PLANE_PIXEL_NORMALIZE_ENABLE | half_float_255;
+		default:
+			return 0;
+		}
+	default:
+		return 0;
+	}
+}
+
 static int
 __intel_display_resume(struct drm_device *dev,
 		       struct drm_atomic_state *state,
@@ -4998,6 +5042,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_XBGR16161616H:
+	case DRM_FORMAT_ABGR16161616H:
+	case DRM_FORMAT_XRGB16161616H:
+	case DRM_FORMAT_ARGB16161616H:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a62d77b..a56b131 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -565,6 +565,9 @@ struct intel_plane_state {
 	u32 slave;
 
 	struct drm_intel_sprite_colorkey ckey;
+
+	/* plane pixel normalize register */
+	u32 pixel_normalize;
 };
 
 struct intel_initial_plane_config {
@@ -1738,6 +1741,8 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 		     int plane);
+u32 icl_plane_pixel_normalize(uint32_t pixel_format,
+			      enum drm_pixel_normalize_range range);
 int skl_check_plane_surface(struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index abe1938..9dea0b8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -515,6 +515,10 @@ skl_program_plane(struct intel_plane *plane,
 	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
 		icl_program_input_csc_coeff(crtc_state, plane_state);
 
+	if (fb->format->is_fp && icl_is_hdr_plane(plane))
+		I915_WRITE_FW(PLANE_PIXEL_NORMALIZE(pipe, plane_id),
+			      plane_state->pixel_normalize);
+
 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
 	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
@@ -1417,8 +1421,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 		/*
 		 * 90/270 is not allowed with RGB64 16:16:16:16 and
 		 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
-		 * TBD: Add RGB64 case once its added in supported format
-		 * list.
 		 */
 		switch (fb->format->format) {
 		case DRM_FORMAT_RGB565:
@@ -1426,6 +1428,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 				break;
 			/* fall through */
 		case DRM_FORMAT_C8:
+		case DRM_FORMAT_XRGB16161616H:
+		case DRM_FORMAT_XBGR16161616H:
+		case DRM_FORMAT_ARGB16161616H:
+		case DRM_FORMAT_ABGR16161616H:
 			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
 				      drm_get_format_name(fb->format->format,
 							  &format_name));
@@ -1552,6 +1558,11 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
 							     plane_state);
 
+	if (icl_is_hdr_plane(plane))
+		plane_state->pixel_normalize =
+			icl_plane_pixel_normalize(plane_state->base.fb->format->format,
+						  plane_state->base.pixel_normalize_range);
+
 	return 0;
 }
 
@@ -1741,6 +1752,45 @@ static const uint32_t skl_planar_formats[] = {
 	DRM_FORMAT_NV12,
 };
 
+static const uint32_t icl_hdr_plane_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_XRGB16161616H,
+	DRM_FORMAT_XBGR16161616H,
+	DRM_FORMAT_ARGB16161616H,
+	DRM_FORMAT_ABGR16161616H,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+};
+
+static const uint32_t icl_hdr_planar_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_XRGB16161616H,
+	DRM_FORMAT_XBGR16161616H,
+	DRM_FORMAT_ARGB16161616H,
+	DRM_FORMAT_ABGR16161616H,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1884,6 +1934,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 			return true;
 		/* fall through */
 	case DRM_FORMAT_C8:
+	case DRM_FORMAT_XBGR16161616H:
+	case DRM_FORMAT_ABGR16161616H:
+	case DRM_FORMAT_XRGB16161616H:
+	case DRM_FORMAT_ARGB16161616H:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
 		    modifier == I915_FORMAT_MOD_Y_TILED)
@@ -2020,11 +2074,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		plane->update_slave = icl_update_slave;
 
 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
-		formats = skl_planar_formats;
-		num_formats = ARRAY_SIZE(skl_planar_formats);
+		if (icl_is_hdr_plane(plane)) {
+			formats = icl_hdr_planar_formats;
+			num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+		} else {
+			formats = skl_planar_formats;
+			num_formats = ARRAY_SIZE(skl_planar_formats);
+		}
 	} else {
-		formats = skl_plane_formats;
-		num_formats = ARRAY_SIZE(skl_plane_formats);
+		if (icl_is_hdr_plane(plane)) {
+			formats = icl_hdr_plane_formats;
+			num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
+		} else {
+			formats = skl_plane_formats;
+			num_formats = ARRAY_SIZE(skl_plane_formats);
+		}
 	}
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
@@ -2074,6 +2138,12 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 					     BIT(DRM_MODE_BLEND_PREMULTI) |
 					     BIT(DRM_MODE_BLEND_COVERAGE));
 
+	if (icl_is_hdr_plane(plane))
+		drm_plane_create_pixel_normalize_range_property(&plane->base,
+				BIT(DRM_PIXEL_NORMALIZE_RANGE_0_1) |
+				BIT(DRM_PIXEL_NORMALIZE_RANGE_0_255),
+				DRM_PIXEL_NORMALIZE_RANGE_0_1);
+
 	drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
 
 	return plane;
-- 
2.7.4

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