From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jeffrey Hugo Subject: [PATCH v1 4/6] phy: qcom-qmp: Add QMP V3 USB3 PHY support for msm8998 Date: Fri, 4 Jan 2019 09:50:47 -0700 Message-ID: <1546620647-2467-1-git-send-email-jhugo@codeaurora.org> Return-path: Sender: linux-kernel-owner@vger.kernel.org To: kishon@ti.com, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, andy.gross@linaro.org, david.brown@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, balbi@kernel.org, linux-usb@vger.kernel.org, Jeffrey Hugo List-Id: linux-arm-msm@vger.kernel.org MSM8998 contains a single QMP v3 USB3 phy similar to the existing sdm845 support, however MSM8998 does not have display port (DP) support. Signed-off-by: Jeffrey Hugo --- .../devicetree/bindings/phy/qcom-qmp-phy.txt | 5 + drivers/phy/qualcomm/phy-qcom-qmp.c | 142 +++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 4 + 3 files changed, 151 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 41a1074..6061b6f 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -9,6 +9,7 @@ Required properties: "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, + "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845. @@ -42,6 +43,8 @@ Required properties: "aux", "cfg_ahb", "ref". For "qcom,msm8996-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref". + For "qcom,msm8998-qmp-usb3-phy" must contain: + "aux", "cfg_ahb", "ref". For "qcom,sdm845-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref", "com_aux". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: @@ -60,6 +63,8 @@ Required properties: For "qcom,msm8996-qmp-pcie-phy" must contain: "phy", "common", "cfg". For "qcom,msm8996-qmp-usb3-phy" must contain + "phy", "common". + For "qcom,msm8998-qmp-usb3-phy" must contain "phy", "common". For "qcom,sdm845-qmp-usb3-phy" must contain: "phy", "common". diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index b400681..c0111a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -687,6 +687,116 @@ enum qphy_reg_layout { QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +}; + + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* phy-type - PCIE/UFS/USB */ @@ -1036,6 +1146,35 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) .no_pcs_sw_reset = true, }; +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = msm8998_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), + .tx_tbl = msm8998_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), + .rx_tbl = msm8998_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), + .pcs_tbl = msm8998_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .mask_pcs_ready = PHYSTATUS, + + .is_dual_lane_phy = true, + .tx_b_lane_offset = 0x400, + .rx_b_lane_offset = 0x400, +}; + static void qcom_qmp_phy_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], @@ -1747,6 +1886,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = &sdm845_ufsphy_cfg, + }, { + .compatible = "qcom,msm8998-qmp-usb3-phy", + .data = &msm8998_usb3phy_cfg, }, { }, }; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index d201cc3..a1b6cde 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -174,6 +174,7 @@ #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc +#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 @@ -201,6 +202,7 @@ #define QSERDES_V3_COM_DEBUG_BUS2 0x170 #define QSERDES_V3_COM_DEBUG_BUS3 0x174 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 +#define QSERDES_V3_COM_CMN_MODE 0x184 /* Only for QMP V3 PHY - TX registers */ #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 @@ -211,6 +213,7 @@ #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 /* Only for QMP V3 PHY - RX registers */ +#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 @@ -219,6 +222,7 @@ #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 #define QSERDES_V3_RX_RX_TERM_BW 0x07c #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1,4/6] phy: qcom-qmp: Add QMP V3 USB3 PHY support for msm8998 From: Jeffrey Hugo Message-Id: <1546620647-2467-1-git-send-email-jhugo@codeaurora.org> Date: Fri, 4 Jan 2019 09:50:47 -0700 To: kishon@ti.com, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, andy.gross@linaro.org, david.brown@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, balbi@kernel.org, linux-usb@vger.kernel.org, Jeffrey Hugo List-ID: TVNNODk5OCBjb250YWlucyBhIHNpbmdsZSBRTVAgdjMgVVNCMyBwaHkgc2ltaWxhciB0byB0aGUg ZXhpc3Rpbmcgc2RtODQ1CnN1cHBvcnQsIGhvd2V2ZXIgTVNNODk5OCBkb2VzIG5vdCBoYXZlIGRp c3BsYXkgcG9ydCAoRFApIHN1cHBvcnQuCgpTaWduZWQtb2ZmLWJ5OiBKZWZmcmV5IEh1Z28gPGpo dWdvQGNvZGVhdXJvcmEub3JnPgotLS0KIC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL3BoeS9xY29t LXFtcC1waHkudHh0ICAgICAgIHwgICA1ICsKIGRyaXZlcnMvcGh5L3F1YWxjb21tL3BoeS1xY29t LXFtcC5jICAgICAgICAgICAgICAgIHwgMTQyICsrKysrKysrKysrKysrKysrKysrKwogZHJpdmVy cy9waHkvcXVhbGNvbW0vcGh5LXFjb20tcW1wLmggICAgICAgICAgICAgICAgfCAgIDQgKwogMyBm aWxlcyBjaGFuZ2VkLCAxNTEgaW5zZXJ0aW9ucygrKQoKZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRp b24vZGV2aWNldHJlZS9iaW5kaW5ncy9waHkvcWNvbS1xbXAtcGh5LnR4dCBiL0RvY3VtZW50YXRp b24vZGV2aWNldHJlZS9iaW5kaW5ncy9waHkvcWNvbS1xbXAtcGh5LnR4dAppbmRleCA0MWExMDc0 Li42MDYxYjZmIDEwMDY0NAotLS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mv cGh5L3Fjb20tcW1wLXBoeS50eHQKKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL3BoeS9xY29tLXFtcC1waHkudHh0CkBAIC05LDYgKzksNyBAQCBSZXF1aXJlZCBwcm9wZXJ0 aWVzOgogCSAgICAgICAicWNvbSxpcHE4MDc0LXFtcC1wY2llLXBoeSIgZm9yIFBDSWUgcGh5IG9u IElQUTgwNzQKIAkgICAgICAgInFjb20sbXNtODk5Ni1xbXAtcGNpZS1waHkiIGZvciAxNG5tIFBD SWUgcGh5IG9uIG1zbTg5OTYsCiAJICAgICAgICJxY29tLG1zbTg5OTYtcW1wLXVzYjMtcGh5IiBm b3IgMTRubSBVU0IzIHBoeSBvbiBtc204OTk2LAorCSAgICAgICAicWNvbSxtc204OTk4LXFtcC11 c2IzLXBoeSIgZm9yIFVTQjMgUU1QIFYzIHBoeSBvbiBtc204OTk4LAogCSAgICAgICAicWNvbSxz ZG04NDUtcW1wLXVzYjMtcGh5IiBmb3IgVVNCMyBRTVAgVjMgcGh5IG9uIHNkbTg0NSwKIAkgICAg ICAgInFjb20sc2RtODQ1LXFtcC11c2IzLXVuaS1waHkiIGZvciBVU0IzIFFNUCBWMyBVTkkgcGh5 IG9uIHNkbTg0NSwKIAkgICAgICAgInFjb20sc2RtODQ1LXFtcC11ZnMtcGh5IiBmb3IgVUZTIFFN UCBwaHkgb24gc2RtODQ1LgpAQCAtNDIsNiArNDMsOCBAQCBSZXF1aXJlZCBwcm9wZXJ0aWVzOgog CQkJImF1eCIsICJjZmdfYWhiIiwgInJlZiIuCiAJCUZvciAicWNvbSxtc204OTk2LXFtcC11c2Iz LXBoeSIgbXVzdCBjb250YWluOgogCQkJImF1eCIsICJjZmdfYWhiIiwgInJlZiIuCisJCUZvciAi cWNvbSxtc204OTk4LXFtcC11c2IzLXBoeSIgbXVzdCBjb250YWluOgorCQkJImF1eCIsICJjZmdf YWhiIiwgInJlZiIuCiAJCUZvciAicWNvbSxzZG04NDUtcW1wLXVzYjMtcGh5IiBtdXN0IGNvbnRh aW46CiAJCQkiYXV4IiwgImNmZ19haGIiLCAicmVmIiwgImNvbV9hdXgiLgogCQlGb3IgInFjb20s c2RtODQ1LXFtcC11c2IzLXVuaS1waHkiIG11c3QgY29udGFpbjoKQEAgLTYwLDYgKzYzLDggQEAg UmVxdWlyZWQgcHJvcGVydGllczoKIAkJRm9yICJxY29tLG1zbTg5OTYtcW1wLXBjaWUtcGh5IiBt dXN0IGNvbnRhaW46CiAJCQkicGh5IiwgImNvbW1vbiIsICJjZmciLgogCQlGb3IgInFjb20sbXNt ODk5Ni1xbXAtdXNiMy1waHkiIG11c3QgY29udGFpbgorCQkgInBoeSIsICJjb21tb24iLgorCQlG b3IgInFjb20sbXNtODk5OC1xbXAtdXNiMy1waHkiIG11c3QgY29udGFpbgogCQkJInBoeSIsICJj b21tb24iLgogCQlGb3IgInFjb20sc2RtODQ1LXFtcC11c2IzLXBoeSIgbXVzdCBjb250YWluOgog CQkJInBoeSIsICJjb21tb24iLgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9waHkvcXVhbGNvbW0vcGh5 LXFjb20tcW1wLmMgYi9kcml2ZXJzL3BoeS9xdWFsY29tbS9waHktcWNvbS1xbXAuYwppbmRleCBi NDAwNjgxLi5jMDExMWE2IDEwMDY0NAotLS0gYS9kcml2ZXJzL3BoeS9xdWFsY29tbS9waHktcWNv bS1xbXAuYworKysgYi9kcml2ZXJzL3BoeS9xdWFsY29tbS9waHktcWNvbS1xbXAuYwpAQCAtNjg3 LDYgKzY4NywxMTYgQEAgZW51bSBxcGh5X3JlZ19sYXlvdXQgewogCVFNUF9QSFlfSU5JVF9DRkco UVBIWV9WM19QQ1NfTVVMVElfTEFORV9DVFJMMSwgMHgwMiksCiB9OwogCitzdGF0aWMgY29uc3Qg c3RydWN0IHFtcF9waHlfaW5pdF90YmwgbXNtODk5OF91c2IzX3NlcmRlc190YmxbXSA9IHsKKwlR TVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX0NMS19TRUxFQ1QsIDB4MzApLAorCVFNUF9Q SFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fQklBU19FTl9DTEtCVUZMUl9FTiwgMHgwNCksCisJ UU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9TWVNDTEtfRU5fU0VMLCAweDE0KSwKKwlR TVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX1NZU19DTEtfQ1RSTCwgMHgwNiksCisJUU1Q X1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9SRVNFVFNNX0NOVFJMMiwgMHgwOCksCisJUU1Q X1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9DTU5fQ09ORklHLCAweDA2KSwKKwlRTVBfUEhZ X0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX1NWU19NT0RFX0NMS19TRUwsIDB4MDEpLAorCVFNUF9Q SFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fSFNDTEtfU0VMLCAweDgwKSwKKwlRTVBfUEhZX0lO SVRfQ0ZHKFFTRVJERVNfVjNfQ09NX0RFQ19TVEFSVF9NT0RFMCwgMHg4MiksCisJUU1QX1BIWV9J TklUX0NGRyhRU0VSREVTX1YzX0NPTV9ESVZfRlJBQ19TVEFSVDFfTU9ERTAsIDB4YWIpLAorCVFN UF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fRElWX0ZSQUNfU1RBUlQyX01PREUwLCAweGVh KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX0RJVl9GUkFDX1NUQVJUM19NT0RF MCwgMHgwMiksCisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9DUF9DVFJMX01PREUw LCAweDA2KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX1BMTF9SQ1RSTF9NT0RF MCwgMHgxNiksCisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9QTExfQ0NUUkxfTU9E RTAsIDB4MzYpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fSU5URUdMT09QX0dB SU4xX01PREUwLCAweDAwKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX0lOVEVH TE9PUF9HQUlOMF9NT0RFMCwgMHgzZiksCisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NP TV9WQ09fVFVORTJfTU9ERTAsIDB4MDEpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19D T01fVkNPX1RVTkUxX01PREUwLCAweGM5KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNf Q09NX0NPUkVDTEtfRElWX01PREUwLCAweDBhKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNf VjNfQ09NX0xPQ0tfQ01QM19NT0RFMCwgMHgwMCksCisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVT X1YzX0NPTV9MT0NLX0NNUDJfTU9ERTAsIDB4MzQpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRF U19WM19DT01fTE9DS19DTVAxX01PREUwLCAweDE1KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJE RVNfVjNfQ09NX0xPQ0tfQ01QX0VOLCAweDA0KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNf VjNfQ09NX0NPUkVfQ0xLX0VOLCAweDAwKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNf Q09NX0xPQ0tfQ01QX0NGRywgMHgwMCksCisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NP TV9WQ09fVFVORV9NQVAsIDB4MDApLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01f QkdfVElNRVIsIDB4MGEpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fUExMX0lW Q08sIDB4MDcpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fSU5URUdMT09QX0lO SVRWQUwsIDB4ODApLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fQ01OX01PREUs IDB4MDEpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fU1NDX0VOX0NFTlRFUiwg MHgwMSksCisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9TU0NfUEVSMSwgMHgzMSks CisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9TU0NfUEVSMiwgMHgwMSksCisJUU1Q X1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX0NPTV9TU0NfQURKX1BFUjEsIDB4MDApLAorCVFNUF9Q SFlfSU5JVF9DRkcoUVNFUkRFU19WM19DT01fU1NDX0FESl9QRVIyLCAweDAwKSwKKwlRTVBfUEhZ X0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX1NTQ19TVEVQX1NJWkUxLCAweDg1KSwKKwlRTVBfUEhZ X0lOSVRfQ0ZHKFFTRVJERVNfVjNfQ09NX1NTQ19TVEVQX1NJWkUyLCAweDA3KSwKK307CisKK3N0 YXRpYyBjb25zdCBzdHJ1Y3QgcW1wX3BoeV9pbml0X3RibCBtc204OTk4X3VzYjNfdHhfdGJsW10g PSB7CisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX1RYX0hJR0haX0RSVlJfRU4sIDB4MTAp LAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19UWF9SQ1ZfREVURUNUX0xWTF8yLCAweDEy KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJERVNfVjNfVFhfTEFORV9NT0RFXzEsIDB4MTYpLAor CVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19UWF9SRVNfQ09ERV9MQU5FX09GRlNFVF9UWCwg MHgwMCksCit9OworCitzdGF0aWMgY29uc3Qgc3RydWN0IHFtcF9waHlfaW5pdF90YmwgbXNtODk5 OF91c2IzX3J4X3RibFtdID0geworCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19SWF9VQ0RS X0ZBU1RMT0NLX0ZPX0dBSU4sIDB4MGIpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19S WF9SWF9FUVVfQURBUFRPUl9DTlRSTDIsIDB4MGYpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRF U19WM19SWF9SWF9FUVVfQURBUFRPUl9DTlRSTDMsIDB4NGUpLAorCVFNUF9QSFlfSU5JVF9DRkco UVNFUkRFU19WM19SWF9SWF9FUVVfQURBUFRPUl9DTlRSTDQsIDB4MTgpLAorCVFNUF9QSFlfSU5J VF9DRkcoUVNFUkRFU19WM19SWF9SWF9FUV9PRkZTRVRfQURBUFRPUl9DTlRSTDEsIDB4MDcpLAor CVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19SWF9SWF9PRkZTRVRfQURBUFRPUl9DTlRSTDIs IDB4ODApLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19SWF9TSUdERVRfQ05UUkwsIDB4 NDMpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19SWF9TSUdERVRfREVHTElUQ0hfQ05U UkwsIDB4MWMpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNFUkRFU19WM19SWF9VQ0RSX1NPX1NBVFVS QVRJT05fQU5EX0VOQUJMRSwgMHg3NSksCisJUU1QX1BIWV9JTklUX0NGRyhRU0VSREVTX1YzX1JY X1VDRFJfRkFTVExPQ0tfQ09VTlRfTE9XLCAweDAwKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFTRVJE RVNfVjNfUlhfVUNEUl9GQVNUTE9DS19DT1VOVF9ISUdILCAweDAwKSwKKwlRTVBfUEhZX0lOSVRf Q0ZHKFFTRVJERVNfVjNfUlhfVUNEUl9QSV9DT05UUk9MUywgMHg4MCksCisJUU1QX1BIWV9JTklU X0NGRyhRU0VSREVTX1YzX1JYX1VDRFJfRk9fR0FJTiwgMHgwYSksCisJUU1QX1BIWV9JTklUX0NG RyhRU0VSREVTX1YzX1JYX1VDRFJfU09fR0FJTiwgMHgwNiksCisJUU1QX1BIWV9JTklUX0NGRyhR U0VSREVTX1YzX1JYX1NJR0RFVF9FTkFCTEVTLCAweDAwKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFT RVJERVNfVjNfUlhfVkdBX0NBTF9DTlRSTDIsIDB4MDMpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVNF UkRFU19WM19SWF9SWF9NT0RFXzAwLCAweDA1KSwKK307CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg cW1wX3BoeV9pbml0X3RibCBtc204OTk4X3VzYjNfcGNzX3RibFtdID0geworCVFNUF9QSFlfSU5J VF9DRkcoUVBIWV9WM19QQ1NfRkxMX0NOVFJMMiwgMHg4MyksCisJUU1QX1BIWV9JTklUX0NGRyhR UEhZX1YzX1BDU19GTExfQ05UX1ZBTF9MLCAweDA5KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQSFlf VjNfUENTX0ZMTF9DTlRfVkFMX0hfVE9MLCAweGEyKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQSFlf VjNfUENTX0ZMTF9NQU5fQ09ERSwgMHg0MCksCisJUU1QX1BIWV9JTklUX0NGRyhRUEhZX1YzX1BD U19GTExfQ05UUkwxLCAweDAyKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQSFlfVjNfUENTX0xPQ0tf REVURUNUX0NPTkZJRzEsIDB4ZDEpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBIWV9WM19QQ1NfTE9D S19ERVRFQ1RfQ09ORklHMiwgMHgxZiksCisJUU1QX1BIWV9JTklUX0NGRyhRUEhZX1YzX1BDU19M T0NLX0RFVEVDVF9DT05GSUczLCAweDQ3KSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQSFlfVjNfUENT X1BPV0VSX1NUQVRFX0NPTkZJRzIsIDB4MWIpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBIWV9WM19Q Q1NfVFhNR05fVjAsIDB4OWYpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBIWV9WM19QQ1NfVFhNR05f VjEsIDB4OWYpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBIWV9WM19QQ1NfVFhNR05fVjIsIDB4Yjcp LAorCVFNUF9QSFlfSU5JVF9DRkcoUVBIWV9WM19QQ1NfVFhNR05fVjMsIDB4NGUpLAorCVFNUF9Q SFlfSU5JVF9DRkcoUVBIWV9WM19QQ1NfVFhNR05fVjQsIDB4NjUpLAorCVFNUF9QSFlfSU5JVF9D RkcoUVBIWV9WM19QQ1NfVFhNR05fTFMsIDB4NmIpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBIWV9W M19QQ1NfVFhERUVNUEhfTTZEQl9WMCwgMHgxNSksCisJUU1QX1BIWV9JTklUX0NGRyhRUEhZX1Yz X1BDU19UWERFRU1QSF9NM1A1REJfVjAsIDB4MGQpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBIWV9W M19QQ1NfVFhfTEFSR0VfQU1QX0RSVl9MVkwsIDB4MTUpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBI WV9WM19QQ1NfVFhERUVNUEhfTTNQNURCX1YxLCAweDBkKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQ SFlfVjNfUENTX1RYREVFTVBIX002REJfVjIsIDB4MTUpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBI WV9WM19QQ1NfVFhERUVNUEhfTTNQNURCX1YyLCAweDBkKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQ SFlfVjNfUENTX1RYREVFTVBIX002REJfVjMsIDB4MTUpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBI WV9WM19QQ1NfVFhERUVNUEhfTTNQNURCX1YzLCAweDBkKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQ SFlfVjNfUENTX1RYREVFTVBIX002REJfVjQsIDB4MTUpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBI WV9WM19QQ1NfVFhERUVNUEhfTTNQNURCX1Y0LCAweDBkKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQ SFlfVjNfUENTX1RYREVFTVBIX002REJfTFMsIDB4MTUpLAorCVFNUF9QSFlfSU5JVF9DRkcoUVBI WV9WM19QQ1NfVFhERUVNUEhfTTNQNURCX0xTLCAweDBkKSwKKwlRTVBfUEhZX0lOSVRfQ0ZHKFFQ SFlfVjNfUENTX1JBVEVfU0xFV19DTlRSTCwgMHgwMiksCisJUU1QX1BIWV9JTklUX0NGRyhRUEhZ X1YzX1BDU19QV1JVUF9SRVNFVF9ETFlfVElNRV9BVVhDTEssIDB4MDQpLAorCVFNUF9QSFlfSU5J VF9DRkcoUVBIWV9WM19QQ1NfVFNZTkNfUlNZTkNfVElNRSwgMHg0NCksCisJUU1QX1BIWV9JTklU X0NGRyhRUEhZX1YzX1BDU19SQ1ZSX0RUQ1RfRExZX1AxVTJfTCwgMHhlNyksCisJUU1QX1BIWV9J TklUX0NGRyhRUEhZX1YzX1BDU19SQ1ZSX0RUQ1RfRExZX1AxVTJfSCwgMHgwMyksCisJUU1QX1BI WV9JTklUX0NGRyhRUEhZX1YzX1BDU19SQ1ZSX0RUQ1RfRExZX1UzX0wsIDB4NDApLAorCVFNUF9Q SFlfSU5JVF9DRkcoUVBIWV9WM19QQ1NfUkNWUl9EVENUX0RMWV9VM19ILCAweDAwKSwKKwlRTVBf UEhZX0lOSVRfQ0ZHKFFQSFlfVjNfUENTX1JYX1NJR0RFVF9MVkwsIDB4OGEpLAorCVFNUF9QSFlf SU5JVF9DRkcoUVBIWV9WM19QQ1NfUlhFUVRSQUlOSU5HX1dBSVRfVElNRSwgMHg3NSksCisJUU1Q X1BIWV9JTklUX0NGRyhRUEhZX1YzX1BDU19MRlBTX1RYX0VDU1RBUlRfRVFUTE9DSywgMHg4Niks CisJUU1QX1BIWV9JTklUX0NGRyhRUEhZX1YzX1BDU19SWEVRVFJBSU5JTkdfUlVOX1RJTUUsIDB4 MTMpLAorfTsKKworCiAvKiBzdHJ1Y3QgcW1wX3BoeV9jZmcgLSBwZXItUEhZIGluaXRpYWxpemF0 aW9uIGNvbmZpZyAqLwogc3RydWN0IHFtcF9waHlfY2ZnIHsKIAkvKiBwaHktdHlwZSAtIFBDSUUv VUZTL1VTQiAqLwpAQCAtMTAzNiw2ICsxMTQ2LDM1IEBAIHN0YXRpYyBpbmxpbmUgdm9pZCBxcGh5 X2NscmJpdHModm9pZCBfX2lvbWVtICpiYXNlLCB1MzIgb2Zmc2V0LCB1MzIgdmFsKQogCS5ub19w Y3Nfc3dfcmVzZXQJPSB0cnVlLAogfTsKIAorc3RhdGljIGNvbnN0IHN0cnVjdCBxbXBfcGh5X2Nm ZyBtc204OTk4X3VzYjNwaHlfY2ZnID0geworCS50eXBlICAgICAgICAgICAgICAgICAgID0gUEhZ X1RZUEVfVVNCMywKKwkubmxhbmVzICAgICAgICAgICAgICAgICA9IDEsCisKKwkuc2VyZGVzX3Ri bCAgICAgICAgICAgICA9IG1zbTg5OThfdXNiM19zZXJkZXNfdGJsLAorCS5zZXJkZXNfdGJsX251 bSAgICAgICAgID0gQVJSQVlfU0laRShtc204OTk4X3VzYjNfc2VyZGVzX3RibCksCisJLnR4X3Ri bCAgICAgICAgICAgICAgICAgPSBtc204OTk4X3VzYjNfdHhfdGJsLAorCS50eF90YmxfbnVtICAg ICAgICAgICAgID0gQVJSQVlfU0laRShtc204OTk4X3VzYjNfdHhfdGJsKSwKKwkucnhfdGJsICAg ICAgICAgICAgICAgICA9IG1zbTg5OThfdXNiM19yeF90YmwsCisJLnJ4X3RibF9udW0gICAgICAg ICAgICAgPSBBUlJBWV9TSVpFKG1zbTg5OThfdXNiM19yeF90YmwpLAorCS5wY3NfdGJsICAgICAg ICAgICAgICAgID0gbXNtODk5OF91c2IzX3Bjc190YmwsCisJLnBjc190YmxfbnVtICAgICAgICAg ICAgPSBBUlJBWV9TSVpFKG1zbTg5OThfdXNiM19wY3NfdGJsKSwKKwkuY2xrX2xpc3QgICAgICAg ICAgICAgICA9IG1zbTg5OTZfcGh5X2Nsa19sLAorCS5udW1fY2xrcyAgICAgICAgICAgICAgID0g QVJSQVlfU0laRShtc204OTk2X3BoeV9jbGtfbCksCisJLnJlc2V0X2xpc3QgICAgICAgICAgICAg PSBtc204OTk2X3VzYjNwaHlfcmVzZXRfbCwKKwkubnVtX3Jlc2V0cyAgICAgICAgICAgICA9IEFS UkFZX1NJWkUobXNtODk5Nl91c2IzcGh5X3Jlc2V0X2wpLAorCS52cmVnX2xpc3QgICAgICAgICAg ICAgID0gcW1wX3BoeV92cmVnX2wsCisJLm51bV92cmVncyAgICAgICAgICAgICAgPSBBUlJBWV9T SVpFKHFtcF9waHlfdnJlZ19sKSwKKwkucmVncyAgICAgICAgICAgICAgICAgICA9IHFtcF92M191 c2IzcGh5X3JlZ3NfbGF5b3V0LAorCisJLnN0YXJ0X2N0cmwgICAgICAgICAgICAgPSBTRVJERVNf U1RBUlQgfCBQQ1NfU1RBUlQsCisJLnB3cmRuX2N0cmwgICAgICAgICAgICAgPSBTV19QV1JETiwK KwkubWFza19wY3NfcmVhZHkgICAgICAgICA9IFBIWVNUQVRVUywKKworCS5pc19kdWFsX2xhbmVf cGh5ICAgICAgID0gdHJ1ZSwKKwkudHhfYl9sYW5lX29mZnNldCAgICAgICA9IDB4NDAwLAorCS5y eF9iX2xhbmVfb2Zmc2V0ICAgICAgID0gMHg0MDAsCit9OworCiBzdGF0aWMgdm9pZCBxY29tX3Ft cF9waHlfY29uZmlndXJlKHZvaWQgX19pb21lbSAqYmFzZSwKIAkJCQkgICBjb25zdCB1bnNpZ25l ZCBpbnQgKnJlZ3MsCiAJCQkJICAgY29uc3Qgc3RydWN0IHFtcF9waHlfaW5pdF90YmwgdGJsW10s CkBAIC0xNzQ3LDYgKzE4ODYsOSBAQCBpbnQgcWNvbV9xbXBfcGh5X2NyZWF0ZShzdHJ1Y3QgZGV2 aWNlICpkZXYsIHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAsIGludCBpZCkKIAl9LCB7CiAJCS5jb21w YXRpYmxlID0gInFjb20sc2RtODQ1LXFtcC11ZnMtcGh5IiwKIAkJLmRhdGEgPSAmc2RtODQ1X3Vm c3BoeV9jZmcsCisJfSwgeworCQkuY29tcGF0aWJsZSA9ICJxY29tLG1zbTg5OTgtcW1wLXVzYjMt cGh5IiwKKwkJLmRhdGEgPSAmbXNtODk5OF91c2IzcGh5X2NmZywKIAl9LAogCXsgfSwKIH07CmRp ZmYgLS1naXQgYS9kcml2ZXJzL3BoeS9xdWFsY29tbS9waHktcWNvbS1xbXAuaCBiL2RyaXZlcnMv cGh5L3F1YWxjb21tL3BoeS1xY29tLXFtcC5oCmluZGV4IGQyMDFjYzMuLmExYjZjZGUgMTAwNjQ0 Ci0tLSBhL2RyaXZlcnMvcGh5L3F1YWxjb21tL3BoeS1xY29tLXFtcC5oCisrKyBiL2RyaXZlcnMv cGh5L3F1YWxjb21tL3BoeS1xY29tLXFtcC5oCkBAIC0xNzQsNiArMTc0LDcgQEAKICNkZWZpbmUg UVNFUkRFU19WM19DT01fRElWX0ZSQUNfU1RBUlQxX01PREUxCQkweDBjNAogI2RlZmluZSBRU0VS REVTX1YzX0NPTV9ESVZfRlJBQ19TVEFSVDJfTU9ERTEJCTB4MGM4CiAjZGVmaW5lIFFTRVJERVNf VjNfQ09NX0RJVl9GUkFDX1NUQVJUM19NT0RFMQkJMHgwY2MKKyNkZWZpbmUgUVNFUkRFU19WM19D T01fSU5URUdMT09QX0lOSVRWQUwJCTB4MGQwCiAjZGVmaW5lIFFTRVJERVNfVjNfQ09NX0lOVEVH TE9PUF9HQUlOMF9NT0RFMAkJMHgwZDgKICNkZWZpbmUgUVNFUkRFU19WM19DT01fSU5URUdMT09Q X0dBSU4xX01PREUwCQkweDBkYwogI2RlZmluZSBRU0VSREVTX1YzX0NPTV9JTlRFR0xPT1BfR0FJ TjBfTU9ERTEJCTB4MGUwCkBAIC0yMDEsNiArMjAyLDcgQEAKICNkZWZpbmUgUVNFUkRFU19WM19D T01fREVCVUdfQlVTMgkJCTB4MTcwCiAjZGVmaW5lIFFTRVJERVNfVjNfQ09NX0RFQlVHX0JVUzMJ CQkweDE3NAogI2RlZmluZSBRU0VSREVTX1YzX0NPTV9ERUJVR19CVVNfU0VMCQkJMHgxNzgKKyNk ZWZpbmUgUVNFUkRFU19WM19DT01fQ01OX01PREUJCQkJMHgxODQKIAogLyogT25seSBmb3IgUU1Q IFYzIFBIWSAtIFRYIHJlZ2lzdGVycyAqLwogI2RlZmluZSBRU0VSREVTX1YzX1RYX1JFU19DT0RF X0xBTkVfT0ZGU0VUX1RYCQkweDA0NApAQCAtMjExLDYgKzIxMyw3IEBACiAjZGVmaW5lIFFTRVJE RVNfVjNfVFhfUkNWX0RFVEVDVF9MVkxfMgkJCTB4MGE0CiAKIC8qIE9ubHkgZm9yIFFNUCBWMyBQ SFkgLSBSWCByZWdpc3RlcnMgKi8KKyNkZWZpbmUgUVNFUkRFU19WM19SWF9VQ0RSX0ZPX0dBSU4J CQkweDAwOAogI2RlZmluZSBRU0VSREVTX1YzX1JYX1VDRFJfU09fR0FJTl9IQUxGCQkJMHgwMGMK ICNkZWZpbmUgUVNFUkRFU19WM19SWF9VQ0RSX1NPX0dBSU4JCQkweDAxNAogI2RlZmluZSBRU0VS REVTX1YzX1JYX1VDRFJfU1ZTX1NPX0dBSU5fSEFMRgkJMHgwMjQKQEAgLTIxOSw2ICsyMjIsNyBA QAogI2RlZmluZSBRU0VSREVTX1YzX1JYX1VDRFJfRkFTVExPQ0tfRk9fR0FJTgkJMHgwMzAKICNk ZWZpbmUgUVNFUkRFU19WM19SWF9VQ0RSX1NPX1NBVFVSQVRJT05fQU5EX0VOQUJMRQkweDAzNAog I2RlZmluZSBRU0VSREVTX1YzX1JYX1VDRFJfRkFTVExPQ0tfQ09VTlRfTE9XCQkweDAzYworI2Rl ZmluZSBRU0VSREVTX1YzX1JYX1VDRFJfRkFTVExPQ0tfQ09VTlRfSElHSAkJMHgwNDAKICNkZWZp bmUgUVNFUkRFU19WM19SWF9VQ0RSX1BJX0NPTlRST0xTCQkJMHgwNDQKICNkZWZpbmUgUVNFUkRF U19WM19SWF9SWF9URVJNX0JXCQkJMHgwN2MKICNkZWZpbmUgUVNFUkRFU19WM19SWF9WR0FfQ0FM X0NOVFJMMQkJCTB4MGJjCg==