From mboxrd@z Thu Jan 1 00:00:00 1970 From: eugeniy.paltsev@synopsys.com (Eugeniy Paltsev) Date: Tue, 29 Jan 2019 17:25:57 +0000 Subject: [PATCH 1/2] ARCv2: Enable unaligned access in early ASM code In-Reply-To: <3c341dd9-f360-640e-a3c9-3291300d02ae@synopsys.com> References: <20190116112951.10641-1-Eugeniy.Paltsev@synopsys.com> <3c341dd9-f360-640e-a3c9-3291300d02ae@synopsys.com> List-ID: Message-ID: <1548782756.29008.20.camel@synopsys.com> To: linux-snps-arc@lists.infradead.org On Tue, 2019-01-29@09:21 -0800, Vineet Gupta wrote: > On 1/16/19 3:29 AM, Eugeniy Paltsev wrote: > > Even though we do enable AD bit in arc_init_IRQ() we need to do > > it in early ASM code otherwise we may face unaligned data until > > we reach arc_init_IRQ() because GCC starting from v8.1.0 actively > > generates unaligned data as it assumes that: > > * ARCv2 always has support of unaliged data > > * This support is turned on in runtime > > > > Signed-off-by: Eugeniy Paltsev > > --- > > arch/arc/kernel/head.S | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S > > index 8b90d25a15cc..d5b7a572365a 100644 > > --- a/arch/arc/kernel/head.S > > +++ b/arch/arc/kernel/head.S > > @@ -17,6 +17,9 @@ > > #include > > #include > > #include > > +#ifdef CONFIG_ISA_ARCV2 > > +#include > > +#endif > > I presume there is no specific reason to include this conditionally. > irqflags.h already includes the right version. Agree. I've just forgotten about common irqflags.h Will fix in V2. > > > > .macro CPU_EARLY_SETUP > > > > @@ -47,6 +50,13 @@ > > sr r5, [ARC_REG_DC_CTRL] > > > > 1: > > + > > +#ifdef CONFIG_ISA_ARCV2 > > + ; Enable handling of unaligned access in the CPU as by default > > + ; this HW feature is disabled while GCC starting from 8.1.0 > > + ; unconditionally uses it for ARC HS cores. > > + flag 1 << STATUS_AD_BIT > > +#endif > > .endm > > > > .section .init.text, "ax", at progbits > > > > -- Eugeniy Paltsev From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9CABC169C4 for ; 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Tue, 29 Jan 2019 18:25:57 +0100 From: Eugeniy Paltsev To: "Eugeniy.Paltsev@synopsys.com" , "Vineet Gupta" , "linux-snps-arc@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , "alexey.brodkin@synopsys.com" Subject: Re: [PATCH 1/2] ARCv2: Enable unaligned access in early ASM code Thread-Topic: [PATCH 1/2] ARCv2: Enable unaligned access in early ASM code Thread-Index: AQHUrY7S1r2HqQHrAUmKrUzEXiBQFaXGgk+AgAABMgA= Date: Tue, 29 Jan 2019 17:25:57 +0000 Message-ID: <1548782756.29008.20.camel@synopsys.com> References: <20190116112951.10641-1-Eugeniy.Paltsev@synopsys.com> <3c341dd9-f360-640e-a3c9-3291300d02ae@synopsys.com> In-Reply-To: <3c341dd9-f360-640e-a3c9-3291300d02ae@synopsys.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.121.8.46] Content-Type: text/plain; charset="utf-8" Content-ID: <8F6D8FD84281D84CB117EC3F745A1C6B@internal.synopsys.com> Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org T24gVHVlLCAyMDE5LTAxLTI5IGF0IDA5OjIxIC0wODAwLCBWaW5lZXQgR3VwdGEgd3JvdGU6DQo+ IE9uIDEvMTYvMTkgMzoyOSBBTSwgRXVnZW5peSBQYWx0c2V2IHdyb3RlOg0KPiA+IEV2ZW4gdGhv dWdoIHdlIGRvIGVuYWJsZSBBRCBiaXQgaW4gYXJjX2luaXRfSVJRKCkgd2UgbmVlZCB0byBkbw0K PiA+IGl0IGluIGVhcmx5IEFTTSBjb2RlIG90aGVyd2lzZSB3ZSBtYXkgZmFjZSB1bmFsaWduZWQg ZGF0YSB1bnRpbA0KPiA+IHdlIHJlYWNoIGFyY19pbml0X0lSUSgpIGJlY2F1c2UgR0NDIHN0YXJ0 aW5nIGZyb20gdjguMS4wIGFjdGl2ZWx5DQo+ID4gZ2VuZXJhdGVzIHVuYWxpZ25lZCBkYXRhIGFz IGl0IGFzc3VtZXMgdGhhdDoNCj4gPiAgKiBBUkN2MiBhbHdheXMgaGFzIHN1cHBvcnQgb2YgdW5h bGlnZWQgZGF0YQ0KPiA+ICAqIFRoaXMgc3VwcG9ydCBpcyB0dXJuZWQgb24gaW4gcnVudGltZQ0K PiA+IA0KPiA+IFNpZ25lZC1vZmYtYnk6IEV1Z2VuaXkgUGFsdHNldiA8RXVnZW5peS5QYWx0c2V2 QHN5bm9wc3lzLmNvbT4NCj4gPiAtLS0NCj4gPiAgYXJjaC9hcmMva2VybmVsL2hlYWQuUyB8IDEw ICsrKysrKysrKysNCj4gPiAgMSBmaWxlIGNoYW5nZWQsIDEwIGluc2VydGlvbnMoKykNCj4gPiAN Cj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcmMva2VybmVsL2hlYWQuUyBiL2FyY2gvYXJjL2tlcm5l bC9oZWFkLlMNCj4gPiBpbmRleCA4YjkwZDI1YTE1Y2MuLmQ1YjdhNTcyMzY1YSAxMDA2NDQNCj4g PiAtLS0gYS9hcmNoL2FyYy9rZXJuZWwvaGVhZC5TDQo+ID4gKysrIGIvYXJjaC9hcmMva2VybmVs L2hlYWQuUw0KPiA+IEBAIC0xNyw2ICsxNyw5IEBADQo+ID4gICNpbmNsdWRlIDxhc20vZW50cnku aD4NCj4gPiAgI2luY2x1ZGUgPGFzbS9hcmNyZWdzLmg+DQo+ID4gICNpbmNsdWRlIDxhc20vY2Fj aGUuaD4NCj4gPiArI2lmZGVmIENPTkZJR19JU0FfQVJDVjINCj4gPiArI2luY2x1ZGUgPGFzbS9p cnFmbGFncy1hcmN2Mi5oPg0KPiA+ICsjZW5kaWYNCj4gDQo+IEkgcHJlc3VtZSB0aGVyZSBpcyBu byBzcGVjaWZpYyByZWFzb24gdG8gaW5jbHVkZSB0aGlzIGNvbmRpdGlvbmFsbHkuDQo+IGlycWZs YWdzLmggYWxyZWFkeSBpbmNsdWRlcyB0aGUgcmlnaHQgdmVyc2lvbi4NCg0KQWdyZWUuDQpJJ3Zl IGp1c3QgZm9yZ290dGVuIGFib3V0IGNvbW1vbiBpcnFmbGFncy5oDQoNCldpbGwgZml4IGluIFYy Lg0KDQo+ID4gIA0KPiA+ICAubWFjcm8gQ1BVX0VBUkxZX1NFVFVQDQo+ID4gIA0KPiA+IEBAIC00 Nyw2ICs1MCwxMyBAQA0KPiA+ICAJc3IJcjUsIFtBUkNfUkVHX0RDX0NUUkxdDQo+ID4gIA0KPiA+ ICAxOg0KPiA+ICsNCj4gPiArI2lmZGVmIENPTkZJR19JU0FfQVJDVjINCj4gPiArCTsgRW5hYmxl IGhhbmRsaW5nIG9mIHVuYWxpZ25lZCBhY2Nlc3MgaW4gdGhlIENQVSBhcyBieSBkZWZhdWx0DQo+ ID4gKwk7IHRoaXMgSFcgZmVhdHVyZSBpcyBkaXNhYmxlZCB3aGlsZSBHQ0Mgc3RhcnRpbmcgZnJv bSA4LjEuMA0KPiA+ICsJOyB1bmNvbmRpdGlvbmFsbHkgdXNlcyBpdCBmb3IgQVJDIEhTIGNvcmVz Lg0KPiA+ICsJZmxhZyAgICAxIDw8IFNUQVRVU19BRF9CSVQNCj4gPiArI2VuZGlmDQo+ID4gIC5l bmRtDQo+ID4gIA0KPiA+ICAJLnNlY3Rpb24gLmluaXQudGV4dCwgImF4IixAcHJvZ2JpdHMNCj4g PiANCj4gDQo+IA0KLS0gDQogRXVnZW5peSBQYWx0c2V2