From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [RFC PATCH v1 06/15] drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets Date: Fri, 1 Mar 2019 12:38:28 -0700 Message-ID: <1551469117-3404-7-git-send-email-jcrouse@codeaurora.org> References: <1551469117-3404-1-git-send-email-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1551469117-3404-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Kees Cook , jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sharat Masetty , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, David Airlie , Rob Clark , dianders-uWgjrcJnOmJ4cg9Nei1l7Q@public.gmane.org, hoegsberg-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, Mamta Shukla , Thomas Zimmermann , Daniel Vetter , Sean Paul , baolu.lu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org QTVYWCBhbmQgbmV3ZXIgR1BVcyBjYW4gYmUgcnVuIGluIGVpdGhlciAzMiBvciA2NCBiaXQgbW9k ZS4gVGhlIEdQVQpyZWdpc3RlcnMgYW5kIHRoZSBtaWNyb2NvZGUgdXNlIDY0IGJpdCB2aXJ0dWFs IGFkZHJlc3NpbmcgaW4gZWl0aGVyCmNhc2UgYnV0IHRoZSB1cHBlciAzMiBiaXRzIGFyZSBpZ25v cmVkIGlmIHRoZSBHUFUgaXMgaW4gMzIgYml0IG1vZGUuClRoZXJlIGlzIG5vIHBlcmZvcm1hbmNl IGRpc2FkdmFudGFnZSB0byByZW1haW5pbmcgaW4gNjQgYml0IG1vZGUgZXZlbgppZiB3ZSBhcmUg b25seSBnZW5lcmF0aW5nIDMyIGJpdCBhZGRyZXNzZXMgc28gc3dpdGNoIG92ZXIgbm93IHRvIHBy ZXBhcmUKZm9yIHVzaW5nIGFkZHJlc3NlcyBhYm92ZSA0RyBmb3IgdGFyZ2V0cyB0aGF0IHN1cHBv cnQgdGhlbS4KClNpZ25lZC1vZmYtYnk6IEpvcmRhbiBDcm91c2UgPGpjcm91c2VAY29kZWF1cm9y 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[198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 777E5C43381 for ; Fri, 1 Mar 2019 19:39:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 40A4120838 for ; Fri, 1 Mar 2019 19:39:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="OZqiQv0l"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="TERRJi0p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727297AbfCATjA (ORCPT ); Fri, 1 Mar 2019 14:39:00 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39528 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727022AbfCATi5 (ORCPT ); Fri, 1 Mar 2019 14:38:57 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 00018615B0; Fri, 1 Mar 2019 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b=TERRJi0pV4QrTlgKLv2J32zc8OI+sYiUuMA8PKz/9jT0PZ26PC3kfVPtBqInhrsgv JWo/7VFKKHV6UI8x0a/ujgWQptVwTlK/SKqzg5EGr/3IN2N65/NC+dw5FEugLJoty2 TkeQjfFKH/jfjiQwcyihZ/dbke9TvZ53JXUWsnZg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 01976611CE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: jean-philippe.brucker@arm.com, linux-arm-msm@vger.kernel.org, dianders@chromimum.org, hoegsberg@google.com, baolu.lu@linux.intel.com, Sean Paul , Kees Cook , Thomas Zimmermann , Sharat Masetty , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , David Airlie , Mamta Shukla , Daniel Vetter Subject: [RFC PATCH v1 06/15] drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets Date: Fri, 1 Mar 2019 12:38:28 -0700 Message-Id: <1551469117-3404-7-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551469117-3404-1-git-send-email-jcrouse@codeaurora.org> References: <1551469117-3404-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A5XX and newer GPUs can be run in either 32 or 64 bit mode. The GPU registers and the microcode use 64 bit virtual addressing in either case but the upper 32 bits are ignored if the GPU is in 32 bit mode. There is no performance disadvantage to remaining in 64 bit mode even if we are only generating 32 bit addresses so switch over now to prepare for using addresses above 4G for targets that support them. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index d5f5e56..45662d3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -749,6 +749,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu) REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); + /* Put the GPU into 64 bit by default */ + gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); + ret = adreno_hw_init(gpu); if (ret) return ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index fefe773..1c20d59 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -375,6 +375,20 @@ static int a6xx_hw_init(struct msm_gpu *gpu) REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); + /* Turn on 64 bit addressing for all blocks */ + gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); + /* enable hardware clockgating */ a6xx_set_hwcg(gpu, true); -- 2.7.4