From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 4/4] ARM: socfpga: Fix A10 SoCDK Kconfig
Date: Fri, 8 Mar 2019 04:33:00 +0000 [thread overview]
Message-ID: <1552019580.9843.6.camel@intel.com> (raw)
In-Reply-To: <20190306210534.9365-4-marex@denx.de>
On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote:
> The Kconfig checked for SoCFPGA Arria10 as a platform, instead of
> checking for specific board configuration, which works with one
> single platform in tree, but not with multiple. Fix it.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> board/altera/arria10-socdk/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/altera/arria10-socdk/Kconfig
> b/board/altera/arria10-socdk/Kconfig
> index b80cc6d6f9..621dc97024 100644
> --- a/board/altera/arria10-socdk/Kconfig
> +++ b/board/altera/arria10-socdk/Kconfig
> @@ -1,4 +1,4 @@
> -if TARGET_SOCFPGA_ARRIA10
> +if TARGET_SOCFPGA_ARRIA10_SOCDK
>
> config SYS_CPU
> default "armv7"
next prev parent reply other threads:[~2019-03-08 4:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-06 21:05 [U-Boot] [PATCH 1/4] ARM: socfpga: Disable D cache in SPL Marek Vasut
2019-03-06 21:05 ` [U-Boot] [PATCH 2/4] ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POS Marek Vasut
2019-03-08 3:54 ` Chee, Tien Fong
2019-03-06 21:05 ` [U-Boot] [PATCH 3/4] ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset Marek Vasut
2019-03-07 8:15 ` Simon Goldschmidt
2019-03-06 21:05 ` [U-Boot] [PATCH 4/4] ARM: socfpga: Fix A10 SoCDK Kconfig Marek Vasut
2019-03-08 4:33 ` Chee, Tien Fong [this message]
2019-03-08 3:43 ` [U-Boot] [PATCH 1/4] ARM: socfpga: Disable D cache in SPL Chee, Tien Fong
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