From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH v1 2/4] drm/msm/a6xx: Add zap shader load Date: Tue, 12 Mar 2019 12:13:40 -0600 Message-ID: <1552414422-9568-3-git-send-email-jcrouse@codeaurora.org> References: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1552414422-9568-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Jonathan Marek , Arnd Bergmann , David Airlie , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Bjorn Andersson , Rob Clark , Mamta Shukla , Thomas Zimmermann , Daniel Vetter , Sean Paul , Daniel Mack List-Id: linux-arm-msm@vger.kernel.org VGhlIGE2eHggR1BVIHBvd2VycyBvbiBpbiBzZWN1cmUgbW9kZSB3aGljaCByZXN0cmljdHMgd2hh dCBtZW1vcnkgaXQgY2FuCndyaXRlIHRvLiBUbyBnZXQgb3V0IG9mIHNlY3VyZSBtb2RlIHRoZSBH UFUgZHJpdmVyIGNhbiB3cml0ZSB0bwpSRUdfQTZYWF9SQkJNX1NFQ1ZJRF9UUlVTVF9DTlRMIGJ1 dCBvbiB0YXJnZXRzIHRoYXQgYXJlICJzZWN1cmUiIHRoYXQKcmVnaXN0ZXIgcmVnaW9uIGlzIGJs b2NrZWQgYW5kIHdyaXRlcyB3aWxsIGNhdXNlIHRoZSBzeXN0ZW0gdG8gZ28gZG93bi4KCkZvciB0 aG9zZSB0YXJnZXRzIHdlIG5lZWQgdG8gZXhlY3V0ZSBhIHNwZWNpYWwgc2VxdWVuY2UgdGhhdCBp bnZvbHZlcwpsb2FkaW5nYSBzcGVjaWFsIHNoYWRlciB0aGF0IGNsZWFycyB0aGUgR1BVIHJlZ2lz dGVycyBhbmQgdXNlIGEgUE00CnNlcXVlbmNlIHRvIHB1bGwgdGhlIEdQVSBvdXQgb2Ygc2VjdXJl LiBBZGQgc3VwcG9ydCBmb3IgbG9hZGluZyB0aGUgemFwCnNoYWRlciBhbmQgZXhlY3V0aW5nIHRo ZSBzZWN1cmUgc2VxdWVuY2UuIEZvciB0YXJnZXRzIHRoYXQgZG8gbm90IHN1cHBvcnQKU0NNIG9y IHRoZSBzcGVjaWZpYyBTQ00gc2VxdWVuY2UgdGhpcyBzaG91bGQgZmFpbCBhbmQgd2Ugd291bGQg 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autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAD1AC43381 for ; Tue, 12 Mar 2019 18:14:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 91629213A2 for ; Tue, 12 Mar 2019 18:14:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="M3ehYlM3"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="NHINJMBr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727710AbfCLSOh (ORCPT ); Tue, 12 Mar 2019 14:14:37 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58244 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727522AbfCLSOQ (ORCPT ); Tue, 12 Mar 2019 14:14:16 -0400 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NHINJMBrQ0nIJTVSwRpCmKbfxfoKgfYSE2MAJhuC3lVNa2ZAcXEygzmoqtAk6GsgF KgfdQEgjVEvMXyUqdsiQxr+0RYXn0J9kV5ISd80p6z/HfbjiNtFUw/2b9KqJ3XsVkB WE7+3leoW/0oglufdV7Q3Cz1f6j72CswhobHqy0Q= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CCF87619D0 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: Bjorn Andersson , Arnd Bergmann , Sean Paul , Thomas Zimmermann , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Clark , David Airlie , Jonathan Marek , Daniel Mack , Mamta Shukla , Daniel Vetter Subject: [PATCH v1 2/4] drm/msm/a6xx: Add zap shader load Date: Tue, 12 Mar 2019 12:13:40 -0600 Message-Id: <1552414422-9568-3-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> References: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The a6xx GPU powers on in secure mode which restricts what memory it can write to. To get out of secure mode the GPU driver can write to REG_A6XX_RBBM_SECVID_TRUST_CNTL but on targets that are "secure" that register region is blocked and writes will cause the system to go down. For those targets we need to execute a special sequence that involves loadinga special shader that clears the GPU registers and use a PM4 sequence to pull the GPU out of secure. Add support for loading the zap shader and executing the secure sequence. For targets that do not support SCM or the specific SCM sequence this should fail and we would fall back to writing the register. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index fefe773..5983e47 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,8 @@ #include +#define GPU_PAS_ID 13 + static inline bool _a6xx_check_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -343,6 +345,20 @@ static int a6xx_ucode_init(struct msm_gpu *gpu) return 0; } +static int a6xx_zap_shader_init(struct msm_gpu *gpu) +{ + static bool loaded; + int ret; + + if (loaded) + return 0; + + ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); + + loaded = !ret; + return ret; +} + #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ @@ -491,7 +507,27 @@ static int a6xx_hw_init(struct msm_gpu *gpu) if (ret) goto out; - gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); + /* + * Try to load a zap shader into the secure world. If successful + * we can use the CP to switch out of secure mode. If not then we + * have no resource but to try to switch ourselves out manually. If we + * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will + * be blocked and a permissions violation will soon follow. + */ + ret = a6xx_zap_shader_init(gpu); + if (!ret) { + OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); + OUT_RING(gpu->rb[0], 0x00000000); + + a6xx_flush(gpu, gpu->rb[0]); + if (!a6xx_idle(gpu, gpu->rb[0])) + return -EINVAL; + } else { + /* Print a warning so if we die, we know why */ + dev_warn_once(gpu->dev->dev, + "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); + } out: /* diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 714ed65..ead5f6a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -155,6 +155,7 @@ static const struct adreno_info gpulist[] = { .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, + .zapfw = "a630_zap.mdt", }, }; -- 2.7.4