From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A24F4C10F05 for ; Fri, 29 Mar 2019 12:28:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6759B2183E for ; Fri, 29 Mar 2019 12:28:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="qQNTE8hf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6759B2183E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=st.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=wUn7t3NnSPs5aLcT3gxERj6PudomqEZgLNHTJdCU2Xc=; b=qQNTE8hfRdAyYB fqjGocgfKg605O43u8bmaUUE6HlFVNiibLMkIMG7tSKlXtJpanRz7ddgwOdIiOyMOUAjZjAWhtibR HKchNSVpZV48JFQXpQKmoWstvth1al3hj6kyBIiTMy75IFWKP3cF5v68vywreofGgiASYiR+Qa9Hh aFSVt+BVEN8xTffWgvcmyvS0DltZGwBdLECLG4i/mUUQZd+QwuBlzosoKJb3oaC+bl4TkzLOZUFEl ZUfoWa8x08YT9SAmeB5gw3WtotuZjsKmy98AoDS4flDhprr/1rehmAGYSkU+88G2WcvMbhZw634X+ EbXsikIRVqnWqusN+zpw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h9qcV-0003ct-Hs; Fri, 29 Mar 2019 12:28:27 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h9qcQ-0003c6-M9 for linux-arm-kernel@lists.infradead.org; Fri, 29 Mar 2019 12:28:25 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2TCSEkH018895; Fri, 29 Mar 2019 13:28:14 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2rf4ycg19d-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 29 Mar 2019 13:28:14 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CE0B931; Fri, 29 Mar 2019 12:28:12 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A728C2A0A; Fri, 29 Mar 2019 12:28:12 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 29 Mar 2019 13:28:12 +0100 Received: from localhost (10.201.23.97) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.435.0; Fri, 29 Mar 2019 13:28:12 +0100 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= To: Maxime Coquelin , Alexandre Torgue , Rob Herring , Mark Rutland , , , , , Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Fabrice Gasnier Subject: [PATCH] ARM: dts: stm32: add ltdc pins muxing on stm32mp157 Date: Fri, 29 Mar 2019 13:27:55 +0100 Message-ID: <1553862475-5956-1-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-29_07:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190329_052823_009927_E0414E99 X-CRM114-Status: UNSURE ( 8.58 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org QWRkIGx0ZGMgcGlucyBtdXhpbmcgb24gc3RtMzJtcDE1Ny4KClNpZ25lZC1vZmYtYnk6IFlhbm5p Y2sgRmVydHLDqSA8eWFubmljay5mZXJ0cmVAc3QuY29tPgotLS0KIGFyY2gvYXJtL2Jvb3QvZHRz L3N0bTMybXAxNTctcGluY3RybC5kdHNpIHwgMTM4ICsrKysrKysrKysrKysrKysrKysrKysrKysr KysrKwogMSBmaWxlIGNoYW5nZWQsIDEzOCBpbnNlcnRpb25zKCspCgpkaWZmIC0tZ2l0IGEvYXJj aC9hcm0vYm9vdC9kdHMvc3RtMzJtcDE1Ny1waW5jdHJsLmR0c2kgYi9hcmNoL2FybS9ib290L2R0 cy9zdG0zMm1wMTU3LXBpbmN0cmwuZHRzaQppbmRleCA5MTA0ODk2Li5kYTRiNDExIDEwMDY0NAot LS0gYS9hcmNoL2FybS9ib290L2R0cy9zdG0zMm1wMTU3LXBpbmN0cmwuZHRzaQorKysgYi9hcmNo L2FybS9ib290L2R0cy9zdG0zMm1wMTU3LXBpbmN0cmwuZHRzaQpAQCAtMjMzLDYgKzIzMywxNDQg QEAKIAkJCQl9OwogCQkJfTsKIAorCQkJbHRkY19waW5zX2E6IGx0ZGMtYS0wIHsKKwkJCQlwaW5z IHsKKwkJCQkJcGlubXV4ID0gPFNUTTMyX1BJTk1VWCgnRycsICA3LCBBRjE0KT4sIC8qIExDRF9D TEsgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdJJywgMTAsIEFGMTQpPiwgLyogTENEX0hTWU5D ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSScsICA5LCBBRjE0KT4sIC8qIExDRF9WU1lOQyAq LworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0YnLCAxMCwgQUYxNCk+LCAvKiBMQ0RfREUgKi8KKwkJ CQkJCSA8U1RNMzJfUElOTVVYKCdIJywgIDIsIEFGMTQpPiwgLyogTENEX1IwICovCisJCQkJCQkg PFNUTTMyX1BJTk1VWCgnSCcsICAzLCBBRjE0KT4sIC8qIExDRF9SMSAqLworCQkJCQkJIDxTVE0z Ml9QSU5NVVgoJ0gnLCAgOCwgQUYxNCk+LCAvKiBMQ0RfUjIgKi8KKwkJCQkJCSA8U1RNMzJfUElO TVVYKCdIJywgIDksIEFGMTQpPiwgLyogTENEX1IzICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgn SCcsIDEwLCBBRjE0KT4sIC8qIExDRF9SNCAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0MnLCAg MCwgQUYxNCk+LCAvKiBMQ0RfUjUgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdIJywgMTIsIEFG MTQpPiwgLyogTENEX1I2ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnRScsIDE1LCBBRjE0KT4s IC8qIExDRF9SNyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0UnLCAgNSwgQUYxNCk+LCAvKiBM Q0RfRzAgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdFJywgIDYsIEFGMTQpPiwgLyogTENEX0cx ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSCcsIDEzLCBBRjE0KT4sIC8qIExDRF9HMiAqLwor CQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0gnLCAxNCwgQUYxNCk+LCAvKiBMQ0RfRzMgKi8KKwkJCQkJ CSA8U1RNMzJfUElOTVVYKCdIJywgMTUsIEFGMTQpPiwgLyogTENEX0c0ICovCisJCQkJCQkgPFNU TTMyX1BJTk1VWCgnSScsICAwLCBBRjE0KT4sIC8qIExDRF9HNSAqLworCQkJCQkJIDxTVE0zMl9Q SU5NVVgoJ0knLCAgMSwgQUYxNCk+LCAvKiBMQ0RfRzYgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVY KCdJJywgIDIsIEFGMTQpPiwgLyogTENEX0c3ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnRCcs ICA5LCBBRjE0KT4sIC8qIExDRF9CMCAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0cnLCAxMiwg QUYxNCk+LCAvKiBMQ0RfQjEgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdHJywgMTAsIEFGMTQp PiwgLyogTENEX0IyICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnRCcsIDEwLCBBRjE0KT4sIC8q IExDRF9CMyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAgNCwgQUYxNCk+LCAvKiBMQ0Rf QjQgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdBJywgIDMsIEFGMTQpPiwgLyogTENEX0I1ICov CisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnQicsICA4LCBBRjE0KT4sIC8qIExDRF9CNiAqLworCQkJ CQkJIDxTVE0zMl9QSU5NVVgoJ0QnLCAgOCwgQUYxNCk+OyAvKiBMQ0RfQjcgKi8KKwkJCQkJYmlh cy1kaXNhYmxlOworCQkJCQlkcml2ZS1wdXNoLXB1bGw7CisJCQkJCXNsZXctcmF0ZSA9IDwxPjsK KwkJCQl9OworCQkJfTsKKworCQkJbHRkY19waW5zX3NsZWVwX2E6IGx0ZGMtYS0xIHsKKwkJCQlw aW5zIHsKKwkJCQkJcGlubXV4ID0gPFNUTTMyX1BJTk1VWCgnRycsICA3LCBBTkFMT0cpPiwgLyog TENEX0NMSyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAxMCwgQU5BTE9HKT4sIC8qIExD RF9IU1lOQyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAgOSwgQU5BTE9HKT4sIC8qIExD RF9WU1lOQyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0YnLCAxMCwgQU5BTE9HKT4sIC8qIExD RF9ERSAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0gnLCAgMiwgQU5BTE9HKT4sIC8qIExDRF9S MCAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0gnLCAgMywgQU5BTE9HKT4sIC8qIExDRF9SMSAq LworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0gnLCAgOCwgQU5BTE9HKT4sIC8qIExDRF9SMiAqLwor CQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0gnLCAgOSwgQU5BTE9HKT4sIC8qIExDRF9SMyAqLworCQkJ CQkJIDxTVE0zMl9QSU5NVVgoJ0gnLCAxMCwgQU5BTE9HKT4sIC8qIExDRF9SNCAqLworCQkJCQkJ IDxTVE0zMl9QSU5NVVgoJ0MnLCAgMCwgQU5BTE9HKT4sIC8qIExDRF9SNSAqLworCQkJCQkJIDxT VE0zMl9QSU5NVVgoJ0gnLCAxMiwgQU5BTE9HKT4sIC8qIExDRF9SNiAqLworCQkJCQkJIDxTVE0z Ml9QSU5NVVgoJ0UnLCAxNSwgQU5BTE9HKT4sIC8qIExDRF9SNyAqLworCQkJCQkJIDxTVE0zMl9Q SU5NVVgoJ0UnLCAgNSwgQU5BTE9HKT4sIC8qIExDRF9HMCAqLworCQkJCQkJIDxTVE0zMl9QSU5N VVgoJ0UnLCAgNiwgQU5BTE9HKT4sIC8qIExDRF9HMSAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgo J0gnLCAxMywgQU5BTE9HKT4sIC8qIExDRF9HMiAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0gn LCAxNCwgQU5BTE9HKT4sIC8qIExDRF9HMyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0gnLCAx NSwgQU5BTE9HKT4sIC8qIExDRF9HNCAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAgMCwg QU5BTE9HKT4sIC8qIExDRF9HNSAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAgMSwgQU5B TE9HKT4sIC8qIExDRF9HNiAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAgMiwgQU5BTE9H KT4sIC8qIExDRF9HNyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0QnLCAgOSwgQU5BTE9HKT4s IC8qIExDRF9CMCAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0cnLCAxMiwgQU5BTE9HKT4sIC8q IExDRF9CMSAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0cnLCAxMCwgQU5BTE9HKT4sIC8qIExD RF9CMiAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0QnLCAxMCwgQU5BTE9HKT4sIC8qIExDRF9C MyAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAgNCwgQU5BTE9HKT4sIC8qIExDRF9CNCAq LworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0EnLCAgMywgQU5BTE9HKT4sIC8qIExDRF9CNSAqLwor CQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0InLCAgOCwgQU5BTE9HKT4sIC8qIExDRF9CNiAqLworCQkJ CQkJIDxTVE0zMl9QSU5NVVgoJ0QnLCAgOCwgQU5BTE9HKT47IC8qIExDRF9CNyAqLworCQkJCX07 CisJCQl9OworCisJCQlsdGRjX3BpbnNfYjogbHRkYy1iLTAgeworCQkJCXBpbnMgeworCQkJCQlw aW5tdXggPSA8U1RNMzJfUElOTVVYKCdJJywgMTQsIEFGMTQpPiwgLyogTENEX0NMSyAqLworCQkJ CQkJIDxTVE0zMl9QSU5NVVgoJ0knLCAxMiwgQUYxNCk+LCAvKiBMQ0RfSFNZTkMgKi8KKwkJCQkJ CSA8U1RNMzJfUElOTVVYKCdJJywgMTMsIEFGMTQpPiwgLyogTENEX1ZTWU5DICovCisJCQkJCQkg PFNUTTMyX1BJTk1VWCgnSycsICA3LCBBRjE0KT4sIC8qIExDRF9ERSAqLworCQkJCQkJIDxTVE0z Ml9QSU5NVVgoJ0knLCAxNSwgQUYxNCk+LCAvKiBMQ0RfUjAgKi8KKwkJCQkJCSA8U1RNMzJfUElO TVVYKCdKJywgIDAsIEFGMTQpPiwgLyogTENEX1IxICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgn SicsICAxLCBBRjE0KT4sIC8qIExDRF9SMiAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0onLCAg MiwgQUYxNCk+LCAvKiBMQ0RfUjMgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdKJywgIDMsIEFG MTQpPiwgLyogTENEX1I0ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsICA0LCBBRjE0KT4s IC8qIExDRF9SNSAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0onLCAgNSwgQUYxNCk+LCAvKiBM Q0RfUjYgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdKJywgIDYsIEFGMTQpPiwgLyogTENEX1I3 ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsICA3LCBBRjE0KT4sIC8qIExDRF9HMCAqLwor CQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0onLCAgOCwgQUYxNCk+LCAvKiBMQ0RfRzEgKi8KKwkJCQkJ CSA8U1RNMzJfUElOTVVYKCdKJywgIDksIEFGMTQpPiwgLyogTENEX0cyICovCisJCQkJCQkgPFNU TTMyX1BJTk1VWCgnSicsIDEwLCBBRjE0KT4sIC8qIExDRF9HMyAqLworCQkJCQkJIDxTVE0zMl9Q SU5NVVgoJ0onLCAxMSwgQUYxNCk+LCAvKiBMQ0RfRzQgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVY KCdLJywgIDAsIEFGMTQpPiwgLyogTENEX0c1ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSycs ICAxLCBBRjE0KT4sIC8qIExDRF9HNiAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0snLCAgMiwg QUYxNCk+LCAvKiBMQ0RfRzcgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdKJywgMTIsIEFGMTQp PiwgLyogTENEX0IwICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsIDEzLCBBRjE0KT4sIC8q IExDRF9CMSAqLworCQkJCQkJIDxTVE0zMl9QSU5NVVgoJ0onLCAxNCwgQUYxNCk+LCAvKiBMQ0Rf QjIgKi8KKwkJCQkJCSA8U1RNMzJfUElOTVVYKCdKJywgMTUsIEFGMTQpPiwgLyogTENEX0IzICov CisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSycsICAzLCBBRjE0KT4sIC8qIExDRF9CNCAqLworCQkJ CQkJIDxTVE0zMl9QSU5NVVgoJ0snLCAgNCwgQUYxNCk+LCAvKiBMQ0RfQjUgKi8KKwkJCQkJCSA8 U1RNMzJfUElOTVVYKCdLJywgIDUsIEFGMTQpPiwgLyogTENEX0I2ICovCisJCQkJCQkgPFNUTTMy X1BJTk1VWCgnSycsICA2LCBBRjE0KT47IC8qIExDRF9CNyAqLworCQkJCQliaWFzLWRpc2FibGU7 CisJCQkJCWRyaXZlLXB1c2gtcHVsbDsKKwkJCQkJc2xldy1yYXRlID0gPDE+OworCQkJCX07CisJ CQl9OworCisJCQlsdGRjX3BpbnNfc2xlZXBfYjogbHRkYy1iLTEgeworCQkJCXBpbnMgeworCQkJ CQlwaW5tdXggPSA8U1RNMzJfUElOTVVYKCdJJywgMTQsIEFOQUxPRyk+LCAvKiBMQ0RfQ0xLICov CisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSScsIDEyLCBBTkFMT0cpPiwgLyogTENEX0hTWU5DICov CisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSScsIDEzLCBBTkFMT0cpPiwgLyogTENEX1ZTWU5DICov CisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSycsICA3LCBBTkFMT0cpPiwgLyogTENEX0RFICovCisJ CQkJCQkgPFNUTTMyX1BJTk1VWCgnSScsIDE1LCBBTkFMT0cpPiwgLyogTENEX1IwICovCisJCQkJ CQkgPFNUTTMyX1BJTk1VWCgnSicsICAwLCBBTkFMT0cpPiwgLyogTENEX1IxICovCisJCQkJCQkg PFNUTTMyX1BJTk1VWCgnSicsICAxLCBBTkFMT0cpPiwgLyogTENEX1IyICovCisJCQkJCQkgPFNU TTMyX1BJTk1VWCgnSicsICAyLCBBTkFMT0cpPiwgLyogTENEX1IzICovCisJCQkJCQkgPFNUTTMy X1BJTk1VWCgnSicsICAzLCBBTkFMT0cpPiwgLyogTENEX1I0ICovCisJCQkJCQkgPFNUTTMyX1BJ Tk1VWCgnSicsICA0LCBBTkFMT0cpPiwgLyogTENEX1I1ICovCisJCQkJCQkgPFNUTTMyX1BJTk1V WCgnSicsICA1LCBBTkFMT0cpPiwgLyogTENEX1I2ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgn SicsICA2LCBBTkFMT0cpPiwgLyogTENEX1I3ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSics ICA3LCBBTkFMT0cpPiwgLyogTENEX0cwICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsICA4 LCBBTkFMT0cpPiwgLyogTENEX0cxICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsICA5LCBB TkFMT0cpPiwgLyogTENEX0cyICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsIDEwLCBBTkFM T0cpPiwgLyogTENEX0czICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsIDExLCBBTkFMT0cp PiwgLyogTENEX0c0ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSycsICAwLCBBTkFMT0cpPiwg LyogTENEX0c1ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSycsICAxLCBBTkFMT0cpPiwgLyog TENEX0c2ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSycsICAyLCBBTkFMT0cpPiwgLyogTENE X0c3ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsIDEyLCBBTkFMT0cpPiwgLyogTENEX0Iw ICovCisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsIDEzLCBBTkFMT0cpPiwgLyogTENEX0IxICov CisJCQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsIDE0LCBBTkFMT0cpPiwgLyogTENEX0IyICovCisJ CQkJCQkgPFNUTTMyX1BJTk1VWCgnSicsIDE1LCBBTkFMT0cpPiwgLyogTENEX0IzICovCisJCQkJ CQkgPFNUTTMyX1BJTk1VWCgnSycsICAzLCBBTkFMT0cpPiwgLyogTENEX0I0ICovCisJCQkJCQkg PFNUTTMyX1BJTk1VWCgnSycsICA0LCBBTkFMT0cpPiwgLyogTENEX0I1ICovCisJCQkJCQkgPFNU TTMyX1BJTk1VWCgnSycsICA1LCBBTkFMT0cpPiwgLyogTENEX0I2ICovCisJCQkJCQkgPFNUTTMy X1BJTk1VWCgnSycsICA2LCBBTkFMT0cpPjsgLyogTENEX0I3ICovCisJCQkJfTsKKwkJCX07CisK IAkJCW1fY2FuMV9waW5zX2E6IG0tY2FuMS0wIHsKIAkJCQlwaW5zMSB7CiAJCQkJCXBpbm11eCA9 IDxTVE0zMl9QSU5NVVgoJ0gnLCAxMywgQUY5KT47IC8qIENBTjFfVFggKi8KLS0gCjIuNy40CgoK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJt LWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3Jn Cmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtl cm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= Subject: [PATCH] ARM: dts: stm32: add ltdc pins muxing on stm32mp157 Date: Fri, 29 Mar 2019 13:27:55 +0100 Message-ID: <1553862475-5956-1-git-send-email-yannick.fertre@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Return-path: Sender: linux-kernel-owner@vger.kernel.org To: Maxime Coquelin , Alexandre Torgue , Rob Herring , Mark Rutland , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Fabrice Gasnier List-Id: devicetree@vger.kernel.org Add ltdc pins muxing on stm32mp157. Signed-off-by: Yannick Fertré --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 9104896..da4b411 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -233,6 +233,144 @@ }; }; + ltdc_pins_a: ltdc-a-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_a: ltdc-a-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + ltdc_pins_b: ltdc-b-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_b: ltdc-b-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UPPERCASE_50_75, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82FF9C43381 for ; Fri, 29 Mar 2019 12:28:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4EDBC2183F for ; Fri, 29 Mar 2019 12:28:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729516AbfC2M23 (ORCPT ); Fri, 29 Mar 2019 08:28:29 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:56160 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729411AbfC2M22 (ORCPT ); Fri, 29 Mar 2019 08:28:28 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2TCSEkH018895; Fri, 29 Mar 2019 13:28:14 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2rf4ycg19d-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 29 Mar 2019 13:28:14 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CE0B931; Fri, 29 Mar 2019 12:28:12 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A728C2A0A; Fri, 29 Mar 2019 12:28:12 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 29 Mar 2019 13:28:12 +0100 Received: from localhost (10.201.23.97) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.435.0; Fri, 29 Mar 2019 13:28:12 +0100 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= To: Maxime Coquelin , Alexandre Torgue , Rob Herring , Mark Rutland , , , , , Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Fabrice Gasnier Subject: [PATCH] ARM: dts: stm32: add ltdc pins muxing on stm32mp157 Date: Fri, 29 Mar 2019 13:27:55 +0100 Message-ID: <1553862475-5956-1-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-03-29_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add ltdc pins muxing on stm32mp157. Signed-off-by: Yannick Fertré --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 9104896..da4b411 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -233,6 +233,144 @@ }; }; + ltdc_pins_a: ltdc-a-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_a: ltdc-a-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + ltdc_pins_b: ltdc-b-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_b: ltdc-b-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ -- 2.7.4