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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com
Subject: [v2 1/2] drm/i915: Fix GCMAX color register programming
Date: Fri, 29 Mar 2019 19:59:15 +0530	[thread overview]
Message-ID: <1553869756-4546-2-git-send-email-uma.shankar@intel.com> (raw)
In-Reply-To: <1553869756-4546-1-git-send-email-uma.shankar@intel.com>

GC MAX register is used to program values from 1.0 to
less than 3.0. A different register was used instead of
the intended one. Fixed the same.

Currently limiting it to 1.0 due to ABI limitations.

v2: Updated the 1.0 programming and aligned as per GLK, based
on Ville's feedback.

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index ff910ed..c776159 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
 			I915_WRITE(PREC_PAL_DATA(pipe), word);
 		}
 
-		/* Program the max register to clamp values > 1.0. */
-		i = lut_size - 1;
-		I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
-			   drm_color_lut_extract(lut[i].red, 16));
-		I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
-			   drm_color_lut_extract(lut[i].green, 16));
-		I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
-			   drm_color_lut_extract(lut[i].blue, 16));
+		/*
+		 * Program the max register to clamp values > 1.0.
+		 * ToDo: Extend the ABI to be able to program values
+		 * from 1.0 to 3.0
+		 */
+		I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+		I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+		I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
 	} else {
 		for (i = 0; i < lut_size; i++) {
 			u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
 				   (v << 20) | (v << 10) | v);
 		}
 
-		I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
-		I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
-		I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
+		I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+		I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+		I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
 	}
 
 	/*
-- 
1.9.1

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  reply	other threads:[~2019-03-29 14:03 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
2019-03-29 14:29 ` Uma Shankar [this message]
2019-03-29 14:29 ` [v2 2/2] drm/i915: Program EXT2 GC MAX registers Uma Shankar
2019-03-29 14:30 ` [v2 0/2] Fixed GC MAX register programming for gamma luts Lionel Landwerlin
2019-03-29 14:49   ` Shankar, Uma
2019-03-29 14:36 ` ✗ Fi.CI.CHECKPATCH: warning for Fixed GC MAX register programming for gamma luts (rev2) Patchwork
2019-03-29 15:02 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-29 18:17 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-29 18:32 ` [v2 0/2] Fixed GC MAX register programming for gamma luts Ville Syrjälä

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