From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de, acme@kernel.org, jolsa@kernel.org,
eranian@google.com, alexander.shishkin@linux.intel.com,
ak@linux.intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 0/2] perf: Add Tremont support
Date: Wed, 10 Apr 2019 11:57:07 -0700 [thread overview]
Message-ID: <1554922629-126287-1-git-send-email-kan.liang@linux.intel.com> (raw)
From: Kan Liang <kan.liang@linux.intel.com>
The patch series intends to add Tremont support for Linux perf.
The patch series is on top of Icelake V5 patch series (with Peter's cleanup patch).
https://lkml.org/lkml/2019/4/8/630
PATCH 1: A fix for Icelake V5 patch series (with Peter's cleanup patch).
It can be merged back into "Subject: perf/x86/intel: Add Icelake support"
PATCH 2: Tremont core PMU support.
Changes since V1:
- The previous patch "perf/x86/intel: Support adaptive PEBS for fixed counters"
will be merged back.
- New patch to fix the checking for instruction event.
- Allow instruction:ppp on generic purpose counter 0
Kan Liang (2):
perf/x86/intel: Fix the checking for instruction event
perf/x86/intel: Add Tremont core PMU support
arch/x86/events/intel/core.c | 96 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 95 insertions(+), 1 deletion(-)
--
2.7.4
next reply other threads:[~2019-04-10 18:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 18:57 kan.liang [this message]
2019-04-10 18:57 ` [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event kan.liang
2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang
2019-04-11 9:06 ` Peter Zijlstra
2019-04-11 13:30 ` Liang, Kan
2019-04-11 13:33 ` Peter Zijlstra
2019-04-11 14:13 ` Liang, Kan
2019-04-16 11:41 ` [tip:perf/core] " tip-bot for Kan Liang
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