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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
Date: Mon, 6 May 2019 03:36:58 +0000	[thread overview]
Message-ID: <1557113818.10055.3.camel@intel.com> (raw)
In-Reply-To: <6dbdb9b5-0eff-a6cf-973d-f9cd5e84c8b3@gmail.com>

On Sat, 2019-04-27 at 21:34 +0200, Simon Goldschmidt wrote:
> 
> On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Ensure the watchdog is reset timely on each status polling.
> I would have expected a longer commit message here explaining why
> this 
> is done, and from where, where to, and why the watchdog reset has
> been 
> moved.
> 
> Anyway, I don't want to hold back this series again for this, but
> please 
> next time: write longer commit messages. Better write too much than
> risk 
> someone in the future doesn't get what or why you did things.
> 
> Thanks,
> Simon
> 
I will improve the commit messages in next version patch set.

Thanks.
> > 
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > ---
> > 
> > changes for v12
> > - Improved the commit messages.
> > 
> > changes for v11
> > - No changes.
> > 
> > changes for v10
> > - This patch was split out from [PATCH v10 5/9]
> >    ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
> > ---
> >   drivers/fpga/socfpga_arria10.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index b0abe1955c..9499d1a014 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
> >   			printf("nstatus == 0 while waiting for
> > condone\n");
> >   			return -EPERM;
> >   		}
> > +		WATCHDOG_RESET();
> >   	}
> >   
> >   	if (i == FPGA_TIMEOUT_CNT)
> > @@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
> >   		printf("FPGA: Poll CD failed with error code
> > %d\n", status);
> >   		return -EPERM;
> >   	}
> > -	WATCHDOG_RESET();
> >   
> >   	/* Ensure the FPGA entering user mode */
> >   	status = fpgamgr_program_poll_usermode();
> > 

  parent reply	other threads:[~2019-05-06  3:36 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-19  8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-03-19  8:50 ` [U-Boot] [PATCH v12 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-03-19  8:50 ` [U-Boot] [PATCH v12 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-03-19  8:50 ` [U-Boot] [PATCH v12 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver tien.fong.chee at intel.com
2019-03-19  8:50 ` [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling tien.fong.chee at intel.com
2019-04-27 19:34   ` Simon Goldschmidt
2019-04-30 11:57     ` Chee, Tien Fong
2019-05-06  3:36     ` Chee, Tien Fong [this message]
2019-03-19  8:50 ` [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-04-27 19:57   ` Simon Goldschmidt
2019-04-30 12:09     ` Chee, Tien Fong
2019-04-30 12:24       ` Simon Goldschmidt
2019-05-02  7:49         ` Chee, Tien Fong
2019-05-03 11:26           ` Simon Goldschmidt
2019-05-06  3:36             ` Chee, Tien Fong
2019-05-06  7:14               ` Simon Goldschmidt
2019-03-19  8:50 ` [U-Boot] [PATCH v12 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-03-19  8:50 ` [U-Boot] [PATCH v12 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-03-19  8:50 ` [U-Boot] [PATCH v12 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-03-19  8:50 ` [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-04-27 19:50   ` Simon Goldschmidt
2019-04-30 12:13     ` Chee, Tien Fong
2019-04-30 12:26       ` Simon Goldschmidt
2019-05-02  7:56         ` Chee, Tien Fong
2019-05-03 11:54           ` Simon Goldschmidt
2019-05-06  3:34             ` Chee, Tien Fong
2019-04-15  3:52 ` [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream Chee, Tien Fong

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