From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: ** X-Spam-Status: No, score=2.3 required=3.0 tests=CHARSET_FARAWAY_HEADER, FROM_EXCESS_BASE64,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B2FFC282DD for ; Fri, 24 May 2019 01:14:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F0FD02168B for ; Fri, 24 May 2019 01:13:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731632AbfEXBN7 (ORCPT ); Thu, 23 May 2019 21:13:59 -0400 Received: from www3345.sakura.ne.jp ([49.212.235.55]:25752 "EHLO www3345.sakura.ne.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731608AbfEXBN7 (ORCPT ); Thu, 23 May 2019 21:13:59 -0400 Received: from fsav405.sakura.ne.jp (fsav405.sakura.ne.jp [133.242.250.104]) by www3345.sakura.ne.jp (8.15.2/8.15.2) with ESMTP id x4O1DuIj002595; Fri, 24 May 2019 10:13:56 +0900 (JST) (envelope-from na-hoan@jinso.co.jp) Received: from www3345.sakura.ne.jp (49.212.235.55) by fsav405.sakura.ne.jp (F-Secure/fsigk_smtp/530/fsav405.sakura.ne.jp); Fri, 24 May 2019 10:13:55 +0900 (JST) X-Virus-Status: clean(F-Secure/fsigk_smtp/530/fsav405.sakura.ne.jp) Received: from nat.cybozu.com (nat.cybozu.com [103.79.14.78]) (authenticated bits=0) by www3345.sakura.ne.jp (8.15.2/8.15.2) with ESMTPA id x4O1DtGR002590; Fri, 24 May 2019 10:13:55 +0900 (JST) (envelope-from na-hoan@jinso.co.jp) Date: Fri, 24 May 2019 10:13:55 +0900 From: =?ISO-2022-JP?B?IhskQiUwJSclcyEmJSIlcyEmJVslISVzGyhCIg==?= To: Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, geert+renesas@glider.be, linux-watchdog@vger.kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, wsa+renesas@sang-engineering.com, kuninori.morimoto.gx@renesas.com, yoshihiro.shimoda.uh@renesas.com, h-inayoshi@jinso.co.jp, cv-dong@jinso.co.jp Message-ID: <155866043594663500007f86@nat.cybozu.com> References: <20190523110451.GA3979@kunai> In-Reply-To: <20190523110451.GA3979@kunai> Subject: Re: [PATCH] watchdog: renesas_wdt: Fix interrupt enable for timer X-Mailer: Cybozu Office 10.8 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-2022-JP Content-Transfer-Encoding: 7bit Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Dear Wolfram-san Dear Geert- san Thank you very much Wolfram Sang wrote: > Hi, > > On Thu, May 23, 2019 at 06:29:37PM +0900, Nguyen An Hoan wrote: > > From: Hoan Nguyen An > > > > Fix setting for bit WOVFE of RWTCSRA. Keep it enable follow hardware document. > > Hmm, I can't find it in the docs. Which version of the documentation do > you use? > > > > - rwdt_write(priv, priv->cks, RWTCSRA); > > + val |= priv->cks; > > + rwdt_write(priv, val, RWTCSRA); > > Have you tested this successfully? According to the docs, CKS bits are > all 1 by default. So, your |= operation should be a NOP and we can't > select a CKS value anymore if I am not mistaken. > I tested and can confirm WOVFE was be disable by command rwdt_write(priv, priv->cks, RWTCSRA); I don't understand why this bit is turned off but the watchdog can still reset, but according to the document it will be 1. > > rwdt_write(priv, 0, RWTCSRB); > > > > while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG) > > cpu_relax(); > > - > > - rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA); > > + /* Enable interrupt and timer */ > > + rwdt_write(priv, val | RWTCSRA_WOVFE | RWTCSRA_TME, RWTCSRA); > > What is the use of enabling an interrupt without having an interrupt > handler? (And I never understood why there is an interrupt for an > overflowing watchdog. We won't have time to serve it, or am I > overlooking something obvious?) I have added the interrupt node to dtsi and created the interrupt handler to successfully handle the Secure watchdog Gen2, but this is not documented. With Gen 3, I am also thinking whether it is necessary or not. Thank you!!! With Gen3, after reset by WDT, then restart will have an interrupt when probe timer(), but we can do this no reset, after this, timer operate normally. Problaly this patch should RFC Thank you for your helps!!! > > Kind regards, > > Wolfram >