From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C57F9C28CC0 for ; Wed, 29 May 2019 20:56:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 902B9241C8 for ; Wed, 29 May 2019 20:56:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="ZFOOvJJH"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="mAEg4epF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726311AbfE2U4S (ORCPT ); Wed, 29 May 2019 16:56:18 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60616 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726038AbfE2U4S (ORCPT ); Wed, 29 May 2019 16:56:18 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DC915618F6; Wed, 29 May 2019 20:55:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1559163376; bh=8eb3TT7qBqZKcSLWpPylJf4TCDyFQpG0l2uLmE4Jm3w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZFOOvJJHvgpRUhO6cTXunqkO4r/0udV88jqpoSD3I/ylElt6Q8XiBTGTHEAuC6OYb rKbBOWjQ+Oj187Il6kCyWS4gszNShKYoOqqf/WUHEWBv8w+x+0OYzdSxLvoGtnDZV4 NkZuVeonVP+ZHMbRJmqpq9lQOTEtz4dPoFj2mSyc= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0D94761A20; Wed, 29 May 2019 20:55:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1559163354; bh=8eb3TT7qBqZKcSLWpPylJf4TCDyFQpG0l2uLmE4Jm3w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mAEg4epFJbBDBMF194fxxqjbBJO0LX4xNb2jftwJYexCO50YVqtFW9U8a8s7D5CrM vzoMy4rYlVnnSKPxekgOfdHQiGQWjIpRy88CIkwaaH5VR4XrNuPSDn4SMR3s4jqR/3 bRjWLbFdR18Z/JTFd/9C3r3QqqOv0VAaLIgeWE80= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0D94761A20 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: jean-philippe.brucker@arm.com, linux-arm-msm@vger.kernel.org, hoegsberg@google.com, dianders@chromium.org, Sean Paul , Sharat Masetty , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , David Airlie , Daniel Vetter Subject: [PATCH v3 15/16] drm/msm/a6xx: Support per-instance pagetables Date: Wed, 29 May 2019 14:54:51 -0600 Message-Id: <1559163292-4792-16-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559163292-4792-1-git-send-email-jcrouse@codeaurora.org> References: <1559163292-4792-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for per-instance pagetables for a6xx targets. Add support to handle split pagetables and create a new instance if the needed IOMMU support exists and insert the necessary PM4 commands to trigger a pagetable switch at the beginning of a user command. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 123 ++++++++++++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 2 files changed, 120 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 3d70588..1be8bfc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -12,6 +12,62 @@ #define GPU_PAS_ID 13 +static void a6xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + struct msm_file_private *ctx) +{ + u64 ttbr; + u32 asid; + + if (!msm_iommu_get_ptinfo(ctx->aspace->mmu, &ttbr, &asid)) + return; + + ttbr = ttbr | ((u64) asid) << 48; + + /* Turn off protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Turn on APIV mode to access critical regions */ + OUT_PKT4(ring, REG_A6XX_CP_MISC_CNTL, 1); + OUT_RING(ring, 1); + + /* Make sure the ME is synchronized before staring the update */ + OUT_PKT7(ring, CP_WAIT_FOR_ME, 0); + + /* Execute the table update */ + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); + OUT_RING(ring, lower_32_bits(ttbr)); + OUT_RING(ring, upper_32_bits(ttbr)); + /* CONTEXTIDR is currently unused */ + OUT_RING(ring, 0); + /* CONTEXTBANK is currently unused */ + OUT_RING(ring, 0); + + /* + * Write the new TTBR0 to the preemption records - this will be used to + * reload the pagetable if the current ring gets preempted out. + */ + OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_RING(ring, lower_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, lower_32_bits(ttbr)); + OUT_RING(ring, upper_32_bits(ttbr)); + + /* Invalidate the draw state so we start off fresh */ + OUT_PKT7(ring, CP_SET_DRAW_STATE, 3); + OUT_RING(ring, 0x40000); + OUT_RING(ring, 1); + OUT_RING(ring, 0); + + /* Turn off APRIV */ + OUT_PKT4(ring, REG_A6XX_CP_MISC_CNTL, 1); + OUT_RING(ring, 0); + + /* Turn off protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); +} + static inline bool _a6xx_check_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -89,6 +145,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, struct msm_ringbuffer *ring = submit->ring; unsigned int i; + a6xx_set_pagetable(gpu, ring, ctx); + get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, rbmemptr_stats(ring, index, cpcycles_start)); @@ -810,21 +868,77 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) return (unsigned long)busy_time; } +static struct msm_gem_address_space *a6xx_new_address_space(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct msm_gem_address_space *aspace; + int ret; + + /* Return the default pagetable if per instance tables don't work */ + if (!a6xx_gpu->per_instance_tables) + return gpu->aspace; + + aspace = msm_gem_address_space_create_instance(&gpu->pdev->dev, "gpu", + 0x100000000ULL, 0x1ffffffffULL); + if (IS_ERR(aspace)) + return aspace; + + ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); + if (ret) { + /* -ENODEV means that aux domains aren't supported */ + if (ret == -ENODEV) + return gpu->aspace; + + return ERR_PTR(ret); + } + + return aspace; +} + static struct msm_gem_address_space * a6xx_create_address_space(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct device *dev = &gpu->pdev->dev; struct msm_gem_address_space *aspace; struct iommu_domain *iommu; - int ret; + int ret, val = 1; + + a6xx_gpu->per_instance_tables = false; iommu = iommu_domain_alloc(&platform_bus_type); if (!iommu) return ERR_PTR(-ENXIO); - iommu->geometry.aperture_start = 0x100000000ULL; - iommu->geometry.aperture_end = 0x1ffffffffULL; + /* Try to enable split pagetables */ + if (iommu_domain_set_attr(iommu, DOMAIN_ATTR_SPLIT_TABLES, &val)) { + /* + * If split pagetables aren't available we won't be able to do + * per-instance pagetables so set up the global va space at our + * susual location + */ + iommu->geometry.aperture_start = 0x100000000ULL; + iommu->geometry.aperture_end = 0x1ffffffffULL; + } else { + /* + * If split pagetables are available then we might be able to do + * per-instance pagetables. Put the default va-space in TTBR1 to + * prepare + */ + iommu->geometry.aperture_start = 0xfffffff100000000ULL; + iommu->geometry.aperture_end = 0xffffff1ffffffffULL; + + /* + * If both split pagetables and aux domains are supported we can + * do per_instance pagetables + */ + a6xx_gpu->per_instance_tables = + iommu_dev_has_feature(dev, IOMMU_DEV_FEAT_AUX); + } - aspace = msm_gem_address_space_create(&gpu->pdev->dev, iommu, "gpu"); + aspace = msm_gem_address_space_create(dev, iommu, "gpu"); if (IS_ERR(aspace)) { iommu_domain_free(iommu); DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n", @@ -865,6 +979,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_put = a6xx_gpu_state_put, #endif .create_address_space = a6xx_create_address_space, + .new_address_space = a6xx_new_address_space, }, .get_timestamp = a6xx_get_timestamp, }; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 6439955..b133aaa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -21,6 +21,7 @@ struct a6xx_gpu { struct msm_ringbuffer *cur_ring; struct a6xx_gmu gmu; + bool per_instance_tables; }; #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH v3 15/16] drm/msm/a6xx: Support per-instance pagetables Date: Wed, 29 May 2019 14:54:51 -0600 Message-ID: <1559163292-4792-16-git-send-email-jcrouse@codeaurora.org> References: <1559163292-4792-1-git-send-email-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1559163292-4792-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sharat Masetty , dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, David Airlie , Rob Clark , hoegsberg-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, Daniel Vetter , Sean Paul List-Id: dri-devel@lists.freedesktop.org QWRkIHN1cHBvcnQgZm9yIHBlci1pbnN0YW5jZSBwYWdldGFibGVzIGZvciBhNnh4IHRhcmdldHMu IEFkZCBzdXBwb3J0CnRvIGhhbmRsZSBzcGxpdCBwYWdldGFibGVzIGFuZCBjcmVhdGUgYSBuZXcg aW5zdGFuY2UgaWYgdGhlIG5lZWRlZApJT01NVSBzdXBwb3J0IGV4aXN0cyBhbmQgaW5zZXJ0IHRo ZSBuZWNlc3NhcnkgUE00IGNvbW1hbmRzIHRvIHRyaWdnZXIKYSBwYWdldGFibGUgc3dpdGNoIGF0 IHRoZSBiZWdpbm5pbmcgb2YgYSB1c2VyIGNvbW1hbmQuCgpTaWduZWQtb2ZmLWJ5OiBKb3JkYW4g Q3JvdXNlIDxqY3JvdXNlQGNvZGVhdXJvcmEub3JnPgotLS0KCiBkcml2ZXJzL2dwdS9kcm0vbXNt L2FkcmVuby9hNnh4X2dwdS5jIHwgMTIzICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr LS0KIGRyaXZlcnMvZ3B1L2RybS9tc20vYWRyZW5vL2E2eHhfZ3B1LmggfCAgIDEgKwogMiBmaWxl cyBjaGFuZ2VkLCAxMjAgaW5zZXJ0aW9ucygrKSwgNCBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQg YS9kcml2ZXJzL2dwdS9kcm0vbXNtL2FkcmVuby9hNnh4X2dwdS5jIGIvZHJpdmVycy9ncHUvZHJt L21zbS9hZHJlbm8vYTZ4eF9ncHUuYwppbmRleCAzZDcwNTg4Li4xYmU4YmZjIDEwMDY0NAotLS0g YS9kcml2ZXJzL2dwdS9kcm0vbXNtL2FkcmVuby9hNnh4X2dwdS5jCisrKyBiL2RyaXZlcnMvZ3B1 L2RybS9tc20vYWRyZW5vL2E2eHhfZ3B1LmMKQEAgLTEyLDYgKzEyLDYyIEBACiAKICNkZWZpbmUg R1BVX1BBU19JRCAxMwogCitzdGF0aWMgdm9pZCBhNnh4X3NldF9wYWdldGFibGUoc3RydWN0IG1z bV9ncHUgKmdwdSwgc3RydWN0IG1zbV9yaW5nYnVmZmVyICpyaW5nLAorCXN0cnVjdCBtc21fZmls ZV9wcml2YXRlICpjdHgpCit7CisJdTY0IHR0YnI7CisJdTMyIGFzaWQ7CisKKwlpZiAoIW1zbV9p b21tdV9nZXRfcHRpbmZvKGN0eC0+YXNwYWNlLT5tbXUsICZ0dGJyLCAmYXNpZCkpCisJCXJldHVy bjsKKworCXR0YnIgPSB0dGJyIHwgKCh1NjQpIGFzaWQpIDw8IDQ4OworCisJLyogVHVybiBvZmYg cHJvdGVjdGVkIG1vZGUgKi8KKwlPVVRfUEtUNyhyaW5nLCBDUF9TRVRfUFJPVEVDVEVEX01PREUs IDEpOworCU9VVF9SSU5HKHJpbmcsIDApOworCisJLyogVHVybiBvbiBBUElWIG1vZGUgdG8gYWNj ZXNzIGNyaXRpY2FsIHJlZ2lvbnMgKi8KKwlPVVRfUEtUNChyaW5nLCBSRUdfQTZYWF9DUF9NSVND X0NOVEwsIDEpOworCU9VVF9SSU5HKHJpbmcsIDEpOworCisJLyogTWFrZSBzdXJlIHRoZSBNRSBp cyBzeW5jaHJvbml6ZWQgYmVmb3JlIHN0YXJpbmcgdGhlIHVwZGF0ZSAqLworCU9VVF9QS1Q3KHJp bmcsIENQX1dBSVRfRk9SX01FLCAwKTsKKworCS8qIEV4ZWN1dGUgdGhlIHRhYmxlIHVwZGF0ZSAq LworCU9VVF9QS1Q3KHJpbmcsIENQX1NNTVVfVEFCTEVfVVBEQVRFLCA0KTsKKwlPVVRfUklORyhy aW5nLCBsb3dlcl8zMl9iaXRzKHR0YnIpKTsKKwlPVVRfUklORyhyaW5nLCB1cHBlcl8zMl9iaXRz KHR0YnIpKTsKKwkvKiBDT05URVhUSURSIGlzIGN1cnJlbnRseSB1bnVzZWQgKi8KKwlPVVRfUklO RyhyaW5nLCAwKTsKKwkvKiBDT05URVhUQkFOSyBpcyBjdXJyZW50bHkgdW51c2VkICovCisJT1VU X1JJTkcocmluZywgMCk7CisKKwkvKgorCSAqIFdyaXRlIHRoZSBuZXcgVFRCUjAgdG8gdGhlIHBy ZWVtcHRpb24gcmVjb3JkcyAtIHRoaXMgd2lsbCBiZSB1c2VkIHRvCisJICogcmVsb2FkIHRoZSBw YWdldGFibGUgaWYgdGhlIGN1cnJlbnQgcmluZyBnZXRzIHByZWVtcHRlZCBvdXQuCisJICovCisJ T1VUX1BLVDcocmluZywgQ1BfTUVNX1dSSVRFLCA0KTsKKwlPVVRfUklORyhyaW5nLCBsb3dlcl8z Ml9iaXRzKHJibWVtcHRyKHJpbmcsIHR0YnIwKSkpOworCU9VVF9SSU5HKHJpbmcsIHVwcGVyXzMy X2JpdHMocmJtZW1wdHIocmluZywgdHRicjApKSk7CisJT1VUX1JJTkcocmluZywgbG93ZXJfMzJf Yml0cyh0dGJyKSk7CisJT1VUX1JJTkcocmluZywgdXBwZXJfMzJfYml0cyh0dGJyKSk7CisKKwkv KiBJbnZhbGlkYXRlIHRoZSBkcmF3IHN0YXRlIHNvIHdlIHN0YXJ0IG9mZiBmcmVzaCAqLworCU9V VF9QS1Q3KHJpbmcsIENQX1NFVF9EUkFXX1NUQVRFLCAzKTsKKwlPVVRfUklORyhyaW5nLCAweDQw MDAwKTsKKwlPVVRfUklORyhyaW5nLCAxKTsKKwlPVVRfUklORyhyaW5nLCAwKTsKKworCS8qIFR1 cm4gb2ZmIEFQUklWICovCisJT1VUX1BLVDQocmluZywgUkVHX0E2WFhfQ1BfTUlTQ19DTlRMLCAx KTsKKwlPVVRfUklORyhyaW5nLCAwKTsKKworCS8qIFR1cm4gb2ZmIHByb3RlY3RlZCBtb2RlICov CisJT1VUX1BLVDcocmluZywgQ1BfU0VUX1BST1RFQ1RFRF9NT0RFLCAxKTsKKwlPVVRfUklORyhy aW5nLCAxKTsKK30KKwogc3RhdGljIGlubGluZSBib29sIF9hNnh4X2NoZWNrX2lkbGUoc3RydWN0 IG1zbV9ncHUgKmdwdSkKIHsKIAlzdHJ1Y3QgYWRyZW5vX2dwdSAqYWRyZW5vX2dwdSA9IHRvX2Fk cmVub19ncHUoZ3B1KTsKQEAgLTg5LDYgKzE0NSw4IEBAIHN0YXRpYyB2b2lkIGE2eHhfc3VibWl0 KHN0cnVjdCBtc21fZ3B1ICpncHUsIHN0cnVjdCBtc21fZ2VtX3N1Ym1pdCAqc3VibWl0LAogCXN0 cnVjdCBtc21fcmluZ2J1ZmZlciAqcmluZyA9IHN1Ym1pdC0+cmluZzsKIAl1bnNpZ25lZCBpbnQg aTsKIAorCWE2eHhfc2V0X3BhZ2V0YWJsZShncHUsIHJpbmcsIGN0eCk7CisKIAlnZXRfc3RhdHNf Y291bnRlcihyaW5nLCBSRUdfQTZYWF9SQkJNX1BFUkZDVFJfQ1BfMF9MTywKIAkJcmJtZW1wdHJf c3RhdHMocmluZywgaW5kZXgsIGNwY3ljbGVzX3N0YXJ0KSk7CiAKQEAgLTgxMCwyMSArODY4LDc3 IEBAIHN0YXRpYyB1bnNpZ25lZCBsb25nIGE2eHhfZ3B1X2J1c3koc3RydWN0IG1zbV9ncHUgKmdw dSkKIAlyZXR1cm4gKHVuc2lnbmVkIGxvbmcpYnVzeV90aW1lOwogfQogCitzdGF0aWMgc3RydWN0 IG1zbV9nZW1fYWRkcmVzc19zcGFjZSAqYTZ4eF9uZXdfYWRkcmVzc19zcGFjZShzdHJ1Y3QgbXNt X2dwdSAqZ3B1KQoreworCXN0cnVjdCBhZHJlbm9fZ3B1ICphZHJlbm9fZ3B1ID0gdG9fYWRyZW5v X2dwdShncHUpOworCXN0cnVjdCBhNnh4X2dwdSAqYTZ4eF9ncHUgPSB0b19hNnh4X2dwdShhZHJl bm9fZ3B1KTsKKwlzdHJ1Y3QgbXNtX2dlbV9hZGRyZXNzX3NwYWNlICphc3BhY2U7CisJaW50IHJl dDsKKworCS8qIFJldHVybiB0aGUgZGVmYXVsdCBwYWdldGFibGUgaWYgcGVyIGluc3RhbmNlIHRh YmxlcyBkb24ndCB3b3JrICovCisJaWYgKCFhNnh4X2dwdS0+cGVyX2luc3RhbmNlX3RhYmxlcykK KwkJcmV0dXJuIGdwdS0+YXNwYWNlOworCisJYXNwYWNlID0gbXNtX2dlbV9hZGRyZXNzX3NwYWNl X2NyZWF0ZV9pbnN0YW5jZSgmZ3B1LT5wZGV2LT5kZXYsICJncHUiLAorCQkweDEwMDAwMDAwMFVM TCwgMHgxZmZmZmZmZmZVTEwpOworCWlmIChJU19FUlIoYXNwYWNlKSkKKwkJcmV0dXJuIGFzcGFj ZTsKKworCXJldCA9IGFzcGFjZS0+bW11LT5mdW5jcy0+YXR0YWNoKGFzcGFjZS0+bW11LCBOVUxM LCAwKTsKKwlpZiAocmV0KSB7CisJCS8qIC1FTk9ERVYgbWVhbnMgdGhhdCBhdXggZG9tYWlucyBh cmVuJ3Qgc3VwcG9ydGVkICovCisJCWlmIChyZXQgPT0gLUVOT0RFVikKKwkJCXJldHVybiBncHUt PmFzcGFjZTsKKworCQlyZXR1cm4gRVJSX1BUUihyZXQpOworCX0KKworCXJldHVybiBhc3BhY2U7 Cit9CisKIHN0YXRpYyBzdHJ1Y3QgbXNtX2dlbV9hZGRyZXNzX3NwYWNlICoKIGE2eHhfY3JlYXRl X2FkZHJlc3Nfc3BhY2Uoc3RydWN0IG1zbV9ncHUgKmdwdSkKIHsKKwlzdHJ1Y3QgYWRyZW5vX2dw dSAqYWRyZW5vX2dwdSA9IHRvX2FkcmVub19ncHUoZ3B1KTsKKwlzdHJ1Y3QgYTZ4eF9ncHUgKmE2 eHhfZ3B1ID0gdG9fYTZ4eF9ncHUoYWRyZW5vX2dwdSk7CisJc3RydWN0IGRldmljZSAqZGV2ID0g JmdwdS0+cGRldi0+ZGV2OwogCXN0cnVjdCBtc21fZ2VtX2FkZHJlc3Nfc3BhY2UgKmFzcGFjZTsK IAlzdHJ1Y3QgaW9tbXVfZG9tYWluICppb21tdTsKLQlpbnQgcmV0OworCWludCByZXQsIHZhbCA9 IDE7CisKKwlhNnh4X2dwdS0+cGVyX2luc3RhbmNlX3RhYmxlcyA9IGZhbHNlOwogCiAJaW9tbXUg PSBpb21tdV9kb21haW5fYWxsb2MoJnBsYXRmb3JtX2J1c190eXBlKTsKIAlpZiAoIWlvbW11KQog CQlyZXR1cm4gRVJSX1BUUigtRU5YSU8pOwogCi0JaW9tbXUtPmdlb21ldHJ5LmFwZXJ0dXJlX3N0 YXJ0ID0gMHgxMDAwMDAwMDBVTEw7Ci0JaW9tbXUtPmdlb21ldHJ5LmFwZXJ0dXJlX2VuZCA9IDB4 MWZmZmZmZmZmVUxMOworCS8qIFRyeSB0byBlbmFibGUgc3BsaXQgcGFnZXRhYmxlcyAqLworCWlm IChpb21tdV9kb21haW5fc2V0X2F0dHIoaW9tbXUsIERPTUFJTl9BVFRSX1NQTElUX1RBQkxFUywg JnZhbCkpIHsKKwkJLyoKKwkJICogSWYgc3BsaXQgcGFnZXRhYmxlcyBhcmVuJ3QgYXZhaWxhYmxl IHdlIHdvbid0IGJlIGFibGUgdG8gZG8KKwkJICogcGVyLWluc3RhbmNlIHBhZ2V0YWJsZXMgc28g c2V0IHVwIHRoZSBnbG9iYWwgdmEgc3BhY2UgYXQgb3VyCisJCSAqIHN1c3VhbCBsb2NhdGlvbgor CQkgKi8KKwkJaW9tbXUtPmdlb21ldHJ5LmFwZXJ0dXJlX3N0YXJ0ID0gMHgxMDAwMDAwMDBVTEw7 CisJCWlvbW11LT5nZW9tZXRyeS5hcGVydHVyZV9lbmQgPSAweDFmZmZmZmZmZlVMTDsKKwl9IGVs c2UgeworCQkvKgorCQkgKiBJZiBzcGxpdCBwYWdldGFibGVzIGFyZSBhdmFpbGFibGUgdGhlbiB3 ZSBtaWdodCBiZSBhYmxlIHRvIGRvCisJCSAqIHBlci1pbnN0YW5jZSBwYWdldGFibGVzLiBQdXQg dGhlIGRlZmF1bHQgdmEtc3BhY2UgaW4gVFRCUjEgdG8KKwkJICogcHJlcGFyZQorCQkgKi8KKwkJ aW9tbXUtPmdlb21ldHJ5LmFwZXJ0dXJlX3N0YXJ0ID0gMHhmZmZmZmZmMTAwMDAwMDAwVUxMOwor CQlpb21tdS0+Z2VvbWV0cnkuYXBlcnR1cmVfZW5kID0gMHhmZmZmZmYxZmZmZmZmZmZVTEw7CisK KwkJLyoKKwkJICogSWYgYm90aCBzcGxpdCBwYWdldGFibGVzIGFuZCBhdXggZG9tYWlucyBhcmUg c3VwcG9ydGVkIHdlIGNhbgorCQkgKiBkbyBwZXJfaW5zdGFuY2UgcGFnZXRhYmxlcworCQkgKi8K KwkJYTZ4eF9ncHUtPnBlcl9pbnN0YW5jZV90YWJsZXMgPQorCQkJaW9tbXVfZGV2X2hhc19mZWF0 dXJlKGRldiwgSU9NTVVfREVWX0ZFQVRfQVVYKTsKKwl9CiAKLQlhc3BhY2UgPSBtc21fZ2VtX2Fk ZHJlc3Nfc3BhY2VfY3JlYXRlKCZncHUtPnBkZXYtPmRldiwgaW9tbXUsICJncHUiKTsKKwlhc3Bh Y2UgPSBtc21fZ2VtX2FkZHJlc3Nfc3BhY2VfY3JlYXRlKGRldiwgaW9tbXUsICJncHUiKTsKIAlp ZiAoSVNfRVJSKGFzcGFjZSkpIHsKIAkJaW9tbXVfZG9tYWluX2ZyZWUoaW9tbXUpOwogCQlEUk1f REVWX0VSUk9SKGdwdS0+ZGV2LT5kZXYsICJmYWlsZWQgdG8gaW5pdCBtbXU6ICVsZFxuIiwKQEAg LTg2NSw2ICs5NzksNyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGFkcmVub19ncHVfZnVuY3MgZnVu Y3MgPSB7CiAJCS5ncHVfc3RhdGVfcHV0ID0gYTZ4eF9ncHVfc3RhdGVfcHV0LAogI2VuZGlmCiAJ CS5jcmVhdGVfYWRkcmVzc19zcGFjZSA9IGE2eHhfY3JlYXRlX2FkZHJlc3Nfc3BhY2UsCisJCS5u ZXdfYWRkcmVzc19zcGFjZSA9IGE2eHhfbmV3X2FkZHJlc3Nfc3BhY2UsCiAJfSwKIAkuZ2V0X3Rp bWVzdGFtcCA9IGE2eHhfZ2V0X3RpbWVzdGFtcCwKIH07CmRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vbXNtL2FkcmVuby9hNnh4X2dwdS5oIGIvZHJpdmVycy9ncHUvZHJtL21zbS9hZHJlbm8v YTZ4eF9ncHUuaAppbmRleCA2NDM5OTU1Li5iMTMzYWFhIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dw dS9kcm0vbXNtL2FkcmVuby9hNnh4X2dwdS5oCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vYWRy ZW5vL2E2eHhfZ3B1LmgKQEAgLTIxLDYgKzIxLDcgQEAgc3RydWN0IGE2eHhfZ3B1IHsKIAlzdHJ1 Y3QgbXNtX3JpbmdidWZmZXIgKmN1cl9yaW5nOwogCiAJc3RydWN0IGE2eHhfZ211IGdtdTsKKwli b29sIHBlcl9pbnN0YW5jZV90YWJsZXM7CiB9OwogCiAjZGVmaW5lIHRvX2E2eHhfZ3B1KHgpIGNv bnRhaW5lcl9vZih4LCBzdHJ1Y3QgYTZ4eF9ncHUsIGJhc2UpCi0tIAoyLjcuNAoKX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KRnJlZWRyZW5vIG1haWxpbmcg bGlzdApGcmVlZHJlbm9AbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRl c2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZnJlZWRyZW5v