From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20320C28CC0 for ; Wed, 29 May 2019 20:56:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EC3E4241C6 for ; Wed, 29 May 2019 20:56:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="TcpYeA+J"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="NygVLsg7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726876AbfE2Uzc (ORCPT ); Wed, 29 May 2019 16:55:32 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57470 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726871AbfE2Uzb (ORCPT ); Wed, 29 May 2019 16:55:31 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9554D61633; Wed, 29 May 2019 20:55:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1559163330; bh=B4EA6+W0bMBZWz+Img5LRozrErEZ8aBa+Kh0uCtpCTE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TcpYeA+J8rOgMttD2H3KglY6R7jLOe3K1UCH9fggHbm37SeKXGvlpRG3PHj1Amtse tg1kso1o1UcmG9bSW6+S996oydlPzSl+6tvffjQhBMLvh2iZCB/OcCZlkezQ6bn/Ta FSuHizi/9rAxav4AYWMWrNof19dPdqkHdvO7XXD8= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C08B1613A7; Wed, 29 May 2019 20:55:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1559163326; bh=B4EA6+W0bMBZWz+Img5LRozrErEZ8aBa+Kh0uCtpCTE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NygVLsg7o0398FQypBvm8OZaapigH9X5AOxMFZdT6auiW/ETsNUtUV7r6kU3X2gl1 TADVCcURJb6BUnGC1JAtZSaK8/2loVlhRuteIWQWUHegvJJCq8jrhQzgdoOJY4FRQQ NTh2B7FxYdeI5aTT/fi1HfujDCisLEKiFF1h3aSU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C08B1613A7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: jean-philippe.brucker@arm.com, linux-arm-msm@vger.kernel.org, hoegsberg@google.com, dianders@chromium.org, Sean Paul , Kees Cook , Wen Yang , Sharat Masetty , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , David Airlie , Mamta Shukla , Daniel Vetter Subject: [PATCH v3 07/16] drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets Date: Wed, 29 May 2019 14:54:43 -0600 Message-Id: <1559163292-4792-8-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559163292-4792-1-git-send-email-jcrouse@codeaurora.org> References: <1559163292-4792-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A5XX and newer GPUs can be run in either 32 or 64 bit mode. The GPU registers and the microcode use 64 bit virtual addressing in either case but the upper 32 bits are ignored if the GPU is in 32 bit mode. There is no performance disadvantage to remaining in 64 bit mode even if we are only generating 32 bit addresses so switch over now to prepare for using addresses above 4G for targets that support them. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index e5fcefa..43a2b4a 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -642,6 +642,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu) REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); + /* Put the GPU into 64 bit by default */ + gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); + ret = adreno_hw_init(gpu); if (ret) return ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1f9f4b0..be39cf0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -391,6 +391,20 @@ static int a6xx_hw_init(struct msm_gpu *gpu) REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); + /* Turn on 64 bit addressing for all blocks */ + gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); + /* enable hardware clockgating */ a6xx_set_hwcg(gpu, true); -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH v3 07/16] drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets Date: Wed, 29 May 2019 14:54:43 -0600 Message-ID: <1559163292-4792-8-git-send-email-jcrouse@codeaurora.org> References: <1559163292-4792-1-git-send-email-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1559163292-4792-1-git-send-email-jcrouse@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: freedreno@lists.freedesktop.org Cc: Kees Cook , jean-philippe.brucker@arm.com, linux-arm-msm@vger.kernel.org, Sharat Masetty , dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, David Airlie , hoegsberg@google.com, Mamta Shukla , Sean Paul , Wen Yang List-Id: dri-devel@lists.freedesktop.org QTVYWCBhbmQgbmV3ZXIgR1BVcyBjYW4gYmUgcnVuIGluIGVpdGhlciAzMiBvciA2NCBiaXQgbW9k ZS4gVGhlIEdQVQpyZWdpc3RlcnMgYW5kIHRoZSBtaWNyb2NvZGUgdXNlIDY0IGJpdCB2aXJ0dWFs IGFkZHJlc3NpbmcgaW4gZWl0aGVyCmNhc2UgYnV0IHRoZSB1cHBlciAzMiBiaXRzIGFyZSBpZ25v cmVkIGlmIHRoZSBHUFUgaXMgaW4gMzIgYml0IG1vZGUuClRoZXJlIGlzIG5vIHBlcmZvcm1hbmNl IGRpc2FkdmFudGFnZSB0byByZW1haW5pbmcgaW4gNjQgYml0IG1vZGUgZXZlbgppZiB3ZSBhcmUg b25seSBnZW5lcmF0aW5nIDMyIGJpdCBhZGRyZXNzZXMgc28gc3dpdGNoIG92ZXIgbm93IHRvIHBy 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