From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v3, 09/27] drm/mediatek: add mutex sof register offset into ddp private data Date: Thu, 13 Jun 2019 15:45:02 +0800 Message-ID: <1560411902.27582.0.camel@mtksdaap41> References: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com> <1559734986-7379-10-git-send-email-yongqiang.niu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1559734986-7379-10-git-send-email-yongqiang.niu@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: yongqiang.niu@mediatek.com Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: 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CQlpZiAoZGRwLT5kYXRhLT5tdXRleF9tb2RbaWRdIDwgMzIpIHsKCgpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRy aS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWw= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85134C31E45 for ; Thu, 13 Jun 2019 07:45:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher 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Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eCc3/hH4/cjsMOng/T+JxBBle3fvCeED+3nB9Oug+ZI=; b=ITtVQCuWK7S3A8 iWYSfWCcwtlC0mWNcjLqYTAfFxlvBb2gtMtV0UJR0M4Msxg/kun87pvueO4OsVO/2O/3hRddj+agS UAzWCwrTUJIduQyZnARgl2+OXKhz81QrJTcfc1YtZ7FvYVnJFRt9ftfqoE/NrkyeGodOdOcy6q6wt 3eIAdngeqCDCqWPgtAkbPbzMxlyZ5+0srlw1UzOCmj4NUoJi9gRiVOINmccOe+ouTx8aoZAycXBzX +/E1Bbdkt8FrilkuVAHBx4G+Pkw7qSuJzF1W3hHsow20cu6TILQg1bBNy50xRqcwm6udaNUgH2uQt FmVWhTAutOSsuWc2lP8A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hbKQ8-0000yQ-JI; Thu, 13 Jun 2019 07:45:16 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hbKQ5-0000y1-20; Thu, 13 Jun 2019 07:45:14 +0000 X-UUID: a1793233c06d4df6a0fe3899141ff412-20190612 X-UUID: a1793233c06d4df6a0fe3899141ff412-20190612 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 597823498; Wed, 12 Jun 2019 23:45:06 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Jun 2019 00:45:05 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Jun 2019 15:45:03 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 13 Jun 2019 15:45:03 +0800 Message-ID: <1560411902.27582.0.camel@mtksdaap41> Subject: Re: [PATCH v3, 09/27] drm/mediatek: add mutex sof register offset into ddp private data From: CK Hu To: Date: Thu, 13 Jun 2019 15:45:02 +0800 In-Reply-To: <1559734986-7379-10-git-send-email-yongqiang.niu@mediatek.com> References: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com> <1559734986-7379-10-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190613_004513_107573_5155E8DE X-CRM114-Status: GOOD ( 12.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Yongqiang: On Wed, 2019-06-05 at 19:42 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > mutex sof register offset will be private data of ddp > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index e1a510f..717609d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -42,12 +42,13 @@ > #define DISP_REG_CONFIG_DPI_SEL 0x064 > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > +#define MT2701_DISP_MUTEX0_SOF0 0x2c 0x30? Regards, CK > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) > -#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > @@ -164,6 +165,7 @@ struct mtk_ddp_data { > const unsigned int *mutex_mod; > const unsigned int *mutex_sof; > const unsigned int mutex_mod_reg; > + const unsigned int mutex_sof_reg; > }; > > struct mtk_ddp { > @@ -235,18 +237,21 @@ struct mtk_ddp { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt2712_ddp_driver_data = { > .mutex_mod = mt2712_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_mod = mt8173_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > @@ -528,7 +533,8 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > } > > writel_relaxed(ddp->data->mutex_sof[sof_id], > - ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > + ddp->regs + > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); > } > > void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > @@ -550,7 +556,8 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > case DDP_COMPONENT_DPI1: > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > ddp->regs + > - DISP_REG_MUTEX_SOF(mutex->id)); > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, > + mutex->id)); > break; > default: > if (ddp->data->mutex_mod[id] < 32) { _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08695C31E45 for ; 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Thu, 13 Jun 2019 15:45:03 +0800 Message-ID: <1560411902.27582.0.camel@mtksdaap41> Subject: Re: [PATCH v3, 09/27] drm/mediatek: add mutex sof register offset into ddp private data From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Thu, 13 Jun 2019 15:45:02 +0800 In-Reply-To: <1559734986-7379-10-git-send-email-yongqiang.niu@mediatek.com> References: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com> <1559734986-7379-10-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Wed, 2019-06-05 at 19:42 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > mutex sof register offset will be private data of ddp > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index e1a510f..717609d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -42,12 +42,13 @@ > #define DISP_REG_CONFIG_DPI_SEL 0x064 > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > +#define MT2701_DISP_MUTEX0_SOF0 0x2c 0x30? Regards, CK > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) > -#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > @@ -164,6 +165,7 @@ struct mtk_ddp_data { > const unsigned int *mutex_mod; > const unsigned int *mutex_sof; > const unsigned int mutex_mod_reg; > + const unsigned int mutex_sof_reg; > }; > > struct mtk_ddp { > @@ -235,18 +237,21 @@ struct mtk_ddp { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt2712_ddp_driver_data = { > .mutex_mod = mt2712_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_mod = mt8173_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > @@ -528,7 +533,8 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > } > > writel_relaxed(ddp->data->mutex_sof[sof_id], > - ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > + ddp->regs + > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); > } > > void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > @@ -550,7 +556,8 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > case DDP_COMPONENT_DPI1: > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > ddp->regs + > - DISP_REG_MUTEX_SOF(mutex->id)); > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, > + mutex->id)); > break; > default: > if (ddp->data->mutex_mod[id] < 32) {