From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v3, 17/27] drm/mediatek: add gmc_bits for ovl private data Date: Fri, 14 Jun 2019 12:59:14 +0800 Message-ID: <1560488354.16718.16.camel@mtksdaap41> References: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com> <1559734986-7379-18-git-send-email-yongqiang.niu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1559734986-7379-18-git-send-email-yongqiang.niu@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: yongqiang.niu@mediatek.com Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org 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3ADFA2133D for ; Fri, 14 Jun 2019 04:59:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="V0rL9Wa+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3ADFA2133D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5Xgotofy1K84CumnJIy8i65Vid1eodjDdF4hshVgMOM=; b=V0rL9Wa+lMgbkz LZQTzlXDTlR5GOWo4+7vlHIdzlNwq1yBn29mdEZvfyvCN6jRdrmNQ/E3peG80LgSOweUaVm6MEIlL XxFvqGlBGqsCD+Vct5V6+aRcr6pa97Se6bhCpNKR8qOYwTQj+fPEn+MJSkpovVjq1LYWxXM6z9ROG Un80WKBpvDEqpOFZsblDDCJYEM78DyCxzNZNmM5ivqiGf+RxXHRqdrvsOuiAX1Dn29e/TXi/BUYw6 A7qDur+RoYFsjEPYL2XuAIldMao71DSVW47J8OBwrRiLMqnjEr9lpXAyyTp7xsbXpTFoUbilEmQkm 7O8bbMmVej1s57igMpdw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hbeJL-0004rE-31; Fri, 14 Jun 2019 04:59:35 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hbeJH-0004q3-Ck; Fri, 14 Jun 2019 04:59:33 +0000 X-UUID: f8cf2459302c47eea6e7eb6837670d72-20190613 X-UUID: f8cf2459302c47eea6e7eb6837670d72-20190613 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 403836149; Thu, 13 Jun 2019 20:59:18 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Jun 2019 21:59:16 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Jun 2019 12:59:14 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 14 Jun 2019 12:59:13 +0800 Message-ID: <1560488354.16718.16.camel@mtksdaap41> Subject: Re: [PATCH v3, 17/27] drm/mediatek: add gmc_bits for ovl private data From: CK Hu To: Date: Fri, 14 Jun 2019 12:59:14 +0800 In-Reply-To: <1559734986-7379-18-git-send-email-yongqiang.niu@mediatek.com> References: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com> <1559734986-7379-18-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190613_215931_442243_BD1EEFCE X-CRM114-Status: GOOD ( 15.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Yongqiang: On Wed, 2019-06-05 at 19:42 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add gmc_bits for ovl private data > GMC register was set RDMA ultra and pre-ultra threshold. > 10bit GMC register define is different with other SOC, gmc_thrshd_l not > used. This patch is identical to v2, and I've give a 'Reviewed-by' for v2, so you should keep this 'Reviewed-by' tag in this patch, so I still give you a Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 28d1911..afb313c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -39,7 +39,9 @@ > #define DISP_REG_OVL_ADDR_MT8173 0x0f40 > #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) > > -#define OVL_RDMA_MEM_GMC 0x40402020 > +#define GMC_THRESHOLD_BITS 16 > +#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) > +#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) > > #define OVL_CON_BYTE_SWAP BIT(24) > #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > @@ -57,6 +59,7 @@ > > struct mtk_disp_ovl_data { > unsigned int addr; > + unsigned int gmc_bits; > bool fmt_rgb565_is_0; > }; > > @@ -140,9 +143,23 @@ static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) > static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) > { > unsigned int reg; > + unsigned int gmc_thrshd_l; > + unsigned int gmc_thrshd_h; > + unsigned int gmc_value; > + struct mtk_disp_ovl *ovl = comp_to_ovl(comp); > > writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); > - writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); > + > + gmc_thrshd_l = GMC_THRESHOLD_LOW >> > + (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); > + gmc_thrshd_h = GMC_THRESHOLD_HIGH >> > + (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); > + if (ovl->data->gmc_bits == 10) > + gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16; > + else > + gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | > + gmc_thrshd_h << 16 | gmc_thrshd_h << 24; > + writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); > > reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); > reg = reg | BIT(idx); > @@ -324,11 +341,13 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > > static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { > .addr = DISP_REG_OVL_ADDR_MT2701, > + .gmc_bits = 8, > .fmt_rgb565_is_0 = false, > }; > > static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { > .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 8, > .fmt_rgb565_is_0 = true, > }; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 344A2C31E44 for ; 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Fri, 14 Jun 2019 12:59:13 +0800 Message-ID: <1560488354.16718.16.camel@mtksdaap41> Subject: Re: [PATCH v3, 17/27] drm/mediatek: add gmc_bits for ovl private data From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Fri, 14 Jun 2019 12:59:14 +0800 In-Reply-To: <1559734986-7379-18-git-send-email-yongqiang.niu@mediatek.com> References: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com> <1559734986-7379-18-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Wed, 2019-06-05 at 19:42 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add gmc_bits for ovl private data > GMC register was set RDMA ultra and pre-ultra threshold. > 10bit GMC register define is different with other SOC, gmc_thrshd_l not > used. This patch is identical to v2, and I've give a 'Reviewed-by' for v2, so you should keep this 'Reviewed-by' tag in this patch, so I still give you a Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 28d1911..afb313c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -39,7 +39,9 @@ > #define DISP_REG_OVL_ADDR_MT8173 0x0f40 > #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) > > -#define OVL_RDMA_MEM_GMC 0x40402020 > +#define GMC_THRESHOLD_BITS 16 > +#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) > +#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) > > #define OVL_CON_BYTE_SWAP BIT(24) > #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > @@ -57,6 +59,7 @@ > > struct mtk_disp_ovl_data { > unsigned int addr; > + unsigned int gmc_bits; > bool fmt_rgb565_is_0; > }; > > @@ -140,9 +143,23 @@ static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) > static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) > { > unsigned int reg; > + unsigned int gmc_thrshd_l; > + unsigned int gmc_thrshd_h; > + unsigned int gmc_value; > + struct mtk_disp_ovl *ovl = comp_to_ovl(comp); > > writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); > - writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); > + > + gmc_thrshd_l = GMC_THRESHOLD_LOW >> > + (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); > + gmc_thrshd_h = GMC_THRESHOLD_HIGH >> > + (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); > + if (ovl->data->gmc_bits == 10) > + gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16; > + else > + gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | > + gmc_thrshd_h << 16 | gmc_thrshd_h << 24; > + writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); > > reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); > reg = reg | BIT(idx); > @@ -324,11 +341,13 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > > static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { > .addr = DISP_REG_OVL_ADDR_MT2701, > + .gmc_bits = 8, > .fmt_rgb565_is_0 = false, > }; > > static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { > .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 8, > .fmt_rgb565_is_0 = true, > }; >