diff for duplicates of <1563809888089.57547@bt.com> diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index de13223..0000000 --- a/a/2.bin +++ /dev/null @@ -1,1534 +0,0 @@ -<html> -<head> -<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> -<style type="text/css" style="display:none"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style> -</head> -<body dir="ltr" style="font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;"> -<p></p> -<div><span style="font-size: 12pt;">Preparation for splitting MO_8 out from TCGMemOp into new accelerator</span><br> -</div> -<div>independent MemOp.</div> -<div><br> -</div> -<div>As MO_8 will be a value of MemOp, existing TCGMemOp comparisons and</div> -<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div> -<div><br> -</div> -<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div> -<div>---</div> -<div> target/arm/sve_helper.c | 4 +-</div> -<div> target/arm/translate-a64.c | 14 +++----</div> -<div> target/arm/translate-sve.c | 4 +-</div> -<div> target/arm/translate.c | 38 +++++++++----------</div> -<div> target/i386/translate.c | 72 +++++++++++++++++------------------</div> -<div> target/mips/translate.c | 4 +-</div> -<div> target/ppc/translate/vmx-impl.inc.c | 28 +++++++-------</div> -<div> target/s390x/translate.c | 2 +-</div> -<div> target/s390x/translate_vx.inc.c | 4 +-</div> -<div> target/s390x/vec.h | 4 +-</div> -<div> tcg/aarch64/tcg-target.inc.c | 16 ++++----</div> -<div> tcg/arm/tcg-target.inc.c | 6 +--</div> -<div> tcg/i386/tcg-target.inc.c | 54 +++++++++++++-------------</div> -<div> tcg/mips/tcg-target.inc.c | 4 +-</div> -<div> tcg/riscv/tcg-target.inc.c | 4 +-</div> -<div> tcg/sparc/tcg-target.inc.c | 2 +-</div> -<div> tcg/tcg-op-gvec.c | 76 ++++++++++++++++++-------------------</div> -<div> tcg/tcg-op-vec.c | 10 ++---</div> -<div> tcg/tcg-op.c | 6 +--</div> -<div> tcg/tcg.h | 2 +-</div> -<div> 20 files changed, 177 insertions(+), 177 deletions(-)</div> -<div><br> -</div> -<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div> -<div>index fc0c175..4c7e11f 100644</div> -<div>--- a/target/arm/sve_helper.c</div> -<div>+++ b/target/arm/sve_helper.c</div> -<div>@@ -1531,7 +1531,7 @@ void HELPER(sve_cpy_m_b)(void *vd, void *vn, void *vg,</div> -<div> uint64_t *d = vd, *n = vn;</div> -<div> uint8_t *pg = vg;</div> -<div> </div> -<div>- mm = dup_const(MO_8, mm);</div> -<div>+ mm = dup_const(MO_UB, mm);</div> -<div> for (i = 0; i < opr_sz; i += 1) {</div> -<div> uint64_t nn = n[i];</div> -<div> uint64_t pp = expand_pred_b(pg[H1(i)]);</div> -<div>@@ -1588,7 +1588,7 @@ void HELPER(sve_cpy_z_b)(void *vd, void *vg, uint64_t val, uint32_t desc)</div> -<div> uint64_t *d = vd;</div> -<div> uint8_t *pg = vg;</div> -<div> </div> -<div>- val = dup_const(MO_8, val);</div> -<div>+ val = dup_const(MO_UB, val);</div> -<div> for (i = 0; i < opr_sz; i += 1) {</div> -<div> d[i] = val & expand_pred_b(pg[H1(i)]);</div> -<div> }</div> -<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div> -<div>index d323147..f840b43 100644</div> -<div>--- a/target/arm/translate-a64.c</div> -<div>+++ b/target/arm/translate-a64.c</div> -<div>@@ -993,7 +993,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1002,7 +1002,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> case MO_32:</div> -<div> tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_8|MO_SIGN:</div> -<div>+ case MO_SB:</div> -<div> tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_16|MO_SIGN:</div> -<div>@@ -1025,13 +1025,13 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_16:</div> -<div> tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_8|MO_SIGN:</div> -<div>+ case MO_SB:</div> -<div> tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_16|MO_SIGN:</div> -<div>@@ -1052,7 +1052,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1074,7 +1074,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -12885,7 +12885,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> default: /* integer */</div> -<div> switch (size) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> case MO_64:</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div> -<div>index fa068b0..ec5fb11 100644</div> -<div>--- a/target/arm/translate-sve.c</div> -<div>+++ b/target/arm/translate-sve.c</div> -<div>@@ -1665,7 +1665,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div> -<div> desc = tcg_const_i32(simd_desc(vsz, vsz, 0));</div> -<div> </div> -<div> switch (esz) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> t32 = tcg_temp_new_i32();</div> -<div> tcg_gen_extrl_i64_i32(t32, val);</div> -<div> if (d) {</div> -<div>@@ -3308,7 +3308,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_sve_subri_b,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8,</div> -<div>+ .vece = MO_UB,</div> -<div> .scalar_first = true },</div> -<div> { .fni8 = tcg_gen_vec_sub16_i64,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div> -<div>index 7853462..39266cf 100644</div> -<div>--- a/target/arm/translate.c</div> -<div>+++ b/target/arm/translate.c</div> -<div>@@ -1474,7 +1474,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div> -<div> long offset = neon_element_offset(reg, ele, size);</div> -<div> </div> -<div> switch (size) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_st8_i32(var, cpu_env, offset);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1493,7 +1493,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div> -<div> long offset = neon_element_offset(reg, ele, size);</div> -<div> </div> -<div> switch (size) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_st8_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -4262,7 +4262,7 @@ const GVecGen2i ssra_op[4] = {</div> -<div> .fniv = gen_ssra_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_ssra,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = gen_ssra16_i64,</div> -<div> .fniv = gen_ssra_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4320,7 +4320,7 @@ const GVecGen2i usra_op[4] = {</div> -<div> .fniv = gen_usra_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_usra,</div> -<div>- .vece = MO_8, },</div> -<div>+ .vece = MO_UB, },</div> -<div> { .fni8 = gen_usra16_i64,</div> -<div> .fniv = gen_usra_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4341,7 +4341,7 @@ const GVecGen2i usra_op[4] = {</div> -<div> </div> -<div> static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_8, 0xff >> shift);</div> -<div>+ uint64_t mask = dup_const(MO_UB, 0xff >> shift);</div> -<div> TCGv_i64 t = tcg_temp_new_i64();</div> -<div> </div> -<div> tcg_gen_shri_i64(t, a, shift);</div> -<div>@@ -4400,7 +4400,7 @@ const GVecGen2i sri_op[4] = {</div> -<div> .fniv = gen_shr_ins_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sri,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = gen_shr16_ins_i64,</div> -<div> .fniv = gen_shr_ins_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4421,7 +4421,7 @@ const GVecGen2i sri_op[4] = {</div> -<div> </div> -<div> static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_8, 0xff << shift);</div> -<div>+ uint64_t mask = dup_const(MO_UB, 0xff << shift);</div> -<div> TCGv_i64 t = tcg_temp_new_i64();</div> -<div> </div> -<div> tcg_gen_shli_i64(t, a, shift);</div> -<div>@@ -4478,7 +4478,7 @@ const GVecGen2i sli_op[4] = {</div> -<div> .fniv = gen_shl_ins_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sli,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = gen_shl16_ins_i64,</div> -<div> .fniv = gen_shl_ins_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4574,7 +4574,7 @@ const GVecGen3 mla_op[4] = {</div> -<div> .fniv = gen_mla_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mla,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni4 = gen_mla16_i32,</div> -<div> .fniv = gen_mla_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4598,7 +4598,7 @@ const GVecGen3 mls_op[4] = {</div> -<div> .fniv = gen_mls_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mls,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni4 = gen_mls16_i32,</div> -<div> .fniv = gen_mls_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4645,7 +4645,7 @@ const GVecGen3 cmtst_op[4] = {</div> -<div> { .fni4 = gen_helper_neon_tst_u8,</div> -<div> .fniv = gen_cmtst_vec,</div> -<div> .opt_opc = vecop_list_cmtst,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni4 = gen_helper_neon_tst_u16,</div> -<div> .fniv = gen_cmtst_vec,</div> -<div> .opt_opc = vecop_list_cmtst,</div> -<div>@@ -4681,7 +4681,7 @@ const GVecGen4 uqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqadd_b,</div> -<div> .write_aofs = true,</div> -<div> .opt_opc = vecop_list_uqadd,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = gen_uqadd_vec,</div> -<div> .fno = gen_helper_gvec_uqadd_h,</div> -<div> .write_aofs = true,</div> -<div>@@ -4719,7 +4719,7 @@ const GVecGen4 sqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqadd_b,</div> -<div> .opt_opc = vecop_list_sqadd,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = gen_sqadd_vec,</div> -<div> .fno = gen_helper_gvec_sqadd_h,</div> -<div> .opt_opc = vecop_list_sqadd,</div> -<div>@@ -4757,7 +4757,7 @@ const GVecGen4 uqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqsub_b,</div> -<div> .opt_opc = vecop_list_uqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = gen_uqsub_vec,</div> -<div> .fno = gen_helper_gvec_uqsub_h,</div> -<div> .opt_opc = vecop_list_uqsub,</div> -<div>@@ -4795,7 +4795,7 @@ const GVecGen4 sqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqsub_b,</div> -<div> .opt_opc = vecop_list_sqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = gen_sqsub_vec,</div> -<div> .fno = gen_helper_gvec_sqsub_h,</div> -<div> .opt_opc = vecop_list_sqsub,</div> -<div>@@ -4972,15 +4972,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div> -<div> vec_size, vec_size);</div> -<div> break;</div> -<div> case 5: /* VBSL */</div> -<div>- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,</div> -<div>+ tcg_gen_gvec_bitsel(MO_UB, rd_ofs, rd_ofs, rn_ofs, rm_ofs,</div> -<div> vec_size, vec_size);</div> -<div> break;</div> -<div> case 6: /* VBIT */</div> -<div>- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,</div> -<div>+ tcg_gen_gvec_bitsel(MO_UB, rd_ofs, rm_ofs, rn_ofs, rd_ofs,</div> -<div> vec_size, vec_size);</div> -<div> break;</div> -<div> case 7: /* VBIF */</div> -<div>- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,</div> -<div>+ tcg_gen_gvec_bitsel(MO_UB, rd_ofs, rm_ofs, rd_ofs, rn_ofs,</div> -<div> vec_size, vec_size);</div> -<div> break;</div> -<div> }</div> -<div>@@ -6873,7 +6873,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div> -<div> return 1;</div> -<div> }</div> -<div> if (insn & (1 << 16)) {</div> -<div>- size = MO_8;</div> -<div>+ size = MO_UB;</div> -<div> element = (insn >> 17) & 7;</div> -<div> } else if (insn & (1 << 17)) {</div> -<div> size = MO_16;</div> -<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div> -<div>index 03150a8..0e45300 100644</div> -<div>--- a/target/i386/translate.c</div> -<div>+++ b/target/i386/translate.c</div> -<div>@@ -349,20 +349,20 @@ static inline TCGMemOp mo_64_32(TCGMemOp ot)</div> -<div> byte vs word opcodes. */</div> -<div> static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div> -<div> {</div> -<div>- return b & 1 ? ot : MO_8;</div> -<div>+ return b & 1 ? ot : MO_UB;</div> -<div> }</div> -<div> </div> -<div> /* Select size 8 if lsb of B is clear, else OT capped at 32.</div> -<div> Used for decoding operand size of port opcodes. */</div> -<div> static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div> -<div> {</div> -<div>- return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;</div> -<div>+ return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_UB;</div> -<div> }</div> -<div> </div> -<div> static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div> {</div> -<div> switch(ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> if (!byte_reg_is_xH(s, reg)) {</div> -<div> tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);</div> -<div> } else {</div> -<div>@@ -390,7 +390,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div> static inline</div> -<div> void gen_op_mov_v_reg(DisasContext *s, TCGMemOp ot, TCGv t0, int reg)</div> -<div> {</div> -<div>- if (ot == MO_8 && byte_reg_is_xH(s, reg)) {</div> -<div>+ if (ot == MO_UB && byte_reg_is_xH(s, reg)) {</div> -<div> tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);</div> -<div> } else {</div> -<div> tcg_gen_mov_tl(t0, cpu_regs[reg]);</div> -<div>@@ -523,7 +523,7 @@ static inline void gen_op_movl_T0_Dshift(DisasContext *s, TCGMemOp ot)</div> -<div> static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div> -<div> {</div> -<div> switch (size) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> if (sign) {</div> -<div> tcg_gen_ext8s_tl(dst, src);</div> -<div> } else {</div> -<div>@@ -580,7 +580,7 @@ void gen_op_jz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div> -<div> static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div> -<div> {</div> -<div> switch (ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> gen_helper_inb(v, cpu_env, n);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -597,7 +597,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div> -<div> static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div> -<div> {</div> -<div> switch (ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> gen_helper_outb(cpu_env, v, n);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -619,7 +619,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div> -<div> if (s->pe && (s->cpl > s->iopl || s->vm86)) {</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> switch (ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> gen_helper_check_iob(cpu_env, s->tmp2_i32);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1557,7 +1557,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div> -<div> tcg_gen_andi_tl(s->T1, s->T1, mask);</div> -<div> </div> -<div> switch (ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> /* Replicate the 8-bit input so that a 32-bit rotate works. */</div> -<div> tcg_gen_ext8u_tl(s->T0, s->T0);</div> -<div> tcg_gen_muli_tl(s->T0, s->T0, 0x01010101);</div> -<div>@@ -1661,7 +1661,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> tcg_gen_rotli_tl(s->T0, s->T0, op2);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> mask = 7;</div> -<div> goto do_shifts;</div> -<div> case MO_16:</div> -<div>@@ -1719,7 +1719,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> </div> -<div> if (is_right) {</div> -<div> switch (ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> gen_helper_rcrb(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1738,7 +1738,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> }</div> -<div> } else {</div> -<div> switch (ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> gen_helper_rclb(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -2184,7 +2184,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div> -<div> uint32_t ret;</div> -<div> </div> -<div> switch (ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> ret = x86_ldub_code(env, s);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -3784,7 +3784,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> if ((b & 0xff) == 0xf0) {</div> -<div>- ot = MO_8;</div> -<div>+ ot = MO_UB;</div> -<div> } else if (s->dflag != MO_64) {</div> -<div> ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);</div> -<div> } else {</div> -<div>@@ -4760,7 +4760,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> val = insn_get(env, s, ot);</div> -<div> break;</div> -<div> case 0x83:</div> -<div>- val = (int8_t)insn_get(env, s, MO_8);</div> -<div>+ val = (int8_t)insn_get(env, s, MO_UB);</div> -<div> break;</div> -<div> }</div> -<div> tcg_gen_movi_tl(s->T1, val);</div> -<div>@@ -4866,8 +4866,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> case 4: /* mul */</div> -<div> switch(ot) {</div> -<div>- case MO_8:</div> -<div>- gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);</div> -<div>+ case MO_UB:</div> -<div>+ gen_op_mov_v_reg(s, MO_UB, s->T1, R_EAX);</div> -<div> tcg_gen_ext8u_tl(s->T0, s->T0);</div> -<div> tcg_gen_ext8u_tl(s->T1, s->T1);</div> -<div> /* XXX: use 32 bit mul which could be faster */</div> -<div>@@ -4915,8 +4915,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> case 5: /* imul */</div> -<div> switch(ot) {</div> -<div>- case MO_8:</div> -<div>- gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);</div> -<div>+ case MO_UB:</div> -<div>+ gen_op_mov_v_reg(s, MO_UB, s->T1, R_EAX);</div> -<div> tcg_gen_ext8s_tl(s->T0, s->T0);</div> -<div> tcg_gen_ext8s_tl(s->T1, s->T1);</div> -<div> /* XXX: use 32 bit mul which could be faster */</div> -<div>@@ -4969,7 +4969,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> case 6: /* div */</div> -<div> switch(ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> gen_helper_divb_AL(cpu_env, s->T0);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -4988,7 +4988,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> case 7: /* idiv */</div> -<div> switch(ot) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> gen_helper_idivb_AL(cpu_env, s->T0);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -5157,7 +5157,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>- gen_op_mov_v_reg(s, MO_8, s->T0, R_EAX);</div> -<div>+ gen_op_mov_v_reg(s, MO_UB, s->T0, R_EAX);</div> -<div> tcg_gen_ext8s_tl(s->T0, s->T0);</div> -<div> gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div> -<div> break;</div> -<div>@@ -5205,7 +5205,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> val = insn_get(env, s, ot);</div> -<div> tcg_gen_movi_tl(s->T1, val);</div> -<div> } else if (b == 0x6b) {</div> -<div>- val = (int8_t)insn_get(env, s, MO_8);</div> -<div>+ val = (int8_t)insn_get(env, s, MO_UB);</div> -<div> tcg_gen_movi_tl(s->T1, val);</div> -<div> } else {</div> -<div> gen_op_mov_v_reg(s, ot, s->T1, reg);</div> -<div>@@ -5419,7 +5419,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (b == 0x68)</div> -<div> val = insn_get(env, s, ot);</div> -<div> else</div> -<div>- val = (int8_t)insn_get(env, s, MO_8);</div> -<div>+ val = (int8_t)insn_get(env, s, MO_UB);</div> -<div> tcg_gen_movi_tl(s->T0, val);</div> -<div> gen_push_v(s, s->T0);</div> -<div> break;</div> -<div>@@ -5573,7 +5573,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* d_ot is the size of destination */</div> -<div> d_ot = dflag;</div> -<div> /* ot is the size of source */</div> -<div>- ot = (b & 1) + MO_8;</div> -<div>+ ot = (b & 1) + MO_UB;</div> -<div> /* s_ot is the sign+size of source */</div> -<div> s_ot = b & 8 ? MO_SIGN | ot : ot;</div> -<div> </div> -<div>@@ -5661,13 +5661,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tcg_gen_add_tl(s->A0, s->A0, s->T0);</div> -<div> gen_extu(s->aflag, s->A0);</div> -<div> gen_add_A0_ds_seg(s);</div> -<div>- gen_op_ld_v(s, MO_8, s->T0, s->A0);</div> -<div>- gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);</div> -<div>+ gen_op_ld_v(s, MO_UB, s->T0, s->A0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UB, R_EAX, s->T0);</div> -<div> break;</div> -<div> case 0xb0 ... 0xb7: /* mov R, Ib */</div> -<div>- val = insn_get(env, s, MO_8);</div> -<div>+ val = insn_get(env, s, MO_UB);</div> -<div> tcg_gen_movi_tl(s->T0, val);</div> -<div>- gen_op_mov_reg_v(s, MO_8, (b & 7) | REX_B(s), s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UB, (b & 7) | REX_B(s), s->T0);</div> -<div> break;</div> -<div> case 0xb8 ... 0xbf: /* mov R, Iv */</div> -<div> #ifdef TARGET_X86_64</div> -<div>@@ -6637,7 +6637,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> }</div> -<div> goto do_ljmp;</div> -<div> case 0xeb: /* jmp Jb */</div> -<div>- tval = (int8_t)insn_get(env, s, MO_8);</div> -<div>+ tval = (int8_t)insn_get(env, s, MO_UB);</div> -<div> tval += s->pc - s->cs_base;</div> -<div> if (dflag == MO_16) {</div> -<div> tval &= 0xffff;</div> -<div>@@ -6645,7 +6645,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_jmp(s, tval);</div> -<div> break;</div> -<div> case 0x70 ... 0x7f: /* jcc Jb */</div> -<div>- tval = (int8_t)insn_get(env, s, MO_8);</div> -<div>+ tval = (int8_t)insn_get(env, s, MO_UB);</div> -<div> goto do_jcc;</div> -<div> case 0x180 ... 0x18f: /* jcc Jv */</div> -<div> if (dflag != MO_16) {</div> -<div>@@ -6666,7 +6666,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x190 ... 0x19f: /* setcc Gv */</div> -<div> modrm = x86_ldub_code(env, s);</div> -<div> gen_setcc1(s, b, s->T0);</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UB, OR_TMP0, 1);</div> -<div> break;</div> -<div> case 0x140 ... 0x14f: /* cmov Gv, Ev */</div> -<div> if (!(s->cpuid_features & CPUID_CMOV)) {</div> -<div>@@ -6751,7 +6751,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x9e: /* sahf */</div> -<div> if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))</div> -<div> goto illegal_op;</div> -<div>- gen_op_mov_v_reg(s, MO_8, s->T0, R_AH);</div> -<div>+ gen_op_mov_v_reg(s, MO_UB, s->T0, R_AH);</div> -<div> gen_compute_eflags(s);</div> -<div> tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C);</div> -<div>@@ -6763,7 +6763,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_compute_eflags(s);</div> -<div> /* Note: gen_compute_eflags() only gives the condition codes */</div> -<div> tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02);</div> -<div>- gen_op_mov_reg_v(s, MO_8, R_AH, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UB, R_AH, s->T0);</div> -<div> break;</div> -<div> case 0xf5: /* cmc */</div> -<div> gen_compute_eflags(s);</div> -<div>@@ -7137,7 +7137,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> goto illegal_op;</div> -<div> gen_compute_eflags_c(s, s->T0);</div> -<div> tcg_gen_neg_tl(s->T0, s->T0);</div> -<div>- gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UB, R_EAX, s->T0);</div> -<div> break;</div> -<div> case 0xe0: /* loopnz */</div> -<div> case 0xe1: /* loopz */</div> -<div>@@ -7146,7 +7146,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> {</div> -<div> TCGLabel *l1, *l2, *l3;</div> -<div> </div> -<div>- tval = (int8_t)insn_get(env, s, MO_8);</div> -<div>+ tval = (int8_t)insn_get(env, s, MO_UB);</div> -<div> next_eip = s->pc - s->cs_base;</div> -<div> tval += next_eip;</div> -<div> if (dflag == MO_16) {</div> -<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div> -<div>index 3575eff..20a9777 100644</div> -<div>--- a/target/mips/translate.c</div> -<div>+++ b/target/mips/translate.c</div> -<div>@@ -3684,7 +3684,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,</div> -<div> mem_idx = MIPS_HFLAG_UM;</div> -<div> /* fall through */</div> -<div> case OPC_SB:</div> -<div>- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8);</div> -<div>+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_UB);</div> -<div> break;</div> -<div> case OPC_SWLE:</div> -<div> mem_idx = MIPS_HFLAG_UM;</div> -<div>@@ -20193,7 +20193,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)</div> -<div> check_nms(ctx);</div> -<div> gen_load_gpr(t1, rd);</div> -<div> tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,</div> -<div>- MO_8);</div> -<div>+ MO_UB);</div> -<div> break;</div> -<div> case NM_SHX:</div> -<div> /*case NM_SHXS:*/</div> -<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div> -<div>index 663275b..4130dd1 100644</div> -<div>--- a/target/ppc/translate/vmx-impl.inc.c</div> -<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div> -<div>@@ -403,7 +403,7 @@ static void glue(gen_, name)(DisasContext *ctx) \</div> -<div> tcg_temp_free_ptr(rb); \</div> -<div> }</div> -<div> </div> -<div>-GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);</div> -<div>+GEN_VXFORM_V(vaddubm, MO_UB, tcg_gen_gvec_add, 0, 0);</div> -<div> GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \</div> -<div> vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div> -<div> GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);</div> -<div>@@ -411,23 +411,23 @@ GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);</div> -<div> GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div> -<div>-GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);</div> -<div>+GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div> -<div> GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);</div> -<div> GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);</div> -<div> GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div> -<div>-GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);</div> -<div>+GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div> -<div> GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);</div> -<div> GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);</div> -<div> GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div> -<div>-GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);</div> -<div>+GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div> -<div> GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);</div> -<div> GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);</div> -<div> GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div> -<div>-GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);</div> -<div>+GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div> -<div> GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);</div> -<div> GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);</div> -<div> GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div> -<div>-GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);</div> -<div>+GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div> -<div> GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);</div> -<div> GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);</div> -<div> GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div> -<div>@@ -530,18 +530,18 @@ GEN_VXFORM(vmuleuw, 4, 10);</div> -<div> GEN_VXFORM(vmulesb, 4, 12);</div> -<div> GEN_VXFORM(vmulesh, 4, 13);</div> -<div> GEN_VXFORM(vmulesw, 4, 14);</div> -<div>-GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);</div> -<div>+GEN_VXFORM_V(vslb, MO_UB, tcg_gen_gvec_shlv, 2, 4);</div> -<div> GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);</div> -<div> GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);</div> -<div> GEN_VXFORM(vrlwnm, 2, 6);</div> -<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div> -<div>-GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);</div> -<div>+GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div> -<div> GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);</div> -<div> GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);</div> -<div> GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div> -<div>-GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);</div> -<div>+GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div> -<div> GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);</div> -<div> GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);</div> -<div> GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div> -<div>@@ -589,20 +589,20 @@ static void glue(gen_, NAME)(DisasContext *ctx) \</div> -<div> 16, 16, &g); \</div> -<div> }</div> -<div> </div> -<div>-GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);</div> -<div>+GEN_VXFORM_SAT(vaddubs, MO_UB, add, usadd, 0, 8);</div> -<div> GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \</div> -<div> vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div> -<div> GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);</div> -<div> GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vmul10euq, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);</div> -<div>-GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);</div> -<div>+GEN_VXFORM_SAT(vaddsbs, MO_UB, add, ssadd, 0, 12);</div> -<div> GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);</div> -<div> GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);</div> -<div>-GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);</div> -<div>+GEN_VXFORM_SAT(vsububs, MO_UB, sub, ussub, 0, 24);</div> -<div> GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);</div> -<div> GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);</div> -<div>-GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);</div> -<div>+GEN_VXFORM_SAT(vsubsbs, MO_UB, sub, sssub, 0, 28);</div> -<div> GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);</div> -<div> GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);</div> -<div> GEN_VXFORM(vadduqm, 0, 4);</div> -<div>@@ -912,7 +912,7 @@ static void glue(gen_, name)(DisasContext *ctx) \</div> -<div> tcg_temp_free_ptr(rd); \</div> -<div> }</div> -<div> </div> -<div>-GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);</div> -<div>+GEN_VXFORM_VSPLT(vspltb, MO_UB, 6, 8);</div> -<div> GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);</div> -<div> GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);</div> -<div> GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);</div> -<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div> -<div>index ac0d8b6..415747f 100644</div> -<div>--- a/target/s390x/translate.c</div> -<div>+++ b/target/s390x/translate.c</div> -<div>@@ -154,7 +154,7 @@ static inline int vec_full_reg_offset(uint8_t reg)</div> -<div> </div> -<div> static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div> -<div> {</div> -<div>- /* Convert element size (es) - e.g. MO_8 - to bytes */</div> -<div>+ /* Convert element size (es) - e.g. MO_UB - to bytes */</div> -<div> const uint8_t bytes = 1 << es;</div> -<div> int offs = enr * bytes;</div> -<div> </div> -<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div> -<div>index 41d5cf8..bb424c8 100644</div> -<div>--- a/target/s390x/translate_vx.inc.c</div> -<div>+++ b/target/s390x/translate_vx.inc.c</div> -<div>@@ -30,7 +30,7 @@</div> -<div> * Sizes:</div> -<div> * On s390x, the operand size (oprsz) and the maximum size (maxsz) are</div> -<div> * always 16 (128 bit). What gvec code calls "vece", s390x calls "es",</div> -<div>- * a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only</div> -<div>+ * a.k.a. "element size". These values nicely map to MO_UB ... MO_64. Only</div> -<div> * 128 bit element size has to be treated in a special way (MO_64 + 1).</div> -<div> * We will use ES_* instead of MO_* for this reason in this file.</div> -<div> *</div> -<div>@@ -46,7 +46,7 @@</div> -<div> #define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es))</div> -<div> #define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)</div> -<div> </div> -<div>-#define ES_8 MO_8</div> -<div>+#define ES_8 MO_UB</div> -<div> #define ES_16 MO_16</div> -<div> #define ES_32 MO_32</div> -<div> #define ES_64 MO_64</div> -<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div> -<div>index a6e3618..b813054 100644</div> -<div>--- a/target/s390x/vec.h</div> -<div>+++ b/target/s390x/vec.h</div> -<div>@@ -76,7 +76,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div> -<div> uint8_t es)</div> -<div> {</div> -<div> switch (es) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> return s390_vec_read_element8(v, enr);</div> -<div> case MO_16:</div> -<div> return s390_vec_read_element16(v, enr);</div> -<div>@@ -121,7 +121,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div> -<div> uint8_t es, uint64_t data)</div> -<div> {</div> -<div> switch (es) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> s390_vec_write_element8(v, enr, data);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div> -<div>index 0713448..e4e0845 100644</div> -<div>--- a/tcg/aarch64/tcg-target.inc.c</div> -<div>+++ b/tcg/aarch64/tcg-target.inc.c</div> -<div>@@ -429,20 +429,20 @@ typedef enum {</div> -<div> </div> -<div> /* Load/store register. Described here as 3.3.12, but the helper</div> -<div> that emits them can transform to 3.3.10 or 3.3.13. */</div> -<div>- I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,</div> -<div>+ I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div> -<div> I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,</div> -<div> I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,</div> -<div> I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div> -<div> </div> -<div>- I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,</div> -<div>+ I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div> -<div> I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,</div> -<div> I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,</div> -<div> I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div> -<div> </div> -<div>- I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,</div> -<div>+ I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div> -<div> I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,</div> -<div> </div> -<div>- I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,</div> -<div>+ I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_UB << 30,</div> -<div> I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,</div> -<div> I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,</div> -<div> </div> -<div>@@ -862,7 +862,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div> -<div> int cmode, imm8, i;</div> -<div> </div> -<div> /* Test all bytes equal first. */</div> -<div>- if (v64 == dup_const(MO_8, v64)) {</div> -<div>+ if (v64 == dup_const(MO_UB, v64)) {</div> -<div> imm8 = (uint8_t)v64;</div> -<div> tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);</div> -<div> return;</div> -<div>@@ -1772,7 +1772,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div> -<div> const TCGMemOp bswap = memop & MO_BSWAP;</div> -<div> </div> -<div> switch (memop & MO_SIZE) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -2186,7 +2186,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div> -<div> </div> -<div> case INDEX_op_ext8s_i64:</div> -<div> case INDEX_op_ext8s_i32:</div> -<div>- tcg_out_sxt(s, ext, MO_8, a0, a1);</div> -<div>+ tcg_out_sxt(s, ext, MO_UB, a0, a1);</div> -<div> break;</div> -<div> case INDEX_op_ext16s_i64:</div> -<div> case INDEX_op_ext16s_i32:</div> -<div>@@ -2198,7 +2198,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div> -<div> break;</div> -<div> case INDEX_op_ext8u_i64:</div> -<div> case INDEX_op_ext8u_i32:</div> -<div>- tcg_out_uxt(s, MO_8, a0, a1);</div> -<div>+ tcg_out_uxt(s, MO_UB, a0, a1);</div> -<div> break;</div> -<div> case INDEX_op_ext16u_i64:</div> -<div> case INDEX_op_ext16u_i32:</div> -<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div> -<div>index ece88dc..542ffa8 100644</div> -<div>--- a/tcg/arm/tcg-target.inc.c</div> -<div>+++ b/tcg/arm/tcg-target.inc.c</div> -<div>@@ -1429,7 +1429,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> datalo = lb->datalo_reg;</div> -<div> datahi = lb->datahi_reg;</div> -<div> switch (opc & MO_SIZE) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> argreg = tcg_out_arg_reg8(s, argreg, datalo);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1621,7 +1621,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div> -<div> TCGMemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> switch (opc & MO_SIZE) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_st8_r(s, cond, datalo, addrlo, addend);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1666,7 +1666,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div> -<div> TCGMemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> switch (opc & MO_SIZE) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div> -<div>index 6ddeebf..0d68ba4 100644</div> -<div>--- a/tcg/i386/tcg-target.inc.c</div> -<div>+++ b/tcg/i386/tcg-target.inc.c</div> -<div>@@ -888,7 +888,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a);</div> -<div> } else {</div> -<div> switch (vece) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> /* ??? With zero in a register, use PSHUFB. */</div> -<div> tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a);</div> -<div> a = r;</div> -<div>@@ -932,7 +932,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> tcg_out8(s, 0); /* imm8 */</div> -<div> tcg_out_dup_vec(s, type, vece, r, r);</div> -<div> break;</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset);</div> -<div> tcg_out8(s, 0); /* imm8 */</div> -<div> tcg_out_dup_vec(s, type, vece, r, r);</div> -<div>@@ -2154,7 +2154,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div> -<div> }</div> -<div> </div> -<div> switch (memop & MO_SIZE) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> /* In 32-bit mode, 8-bit stores can only happen from [abcd]x.</div> -<div> Use the scratch register if necessary. */</div> -<div> if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) {</div> -<div>@@ -2901,7 +2901,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div> -<div> tcg_debug_assert(vece != MO_64);</div> -<div> sub = 4;</div> -<div> gen_shift:</div> -<div>- tcg_debug_assert(vece != MO_8);</div> -<div>+ tcg_debug_assert(vece != MO_UB);</div> -<div> insn = shift_imm_insn[vece];</div> -<div> if (type == TCG_TYPE_V256) {</div> -<div> insn |= P_VEXL;</div> -<div>@@ -3273,12 +3273,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> </div> -<div> case INDEX_op_shli_vec:</div> -<div> case INDEX_op_shri_vec:</div> -<div>- /* We must expand the operation for MO_8. */</div> -<div>- return vece == MO_8 ? -1 : 1;</div> -<div>+ /* We must expand the operation for MO_UB. */</div> -<div>+ return vece == MO_UB ? -1 : 1;</div> -<div> </div> -<div> case INDEX_op_sari_vec:</div> -<div>- /* We must expand the operation for MO_8. */</div> -<div>- if (vece == MO_8) {</div> -<div>+ /* We must expand the operation for MO_UB. */</div> -<div>+ if (vece == MO_UB) {</div> -<div> return -1;</div> -<div> }</div> -<div> /* We can emulate this for MO_64, but it does not pay off</div> -<div>@@ -3301,8 +3301,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> return have_avx2 && vece == MO_32;</div> -<div> </div> -<div> case INDEX_op_mul_vec:</div> -<div>- if (vece == MO_8) {</div> -<div>- /* We can expand the operation for MO_8. */</div> -<div>+ if (vece == MO_UB) {</div> -<div>+ /* We can expand the operation for MO_UB. */</div> -<div> return -1;</div> -<div> }</div> -<div> if (vece == MO_64) {</div> -<div>@@ -3332,7 +3332,7 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div> -<div> {</div> -<div> TCGv_vec t1, t2;</div> -<div> </div> -<div>- tcg_debug_assert(vece == MO_8);</div> -<div>+ tcg_debug_assert(vece == MO_UB);</div> -<div> </div> -<div> t1 = tcg_temp_new_vec(type);</div> -<div> t2 = tcg_temp_new_vec(type);</div> -<div>@@ -3346,9 +3346,9 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div> -<div> (3) Step 2 leaves high half zero such that PACKUSWB</div> -<div> (pack with unsigned saturation) does not modify</div> -<div> the quantity. */</div> -<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div> -<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div> -<div> </div> -<div> if (shr) {</div> -<div>@@ -3361,7 +3361,7 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div> -<div> tcg_gen_shri_vec(MO_16, t2, t2, 8);</div> -<div> }</div> -<div> </div> -<div>- vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));</div> -<div> tcg_temp_free_vec(t1);</div> -<div> tcg_temp_free_vec(t2);</div> -<div>@@ -3373,17 +3373,17 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div> -<div> TCGv_vec t1, t2;</div> -<div> </div> -<div> switch (vece) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> /* Unpack to W, shift, and repack, as in expand_vec_shi. */</div> -<div> t1 = tcg_temp_new_vec(type);</div> -<div> t2 = tcg_temp_new_vec(type);</div> -<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div> -<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div> -<div> tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);</div> -<div> tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);</div> -<div>- vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_packss_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));</div> -<div> tcg_temp_free_vec(t1);</div> -<div> tcg_temp_free_vec(t2);</div> -<div>@@ -3425,7 +3425,7 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div> -<div> {</div> -<div> TCGv_vec t1, t2, t3, t4;</div> -<div> </div> -<div>- tcg_debug_assert(vece == MO_8);</div> -<div>+ tcg_debug_assert(vece == MO_UB);</div> -<div> </div> -<div> /*</div> -<div> * Unpack v1 bytes to words, 0 | x.</div> -<div>@@ -3442,13 +3442,13 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div> -<div> t1 = tcg_temp_new_vec(TCG_TYPE_V128);</div> -<div> t2 = tcg_temp_new_vec(TCG_TYPE_V128);</div> -<div> tcg_gen_dup16i_vec(t2, 0);</div> -<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_UB,</div> -<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));</div> -<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_UB,</div> -<div> tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));</div> -<div> tcg_gen_mul_vec(MO_16, t1, t1, t2);</div> -<div> tcg_gen_shri_vec(MO_16, t1, t1, 8);</div> -<div>- vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_UB,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1));</div> -<div> tcg_temp_free_vec(t1);</div> -<div> tcg_temp_free_vec(t2);</div> -<div>@@ -3461,19 +3461,19 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div> -<div> t3 = tcg_temp_new_vec(type);</div> -<div> t4 = tcg_temp_new_vec(type);</div> -<div> tcg_gen_dup16i_vec(t4, 0);</div> -<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));</div> -<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));</div> -<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));</div> -<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));</div> -<div> tcg_gen_mul_vec(MO_16, t1, t1, t2);</div> -<div> tcg_gen_mul_vec(MO_16, t3, t3, t4);</div> -<div> tcg_gen_shri_vec(MO_16, t1, t1, 8);</div> -<div> tcg_gen_shri_vec(MO_16, t3, t3, 8);</div> -<div>- vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,</div> -<div>+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3));</div> -<div> tcg_temp_free_vec(t1);</div> -<div> tcg_temp_free_vec(t2);</div> -<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div> -<div>index 41bff32..c6d13ea 100644</div> -<div>--- a/tcg/mips/tcg-target.inc.c</div> -<div>+++ b/tcg/mips/tcg-target.inc.c</div> -<div>@@ -1380,7 +1380,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);</div> -<div> }</div> -<div> switch (s_bits) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1566,7 +1566,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> }</div> -<div> </div> -<div> switch (opc & (MO_SIZE | MO_BSWAP)) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_opc_imm(s, OPC_SB, lo, base, 0);</div> -<div> break;</div> -<div> </div> -<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div> -<div>index 3e76bf5..9c60c0f 100644</div> -<div>--- a/tcg/riscv/tcg-target.inc.c</div> -<div>+++ b/tcg/riscv/tcg-target.inc.c</div> -<div>@@ -1101,7 +1101,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);</div> -<div> tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);</div> -<div> switch (s_bits) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_ext8u(s, a2, a2);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1216,7 +1216,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> g_assert(!bswap);</div> -<div> </div> -<div> switch (opc & (MO_SSIZE)) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_opc_store(s, OPC_SB, base, lo, 0);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div> -<div>index 10b1cea..479ee2e 100644</div> -<div>--- a/tcg/sparc/tcg-target.inc.c</div> -<div>+++ b/tcg/sparc/tcg-target.inc.c</div> -<div>@@ -882,7 +882,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div> -<div> * required by the MO_* value op; do nothing for 64 bit.</div> -<div> */</div> -<div> switch (op & MO_SIZE) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_out_arithi(s, r, r, 0xff, ARITH_AND);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div> -<div>index 17679b6..9658c36 100644</div> -<div>--- a/tcg/tcg-op-gvec.c</div> -<div>+++ b/tcg/tcg-op-gvec.c</div> -<div>@@ -306,7 +306,7 @@ static void expand_clr(uint32_t dofs, uint32_t maxsz);</div> -<div> uint64_t (dup_const)(unsigned vece, uint64_t c)</div> -<div> {</div> -<div> switch (vece) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> return 0x0101010101010101ull * (uint8_t)c;</div> -<div> case MO_16:</div> -<div> return 0x0001000100010001ull * (uint16_t)c;</div> -<div>@@ -323,7 +323,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div> -<div> static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div> -<div> {</div> -<div> switch (vece) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_ext8u_i32(out, in);</div> -<div> tcg_gen_muli_i32(out, out, 0x01010101);</div> -<div> break;</div> -<div>@@ -341,7 +341,7 @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div> -<div> static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div> -<div> {</div> -<div> switch (vece) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_ext8u_i64(out, in);</div> -<div> tcg_gen_muli_i64(out, out, 0x0101010101010101ull);</div> -<div> break;</div> -<div>@@ -556,7 +556,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> t_32 = tcg_temp_new_i32();</div> -<div> if (in_64) {</div> -<div> tcg_gen_extrl_i64_i32(t_32, in_64);</div> -<div>- } else if (vece == MO_8) {</div> -<div>+ } else if (vece == MO_UB) {</div> -<div> tcg_gen_movi_i32(t_32, in_c & 0xff);</div> -<div> } else if (vece == MO_16) {</div> -<div> tcg_gen_movi_i32(t_32, in_c & 0xffff);</div> -<div>@@ -581,7 +581,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> /* Likewise, but with zero. */</div> -<div> static void expand_clr(uint32_t dofs, uint32_t maxsz)</div> -<div> {</div> -<div>- do_dup(MO_8, dofs, maxsz, maxsz, NULL, NULL, 0);</div> -<div>+ do_dup(MO_UB, dofs, maxsz, maxsz, NULL, NULL, 0);</div> -<div> }</div> -<div> </div> -<div> /* Expand OPSZ bytes worth of two-operand operations using i32 elements. */</div> -<div>@@ -1456,7 +1456,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> } else if (vece <= MO_32) {</div> -<div> TCGv_i32 in = tcg_temp_new_i32();</div> -<div> switch (vece) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> tcg_gen_ld8u_i32(in, cpu_env, aofs);</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -1533,7 +1533,7 @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,</div> -<div> uint32_t maxsz, uint8_t x)</div> -<div> {</div> -<div> check_size_align(oprsz, maxsz, dofs);</div> -<div>- do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div>+ do_dup(MO_UB, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div>@@ -1572,7 +1572,7 @@ static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)</div> -<div> </div> -<div> void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div> -<div> {</div> -<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));</div> -<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UB, 0x80));</div> -<div> gen_addv_mask(d, a, b, m);</div> -<div> tcg_temp_free_i64(m);</div> -<div> }</div> -<div>@@ -1608,7 +1608,7 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_add8,</div> -<div> .opt_opc = vecop_list_add,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_add16_i64,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_add16,</div> -<div>@@ -1639,7 +1639,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_adds8,</div> -<div> .opt_opc = vecop_list_add,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_add16_i64,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_adds16,</div> -<div>@@ -1680,7 +1680,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_subs8,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_sub16_i64,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_subs16,</div> -<div>@@ -1725,7 +1725,7 @@ static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)</div> -<div> </div> -<div> void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div> -<div> {</div> -<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));</div> -<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UB, 0x80));</div> -<div> gen_subv_mask(d, a, b, m);</div> -<div> tcg_temp_free_i64(m);</div> -<div> }</div> -<div>@@ -1759,7 +1759,7 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_sub8,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_sub16_i64,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_sub16,</div> -<div>@@ -1791,7 +1791,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_mul8,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_mul16,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>@@ -1820,7 +1820,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_muls8,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_muls16,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>@@ -1858,7 +1858,7 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_ssadd_vec,</div> -<div> .fno = gen_helper_gvec_ssadd8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_ssadd_vec,</div> -<div> .fno = gen_helper_gvec_ssadd16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1884,7 +1884,7 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_sssub_vec,</div> -<div> .fno = gen_helper_gvec_sssub8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_sssub_vec,</div> -<div> .fno = gen_helper_gvec_sssub16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1926,7 +1926,7 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_usadd_vec,</div> -<div> .fno = gen_helper_gvec_usadd8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_usadd_vec,</div> -<div> .fno = gen_helper_gvec_usadd16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1970,7 +1970,7 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_ussub_vec,</div> -<div> .fno = gen_helper_gvec_ussub8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_ussub_vec,</div> -<div> .fno = gen_helper_gvec_ussub16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1998,7 +1998,7 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_smin_vec,</div> -<div> .fno = gen_helper_gvec_smin8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_smin_vec,</div> -<div> .fno = gen_helper_gvec_smin16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -2026,7 +2026,7 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_umin_vec,</div> -<div> .fno = gen_helper_gvec_umin8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_umin_vec,</div> -<div> .fno = gen_helper_gvec_umin16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -2054,7 +2054,7 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_smax_vec,</div> -<div> .fno = gen_helper_gvec_smax8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_smax_vec,</div> -<div> .fno = gen_helper_gvec_smax16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -2082,7 +2082,7 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_umax_vec,</div> -<div> .fno = gen_helper_gvec_umax8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_umax_vec,</div> -<div> .fno = gen_helper_gvec_umax16,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -2120,7 +2120,7 @@ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)</div> -<div> </div> -<div> void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)</div> -<div> {</div> -<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));</div> -<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UB, 0x80));</div> -<div> gen_negv_mask(d, b, m);</div> -<div> tcg_temp_free_i64(m);</div> -<div> }</div> -<div>@@ -2155,7 +2155,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_neg_vec,</div> -<div> .fno = gen_helper_gvec_neg8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_neg16_i64,</div> -<div> .fniv = tcg_gen_neg_vec,</div> -<div> .fno = gen_helper_gvec_neg16,</div> -<div>@@ -2201,7 +2201,7 @@ static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece)</div> -<div> </div> -<div> static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b)</div> -<div> {</div> -<div>- gen_absv_mask(d, b, MO_8);</div> -<div>+ gen_absv_mask(d, b, MO_UB);</div> -<div> }</div> -<div> </div> -<div> static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b)</div> -<div>@@ -2218,7 +2218,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_abs_vec,</div> -<div> .fno = gen_helper_gvec_abs8,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_abs16_i64,</div> -<div> .fniv = tcg_gen_abs_vec,</div> -<div> .fno = gen_helper_gvec_abs16,</div> -<div>@@ -2454,7 +2454,7 @@ void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> </div> -<div> void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_8, 0xff << c);</div> -<div>+ uint64_t mask = dup_const(MO_UB, 0xff << c);</div> -<div> tcg_gen_shli_i64(d, a, c);</div> -<div> tcg_gen_andi_i64(d, d, mask);</div> -<div> }</div> -<div>@@ -2475,7 +2475,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shli_vec,</div> -<div> .fno = gen_helper_gvec_shl8i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_shl16i_i64,</div> -<div> .fniv = tcg_gen_shli_vec,</div> -<div> .fno = gen_helper_gvec_shl16i,</div> -<div>@@ -2505,7 +2505,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> </div> -<div> void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_8, 0xff >> c);</div> -<div>+ uint64_t mask = dup_const(MO_UB, 0xff >> c);</div> -<div> tcg_gen_shri_i64(d, a, c);</div> -<div> tcg_gen_andi_i64(d, d, mask);</div> -<div> }</div> -<div>@@ -2526,7 +2526,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shri_vec,</div> -<div> .fno = gen_helper_gvec_shr8i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_shr16i_i64,</div> -<div> .fniv = tcg_gen_shri_vec,</div> -<div> .fno = gen_helper_gvec_shr16i,</div> -<div>@@ -2556,8 +2556,8 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> </div> -<div> void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> {</div> -<div>- uint64_t s_mask = dup_const(MO_8, 0x80 >> c);</div> -<div>- uint64_t c_mask = dup_const(MO_8, 0xff >> c);</div> -<div>+ uint64_t s_mask = dup_const(MO_UB, 0x80 >> c);</div> -<div>+ uint64_t c_mask = dup_const(MO_UB, 0xff >> c);</div> -<div> TCGv_i64 s = tcg_temp_new_i64();</div> -<div> </div> -<div> tcg_gen_shri_i64(d, a, c);</div> -<div>@@ -2591,7 +2591,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sari_vec,</div> -<div> .fno = gen_helper_gvec_sar8i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fni8 = tcg_gen_vec_sar16i_i64,</div> -<div> .fniv = tcg_gen_sari_vec,</div> -<div> .fno = gen_helper_gvec_sar16i,</div> -<div>@@ -2880,7 +2880,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_shlv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shl8v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_shlv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shl16v,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -2943,7 +2943,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_shrv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shr8v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_shrv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shr16v,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -3006,7 +3006,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_sarv_mod_vec,</div> -<div> .fno = gen_helper_gvec_sar8v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_8 },</div> -<div>+ .vece = MO_UB },</div> -<div> { .fniv = tcg_gen_sarv_mod_vec,</div> -<div> .fno = gen_helper_gvec_sar16v,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -3129,7 +3129,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div> -<div> check_overlap_3(dofs, aofs, bofs, maxsz);</div> -<div> </div> -<div> if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {</div> -<div>- do_dup(MO_8, dofs, oprsz, maxsz,</div> -<div>+ do_dup(MO_UB, dofs, oprsz, maxsz,</div> -<div> NULL, NULL, -(cond == TCG_COND_ALWAYS));</div> -<div> return;</div> -<div> }</div> -<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div> -<div>index 6714991..d7ffc9e 100644</div> -<div>--- a/tcg/tcg-op-vec.c</div> -<div>+++ b/tcg/tcg-op-vec.c</div> -<div>@@ -275,7 +275,7 @@ void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)</div> -<div> </div> -<div> void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)</div> -<div> {</div> -<div>- do_dupi_vec(r, MO_REG, dup_const(MO_8, a));</div> -<div>+ do_dupi_vec(r, MO_REG, dup_const(MO_UB, a));</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)</div> -<div>@@ -752,13 +752,13 @@ void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,</div> -<div> tcg_debug_assert(ct->base_type >= type);</div> -<div> </div> -<div> if (TCG_TARGET_HAS_bitsel_vec) {</div> -<div>- vec_gen_4(INDEX_op_bitsel_vec, type, MO_8,</div> -<div>+ vec_gen_4(INDEX_op_bitsel_vec, type, MO_UB,</div> -<div> temp_arg(rt), temp_arg(at), temp_arg(bt), temp_arg(ct));</div> -<div> } else {</div> -<div> TCGv_vec t = tcg_temp_new_vec(type);</div> -<div>- tcg_gen_and_vec(MO_8, t, a, b);</div> -<div>- tcg_gen_andc_vec(MO_8, r, c, a);</div> -<div>- tcg_gen_or_vec(MO_8, r, r, t);</div> -<div>+ tcg_gen_and_vec(MO_UB, t, a, b);</div> -<div>+ tcg_gen_andc_vec(MO_UB, r, c, a);</div> -<div>+ tcg_gen_or_vec(MO_UB, r, r, t);</div> -<div> tcg_temp_free_vec(t);</div> -<div> }</div> -<div> }</div> -<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div> -<div>index 587d092..61eda33 100644</div> -<div>--- a/tcg/tcg-op.c</div> -<div>+++ b/tcg/tcg-op.c</div> -<div>@@ -2720,7 +2720,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div> -<div> (void)get_alignment_bits(op);</div> -<div> </div> -<div> switch (op & MO_SIZE) {</div> -<div>- case MO_8:</div> -<div>+ case MO_UB:</div> -<div> op &= ~MO_BSWAP;</div> -<div> break;</div> -<div> case MO_16:</div> -<div>@@ -3024,7 +3024,7 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64);</div> -<div> #endif</div> -<div> </div> -<div> static void * const table_cmpxchg[16] = {</div> -<div>- [MO_8] = gen_helper_atomic_cmpxchgb,</div> -<div>+ [MO_UB] = gen_helper_atomic_cmpxchgb,</div> -<div> [MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div> -<div> [MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div> -<div> [MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div> -<div>@@ -3248,7 +3248,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div> -<div> </div> -<div> #define GEN_ATOMIC_HELPER(NAME, OP, NEW) \</div> -<div> static void * const table_##NAME[16] = { \</div> -<div>- [MO_8] = gen_helper_atomic_##NAME##b, \</div> -<div>+ [MO_UB] = gen_helper_atomic_##NAME##b, \</div> -<div> [MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \</div> -<div> [MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \</div> -<div> [MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \</div> -<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div> -<div>index b411e17..5636d6b 100644</div> -<div>--- a/tcg/tcg.h</div> -<div>+++ b/tcg/tcg.h</div> -<div>@@ -1302,7 +1302,7 @@ uint64_t dup_const(unsigned vece, uint64_t c);</div> -<div> </div> -<div> #define dup_const(VECE, C) \</div> -<div> (__builtin_constant_p(VECE) \</div> -<div>- ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \</div> -<div>+ ? ((VECE) == MO_UB ? 0x0101010101010101ull * (uint8_t)(C) \</div> -<div> : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \</div> -<div> : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \</div> -<div> : dup_const(VECE, C)) \</div> -<div>-- </div> -<div>1.8.3.1</div> -<div><br> -<br> -</div> -<p><br> -</p> -</body> -</html> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index e54d0ae..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/html; charset="iso-8859-1" -Content-Transfer-Encoding: quoted-printable diff --git a/a/content_digest b/N1/content_digest index a6f006f..2b2c3a9 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,34 +1,34 @@ "ref\0e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net\0" "From\0<tony.nguyen@bt.com>\0" - "Subject\0[Qemu-riscv] [Qemu-devel] [PATCH v2 01/20] tcg: Replace MO_8 with MO_UB alias\0" + "Subject\0[Qemu-devel] [PATCH v2 01/20] tcg: Replace MO_8 with MO_UB alias\0" "Date\0Mon, 22 Jul 2019 15:38:09 +0000\0" "To\0<qemu-devel@nongnu.org>\0" - "Cc\0<peter.maydell@linaro.org>" - <walling@linux.ibm.com> - <david@redhat.com> - <palmer@sifive.com> - <mark.cave-ayland@ilande.co.uk> - <Alistair.Francis@wdc.com> - <arikalo@wavecomp.com> - <mst@redhat.com> - <pasic@linux.ibm.com> - <borntraeger@de.ibm.com> - <rth@twiddle.net> - <atar4qemu@gmail.com> - <ehabkost@redhat.com> - <sw@weilnetz.de> - <alex.williamson@redhat.com> - <qemu-arm@nongnu.org> - <david@gibson.dropbear.id.au> - <qemu-riscv@nongnu.org> - <cohuck@redhat.com> - <claudio.fontana@huawei.com> - <qemu-s390x@nongnu.org> - <qemu-ppc@nongnu.org> - <amarkovic@wavecomp.com> - <pbonzini@redhat.com> - " <aurelien@aurel32.net>\0" - "\01:1\0" + "Cc\0peter.maydell@linaro.org" + walling@linux.ibm.com + mst@redhat.com + palmer@sifive.com + mark.cave-ayland@ilande.co.uk + Alistair.Francis@wdc.com + arikalo@wavecomp.com + david@redhat.com + pasic@linux.ibm.com + borntraeger@de.ibm.com + rth@twiddle.net + atar4qemu@gmail.com + ehabkost@redhat.com + sw@weilnetz.de + qemu-s390x@nongnu.org + qemu-arm@nongnu.org + david@gibson.dropbear.id.au + qemu-riscv@nongnu.org + cohuck@redhat.com + claudio.fontana@huawei.com + alex.williamson@redhat.com + qemu-ppc@nongnu.org + amarkovic@wavecomp.com + pbonzini@redhat.com + " aurelien@aurel32.net\0" + "\00:1\0" "b\0" "Preparation for splitting MO_8 out from TCGMemOp into new accelerator\n" "independent MemOp.\n" @@ -1546,1541 +1546,5 @@ " : dup_const(VECE, C)) \\\n" "--\n" 1.8.3.1 - "\01:2\0" - "b\0" - "<html>\r\n" - "<head>\r\n" - "<meta http-equiv=\"Content-Type\" content=\"text/html; charset=iso-8859-1\">\r\n" - "<style type=\"text/css\" style=\"display:none\"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style>\r\n" - "</head>\r\n" - "<body dir=\"ltr\" style=\"font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;\">\r\n" - "<p></p>\r\n" - "<div><span style=\"font-size: 12pt;\">Preparation for splitting MO_8 out from TCGMemOp into new accelerator</span><br>\r\n" - "</div>\r\n" - "<div>independent MemOp.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>As MO_8 will be a value of MemOp, existing TCGMemOp comparisons and</div>\r\n" - "<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div>\r\n" - "<div>---</div>\r\n" - "<div> target/arm/sve_helper.c | 4 +-</div>\r\n" - "<div> target/arm/translate-a64.c | 14 +++----</div>\r\n" - "<div> target/arm/translate-sve.c | 4 +-</div>\r\n" - "<div> target/arm/translate.c | 38 +++++++++----------</div>\r\n" - "<div> target/i386/translate.c | 72 +++++++++++++++++------------------</div>\r\n" - "<div> target/mips/translate.c | 4 +-</div>\r\n" - "<div> target/ppc/translate/vmx-impl.inc.c | 28 +++++++-------</div>\r\n" - "<div> target/s390x/translate.c | 2 +-</div>\r\n" - "<div> target/s390x/translate_vx.inc.c | 4 +-</div>\r\n" - "<div> target/s390x/vec.h | 4 +-</div>\r\n" - "<div> tcg/aarch64/tcg-target.inc.c | 16 ++++----</div>\r\n" - "<div> tcg/arm/tcg-target.inc.c | 6 +--</div>\r\n" - "<div> tcg/i386/tcg-target.inc.c | 54 +++++++++++++-------------</div>\r\n" - "<div> tcg/mips/tcg-target.inc.c | 4 +-</div>\r\n" - "<div> tcg/riscv/tcg-target.inc.c | 4 +-</div>\r\n" - "<div> tcg/sparc/tcg-target.inc.c | 2 +-</div>\r\n" - "<div> tcg/tcg-op-gvec.c | 76 ++++++++++++++++++-------------------</div>\r\n" - "<div> tcg/tcg-op-vec.c | 10 ++---</div>\r\n" - "<div> tcg/tcg-op.c | 6 +--</div>\r\n" - "<div> tcg/tcg.h | 2 +-</div>\r\n" - "<div> 20 files changed, 177 insertions(+), 177 deletions(-)</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div>\r\n" - "<div>index fc0c175..4c7e11f 100644</div>\r\n" - "<div>--- a/target/arm/sve_helper.c</div>\r\n" - "<div>+++ b/target/arm/sve_helper.c</div>\r\n" - "<div>@@ -1531,7 +1531,7 @@ void HELPER(sve_cpy_m_b)(void *vd, void *vn, void *vg,</div>\r\n" - "<div> uint64_t *d = vd, *n = vn;</div>\r\n" - "<div> uint8_t *pg = vg;</div>\r\n" - "<div> </div>\r\n" - "<div>- mm = dup_const(MO_8, mm);</div>\r\n" - "<div>+ mm = dup_const(MO_UB, mm);</div>\r\n" - "<div> for (i = 0; i < opr_sz; i += 1) {</div>\r\n" - "<div> uint64_t nn = n[i];</div>\r\n" - "<div> uint64_t pp = expand_pred_b(pg[H1(i)]);</div>\r\n" - "<div>@@ -1588,7 +1588,7 @@ void HELPER(sve_cpy_z_b)(void *vd, void *vg, uint64_t val, uint32_t desc)</div>\r\n" - "<div> uint64_t *d = vd;</div>\r\n" - "<div> uint8_t *pg = vg;</div>\r\n" - "<div> </div>\r\n" - "<div>- val = dup_const(MO_8, val);</div>\r\n" - "<div>+ val = dup_const(MO_UB, val);</div>\r\n" - "<div> for (i = 0; i < opr_sz; i += 1) {</div>\r\n" - "<div> d[i] = val & expand_pred_b(pg[H1(i)]);</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div>\r\n" - "<div>index d323147..f840b43 100644</div>\r\n" - "<div>--- a/target/arm/translate-a64.c</div>\r\n" - "<div>+++ b/target/arm/translate-a64.c</div>\r\n" - "<div>@@ -993,7 +993,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1002,7 +1002,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div> tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_8|MO_SIGN:</div>\r\n" - "<div>+ case MO_SB:</div>\r\n" - "<div> tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16|MO_SIGN:</div>\r\n" - "<div>@@ -1025,13 +1025,13 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div> tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_8|MO_SIGN:</div>\r\n" - "<div>+ case MO_SB:</div>\r\n" - "<div> tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16|MO_SIGN:</div>\r\n" - "<div>@@ -1052,7 +1052,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1074,7 +1074,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -12885,7 +12885,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> default: /* integer */</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div>\r\n" - "<div>index fa068b0..ec5fb11 100644</div>\r\n" - "<div>--- a/target/arm/translate-sve.c</div>\r\n" - "<div>+++ b/target/arm/translate-sve.c</div>\r\n" - "<div>@@ -1665,7 +1665,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div>\r\n" - "<div> desc = tcg_const_i32(simd_desc(vsz, vsz, 0));</div>\r\n" - "<div> </div>\r\n" - "<div> switch (esz) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> t32 = tcg_temp_new_i32();</div>\r\n" - "<div> tcg_gen_extrl_i64_i32(t32, val);</div>\r\n" - "<div> if (d) {</div>\r\n" - "<div>@@ -3308,7 +3308,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_sve_subri_b,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8,</div>\r\n" - "<div>+ .vece = MO_UB,</div>\r\n" - "<div> .scalar_first = true },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_sub16_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div>\r\n" - "<div>index 7853462..39266cf 100644</div>\r\n" - "<div>--- a/target/arm/translate.c</div>\r\n" - "<div>+++ b/target/arm/translate.c</div>\r\n" - "<div>@@ -1474,7 +1474,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div>\r\n" - "<div> long offset = neon_element_offset(reg, ele, size);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i32(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1493,7 +1493,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div>\r\n" - "<div> long offset = neon_element_offset(reg, ele, size);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -4262,7 +4262,7 @@ const GVecGen2i ssra_op[4] = {</div>\r\n" - "<div> .fniv = gen_ssra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_ssra,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = gen_ssra16_i64,</div>\r\n" - "<div> .fniv = gen_ssra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4320,7 +4320,7 @@ const GVecGen2i usra_op[4] = {</div>\r\n" - "<div> .fniv = gen_usra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_usra,</div>\r\n" - "<div>- .vece = MO_8, },</div>\r\n" - "<div>+ .vece = MO_UB, },</div>\r\n" - "<div> { .fni8 = gen_usra16_i64,</div>\r\n" - "<div> .fniv = gen_usra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4341,7 +4341,7 @@ const GVecGen2i usra_op[4] = {</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_8, 0xff >> shift);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UB, 0xff >> shift);</div>\r\n" - "<div> TCGv_i64 t = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_shri_i64(t, a, shift);</div>\r\n" - "<div>@@ -4400,7 +4400,7 @@ const GVecGen2i sri_op[4] = {</div>\r\n" - "<div> .fniv = gen_shr_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sri,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = gen_shr16_ins_i64,</div>\r\n" - "<div> .fniv = gen_shr_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4421,7 +4421,7 @@ const GVecGen2i sri_op[4] = {</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_8, 0xff << shift);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UB, 0xff << shift);</div>\r\n" - "<div> TCGv_i64 t = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_shli_i64(t, a, shift);</div>\r\n" - "<div>@@ -4478,7 +4478,7 @@ const GVecGen2i sli_op[4] = {</div>\r\n" - "<div> .fniv = gen_shl_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sli,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = gen_shl16_ins_i64,</div>\r\n" - "<div> .fniv = gen_shl_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4574,7 +4574,7 @@ const GVecGen3 mla_op[4] = {</div>\r\n" - "<div> .fniv = gen_mla_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mla,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni4 = gen_mla16_i32,</div>\r\n" - "<div> .fniv = gen_mla_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4598,7 +4598,7 @@ const GVecGen3 mls_op[4] = {</div>\r\n" - "<div> .fniv = gen_mls_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mls,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni4 = gen_mls16_i32,</div>\r\n" - "<div> .fniv = gen_mls_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4645,7 +4645,7 @@ const GVecGen3 cmtst_op[4] = {</div>\r\n" - "<div> { .fni4 = gen_helper_neon_tst_u8,</div>\r\n" - "<div> .fniv = gen_cmtst_vec,</div>\r\n" - "<div> .opt_opc = vecop_list_cmtst,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni4 = gen_helper_neon_tst_u16,</div>\r\n" - "<div> .fniv = gen_cmtst_vec,</div>\r\n" - "<div> .opt_opc = vecop_list_cmtst,</div>\r\n" - "<div>@@ -4681,7 +4681,7 @@ const GVecGen4 uqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqadd_b,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div> .opt_opc = vecop_list_uqadd,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = gen_uqadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_uqadd_h,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>@@ -4719,7 +4719,7 @@ const GVecGen4 sqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqadd_b,</div>\r\n" - "<div> .opt_opc = vecop_list_sqadd,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = gen_sqadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sqadd_h,</div>\r\n" - "<div> .opt_opc = vecop_list_sqadd,</div>\r\n" - "<div>@@ -4757,7 +4757,7 @@ const GVecGen4 uqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqsub_b,</div>\r\n" - "<div> .opt_opc = vecop_list_uqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = gen_uqsub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_uqsub_h,</div>\r\n" - "<div> .opt_opc = vecop_list_uqsub,</div>\r\n" - "<div>@@ -4795,7 +4795,7 @@ const GVecGen4 sqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqsub_b,</div>\r\n" - "<div> .opt_opc = vecop_list_sqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = gen_sqsub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sqsub_h,</div>\r\n" - "<div> .opt_opc = vecop_list_sqsub,</div>\r\n" - "<div>@@ -4972,15 +4972,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> vec_size, vec_size);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 5: /* VBSL */</div>\r\n" - "<div>- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,</div>\r\n" - "<div>+ tcg_gen_gvec_bitsel(MO_UB, rd_ofs, rd_ofs, rn_ofs, rm_ofs,</div>\r\n" - "<div> vec_size, vec_size);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 6: /* VBIT */</div>\r\n" - "<div>- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,</div>\r\n" - "<div>+ tcg_gen_gvec_bitsel(MO_UB, rd_ofs, rm_ofs, rn_ofs, rd_ofs,</div>\r\n" - "<div> vec_size, vec_size);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 7: /* VBIF */</div>\r\n" - "<div>- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,</div>\r\n" - "<div>+ tcg_gen_gvec_bitsel(MO_UB, rd_ofs, rm_ofs, rd_ofs, rn_ofs,</div>\r\n" - "<div> vec_size, vec_size);</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6873,7 +6873,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> return 1;</div>\r\n" - "<div> }</div>\r\n" - "<div> if (insn & (1 << 16)) {</div>\r\n" - "<div>- size = MO_8;</div>\r\n" - "<div>+ size = MO_UB;</div>\r\n" - "<div> element = (insn >> 17) & 7;</div>\r\n" - "<div> } else if (insn & (1 << 17)) {</div>\r\n" - "<div> size = MO_16;</div>\r\n" - "<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div>\r\n" - "<div>index 03150a8..0e45300 100644</div>\r\n" - "<div>--- a/target/i386/translate.c</div>\r\n" - "<div>+++ b/target/i386/translate.c</div>\r\n" - "<div>@@ -349,20 +349,20 @@ static inline TCGMemOp mo_64_32(TCGMemOp ot)</div>\r\n" - "<div> byte vs word opcodes. */</div>\r\n" - "<div> static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return b & 1 ? ot : MO_8;</div>\r\n" - "<div>+ return b & 1 ? ot : MO_UB;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select size 8 if lsb of B is clear, else OT capped at 32.</div>\r\n" - "<div> Used for decoding operand size of port opcodes. */</div>\r\n" - "<div> static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;</div>\r\n" - "<div>+ return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_UB;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch(ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> if (!byte_reg_is_xH(s, reg)) {</div>\r\n" - "<div> tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -390,7 +390,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div> static inline</div>\r\n" - "<div> void gen_op_mov_v_reg(DisasContext *s, TCGMemOp ot, TCGv t0, int reg)</div>\r\n" - "<div> {</div>\r\n" - "<div>- if (ot == MO_8 && byte_reg_is_xH(s, reg)) {</div>\r\n" - "<div>+ if (ot == MO_UB && byte_reg_is_xH(s, reg)) {</div>\r\n" - "<div> tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_mov_tl(t0, cpu_regs[reg]);</div>\r\n" - "<div>@@ -523,7 +523,7 @@ static inline void gen_op_movl_T0_Dshift(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> if (sign) {</div>\r\n" - "<div> tcg_gen_ext8s_tl(dst, src);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -580,7 +580,7 @@ void gen_op_jz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div>\r\n" - "<div> static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> gen_helper_inb(v, cpu_env, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -597,7 +597,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div>\r\n" - "<div> static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> gen_helper_outb(cpu_env, v, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -619,7 +619,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div>\r\n" - "<div> if (s->pe && (s->cpl > s->iopl || s->vm86)) {</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> gen_helper_check_iob(cpu_env, s->tmp2_i32);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1557,7 +1557,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div>\r\n" - "<div> tcg_gen_andi_tl(s->T1, s->T1, mask);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> /* Replicate the 8-bit input so that a 32-bit rotate works. */</div>\r\n" - "<div> tcg_gen_ext8u_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_muli_tl(s->T0, s->T0, 0x01010101);</div>\r\n" - "<div>@@ -1661,7 +1661,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> tcg_gen_rotli_tl(s->T0, s->T0, op2);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> mask = 7;</div>\r\n" - "<div> goto do_shifts;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1719,7 +1719,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> </div>\r\n" - "<div> if (is_right) {</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> gen_helper_rcrb(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1738,7 +1738,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> gen_helper_rclb(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -2184,7 +2184,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> uint32_t ret;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> ret = x86_ldub_code(env, s);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -3784,7 +3784,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> if ((b & 0xff) == 0xf0) {</div>\r\n" - "<div>- ot = MO_8;</div>\r\n" - "<div>+ ot = MO_UB;</div>\r\n" - "<div> } else if (s->dflag != MO_64) {</div>\r\n" - "<div> ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -4760,7 +4760,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> val = insn_get(env, s, ot);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x83:</div>\r\n" - "<div>- val = (int8_t)insn_get(env, s, MO_8);</div>\r\n" - "<div>+ val = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_movi_tl(s->T1, val);</div>\r\n" - "<div>@@ -4866,8 +4866,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 4: /* mul */</div>\r\n" - "<div> switch(ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UB, s->T1, R_EAX);</div>\r\n" - "<div> tcg_gen_ext8u_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_ext8u_tl(s->T1, s->T1);</div>\r\n" - "<div> /* XXX: use 32 bit mul which could be faster */</div>\r\n" - "<div>@@ -4915,8 +4915,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 5: /* imul */</div>\r\n" - "<div> switch(ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UB, s->T1, R_EAX);</div>\r\n" - "<div> tcg_gen_ext8s_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_ext8s_tl(s->T1, s->T1);</div>\r\n" - "<div> /* XXX: use 32 bit mul which could be faster */</div>\r\n" - "<div>@@ -4969,7 +4969,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 6: /* div */</div>\r\n" - "<div> switch(ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> gen_helper_divb_AL(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -4988,7 +4988,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 7: /* idiv */</div>\r\n" - "<div> switch(ot) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> gen_helper_idivb_AL(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -5157,7 +5157,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_8, s->T0, R_EAX);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UB, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext8s_tl(s->T0, s->T0);</div>\r\n" - "<div> gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -5205,7 +5205,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> val = insn_get(env, s, ot);</div>\r\n" - "<div> tcg_gen_movi_tl(s->T1, val);</div>\r\n" - "<div> } else if (b == 0x6b) {</div>\r\n" - "<div>- val = (int8_t)insn_get(env, s, MO_8);</div>\r\n" - "<div>+ val = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> tcg_gen_movi_tl(s->T1, val);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> gen_op_mov_v_reg(s, ot, s->T1, reg);</div>\r\n" - "<div>@@ -5419,7 +5419,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (b == 0x68)</div>\r\n" - "<div> val = insn_get(env, s, ot);</div>\r\n" - "<div> else</div>\r\n" - "<div>- val = (int8_t)insn_get(env, s, MO_8);</div>\r\n" - "<div>+ val = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> tcg_gen_movi_tl(s->T0, val);</div>\r\n" - "<div> gen_push_v(s, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -5573,7 +5573,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* d_ot is the size of destination */</div>\r\n" - "<div> d_ot = dflag;</div>\r\n" - "<div> /* ot is the size of source */</div>\r\n" - "<div>- ot = (b & 1) + MO_8;</div>\r\n" - "<div>+ ot = (b & 1) + MO_UB;</div>\r\n" - "<div> /* s_ot is the sign+size of source */</div>\r\n" - "<div> s_ot = b & 8 ? MO_SIGN | ot : ot;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -5661,13 +5661,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tcg_gen_add_tl(s->A0, s->A0, s->T0);</div>\r\n" - "<div> gen_extu(s->aflag, s->A0);</div>\r\n" - "<div> gen_add_A0_ds_seg(s);</div>\r\n" - "<div>- gen_op_ld_v(s, MO_8, s->T0, s->A0);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UB, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UB, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0xb0 ... 0xb7: /* mov R, Ib */</div>\r\n" - "<div>- val = insn_get(env, s, MO_8);</div>\r\n" - "<div>+ val = insn_get(env, s, MO_UB);</div>\r\n" - "<div> tcg_gen_movi_tl(s->T0, val);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_8, (b & 7) | REX_B(s), s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UB, (b & 7) | REX_B(s), s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0xb8 ... 0xbf: /* mov R, Iv */</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>@@ -6637,7 +6637,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> }</div>\r\n" - "<div> goto do_ljmp;</div>\r\n" - "<div> case 0xeb: /* jmp Jb */</div>\r\n" - "<div>- tval = (int8_t)insn_get(env, s, MO_8);</div>\r\n" - "<div>+ tval = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> tval += s->pc - s->cs_base;</div>\r\n" - "<div> if (dflag == MO_16) {</div>\r\n" - "<div> tval &= 0xffff;</div>\r\n" - "<div>@@ -6645,7 +6645,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_jmp(s, tval);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x70 ... 0x7f: /* jcc Jb */</div>\r\n" - "<div>- tval = (int8_t)insn_get(env, s, MO_8);</div>\r\n" - "<div>+ tval = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> goto do_jcc;</div>\r\n" - "<div> case 0x180 ... 0x18f: /* jcc Jv */</div>\r\n" - "<div> if (dflag != MO_16) {</div>\r\n" - "<div>@@ -6666,7 +6666,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x190 ... 0x19f: /* setcc Gv */</div>\r\n" - "<div> modrm = x86_ldub_code(env, s);</div>\r\n" - "<div> gen_setcc1(s, b, s->T0);</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UB, OR_TMP0, 1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x140 ... 0x14f: /* cmov Gv, Ev */</div>\r\n" - "<div> if (!(s->cpuid_features & CPUID_CMOV)) {</div>\r\n" - "<div>@@ -6751,7 +6751,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x9e: /* sahf */</div>\r\n" - "<div> if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_8, s->T0, R_AH);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UB, s->T0, R_AH);</div>\r\n" - "<div> gen_compute_eflags(s);</div>\r\n" - "<div> tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C);</div>\r\n" - "<div>@@ -6763,7 +6763,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_compute_eflags(s);</div>\r\n" - "<div> /* Note: gen_compute_eflags() only gives the condition codes */</div>\r\n" - "<div> tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_8, R_AH, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UB, R_AH, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0xf5: /* cmc */</div>\r\n" - "<div> gen_compute_eflags(s);</div>\r\n" - "<div>@@ -7137,7 +7137,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> gen_compute_eflags_c(s, s->T0);</div>\r\n" - "<div> tcg_gen_neg_tl(s->T0, s->T0);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UB, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0xe0: /* loopnz */</div>\r\n" - "<div> case 0xe1: /* loopz */</div>\r\n" - "<div>@@ -7146,7 +7146,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGLabel *l1, *l2, *l3;</div>\r\n" - "<div> </div>\r\n" - "<div>- tval = (int8_t)insn_get(env, s, MO_8);</div>\r\n" - "<div>+ tval = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> next_eip = s->pc - s->cs_base;</div>\r\n" - "<div> tval += next_eip;</div>\r\n" - "<div> if (dflag == MO_16) {</div>\r\n" - "<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div>\r\n" - "<div>index 3575eff..20a9777 100644</div>\r\n" - "<div>--- a/target/mips/translate.c</div>\r\n" - "<div>+++ b/target/mips/translate.c</div>\r\n" - "<div>@@ -3684,7 +3684,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,</div>\r\n" - "<div> mem_idx = MIPS_HFLAG_UM;</div>\r\n" - "<div> /* fall through */</div>\r\n" - "<div> case OPC_SB:</div>\r\n" - "<div>- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8);</div>\r\n" - "<div>+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_UB);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case OPC_SWLE:</div>\r\n" - "<div> mem_idx = MIPS_HFLAG_UM;</div>\r\n" - "<div>@@ -20193,7 +20193,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)</div>\r\n" - "<div> check_nms(ctx);</div>\r\n" - "<div> gen_load_gpr(t1, rd);</div>\r\n" - "<div> tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,</div>\r\n" - "<div>- MO_8);</div>\r\n" - "<div>+ MO_UB);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case NM_SHX:</div>\r\n" - "<div> /*case NM_SHXS:*/</div>\r\n" - "<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>index 663275b..4130dd1 100644</div>\r\n" - "<div>--- a/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>@@ -403,7 +403,7 @@ static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div> tcg_temp_free_ptr(rb); \\</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);</div>\r\n" - "<div>+GEN_VXFORM_V(vaddubm, MO_UB, tcg_gen_gvec_add, 0, 0);</div>\r\n" - "<div> GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \\</div>\r\n" - "<div> vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div>\r\n" - "<div> GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);</div>\r\n" - "<div>@@ -411,23 +411,23 @@ GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);</div>\r\n" - "<div> GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div>\r\n" - "<div>-GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);</div>\r\n" - "<div>+GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div>\r\n" - "<div> GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);</div>\r\n" - "<div> GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);</div>\r\n" - "<div> GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div>\r\n" - "<div>-GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);</div>\r\n" - "<div>+GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div>\r\n" - "<div> GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);</div>\r\n" - "<div> GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);</div>\r\n" - "<div> GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div>\r\n" - "<div>-GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);</div>\r\n" - "<div>+GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div>\r\n" - "<div> GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);</div>\r\n" - "<div> GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div>\r\n" - "<div>@@ -530,18 +530,18 @@ GEN_VXFORM(vmuleuw, 4, 10);</div>\r\n" - "<div> GEN_VXFORM(vmulesb, 4, 12);</div>\r\n" - "<div> GEN_VXFORM(vmulesh, 4, 13);</div>\r\n" - "<div> GEN_VXFORM(vmulesw, 4, 14);</div>\r\n" - "<div>-GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);</div>\r\n" - "<div>+GEN_VXFORM_V(vslb, MO_UB, tcg_gen_gvec_shlv, 2, 4);</div>\r\n" - "<div> GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);</div>\r\n" - "<div> GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);</div>\r\n" - "<div> GEN_VXFORM(vrlwnm, 2, 6);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div>\r\n" - "<div>-GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);</div>\r\n" - "<div>+GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div>\r\n" - "<div> GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);</div>\r\n" - "<div> GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);</div>\r\n" - "<div> GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div>\r\n" - "<div>-GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);</div>\r\n" - "<div>+GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div>\r\n" - "<div> GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);</div>\r\n" - "<div> GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div>\r\n" - "<div>@@ -589,20 +589,20 @@ static void glue(gen_, NAME)(DisasContext *ctx) \\</div>\r\n" - "<div> 16, 16, &g); \\</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vaddubs, MO_UB, add, usadd, 0, 8);</div>\r\n" - "<div> GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \\</div>\r\n" - "<div> vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div>\r\n" - "<div> GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vmul10euq, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vaddsbs, MO_UB, add, ssadd, 0, 12);</div>\r\n" - "<div> GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);</div>\r\n" - "<div> GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vsububs, MO_UB, sub, ussub, 0, 24);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vsubsbs, MO_UB, sub, sssub, 0, 28);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);</div>\r\n" - "<div> GEN_VXFORM(vadduqm, 0, 4);</div>\r\n" - "<div>@@ -912,7 +912,7 @@ static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div> tcg_temp_free_ptr(rd); \\</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);</div>\r\n" - "<div>+GEN_VXFORM_VSPLT(vspltb, MO_UB, 6, 8);</div>\r\n" - "<div> GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);</div>\r\n" - "<div> GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);</div>\r\n" - "<div> GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);</div>\r\n" - "<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div>\r\n" - "<div>index ac0d8b6..415747f 100644</div>\r\n" - "<div>--- a/target/s390x/translate.c</div>\r\n" - "<div>+++ b/target/s390x/translate.c</div>\r\n" - "<div>@@ -154,7 +154,7 @@ static inline int vec_full_reg_offset(uint8_t reg)</div>\r\n" - "<div> </div>\r\n" - "<div> static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div>\r\n" - "<div> {</div>\r\n" - "<div>- /* Convert element size (es) - e.g. MO_8 - to bytes */</div>\r\n" - "<div>+ /* Convert element size (es) - e.g. MO_UB - to bytes */</div>\r\n" - "<div> const uint8_t bytes = 1 << es;</div>\r\n" - "<div> int offs = enr * bytes;</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>index 41d5cf8..bb424c8 100644</div>\r\n" - "<div>--- a/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>+++ b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>@@ -30,7 +30,7 @@</div>\r\n" - "<div> * Sizes:</div>\r\n" - "<div> * On s390x, the operand size (oprsz) and the maximum size (maxsz) are</div>\r\n" - "<div> * always 16 (128 bit). What gvec code calls "vece", s390x calls "es",</div>\r\n" - "<div>- * a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only</div>\r\n" - "<div>+ * a.k.a. "element size". These values nicely map to MO_UB ... MO_64. Only</div>\r\n" - "<div> * 128 bit element size has to be treated in a special way (MO_64 + 1).</div>\r\n" - "<div> * We will use ES_* instead of MO_* for this reason in this file.</div>\r\n" - "<div> *</div>\r\n" - "<div>@@ -46,7 +46,7 @@</div>\r\n" - "<div> #define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es))</div>\r\n" - "<div> #define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)</div>\r\n" - "<div> </div>\r\n" - "<div>-#define ES_8 MO_8</div>\r\n" - "<div>+#define ES_8 MO_UB</div>\r\n" - "<div> #define ES_16 MO_16</div>\r\n" - "<div> #define ES_32 MO_32</div>\r\n" - "<div> #define ES_64 MO_64</div>\r\n" - "<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div>\r\n" - "<div>index a6e3618..b813054 100644</div>\r\n" - "<div>--- a/target/s390x/vec.h</div>\r\n" - "<div>+++ b/target/s390x/vec.h</div>\r\n" - "<div>@@ -76,7 +76,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div>\r\n" - "<div> uint8_t es)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (es) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> return s390_vec_read_element8(v, enr);</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div> return s390_vec_read_element16(v, enr);</div>\r\n" - "<div>@@ -121,7 +121,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div>\r\n" - "<div> uint8_t es, uint64_t data)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (es) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> s390_vec_write_element8(v, enr, data);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>index 0713448..e4e0845 100644</div>\r\n" - "<div>--- a/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>@@ -429,20 +429,20 @@ typedef enum {</div>\r\n" - "<div> </div>\r\n" - "<div> /* Load/store register. Described here as 3.3.12, but the helper</div>\r\n" - "<div> that emits them can transform to 3.3.10 or 3.3.13. */</div>\r\n" - "<div>- I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,</div>\r\n" - "<div>+ I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,</div>\r\n" - "<div> I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,</div>\r\n" - "<div> I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div>- I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,</div>\r\n" - "<div>+ I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,</div>\r\n" - "<div> I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,</div>\r\n" - "<div> I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div>- I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,</div>\r\n" - "<div>+ I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div>- I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,</div>\r\n" - "<div>+ I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,</div>\r\n" - "<div> I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -862,7 +862,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div>\r\n" - "<div> int cmode, imm8, i;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Test all bytes equal first. */</div>\r\n" - "<div>- if (v64 == dup_const(MO_8, v64)) {</div>\r\n" - "<div>+ if (v64 == dup_const(MO_UB, v64)) {</div>\r\n" - "<div> imm8 = (uint8_t)v64;</div>\r\n" - "<div> tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -1772,7 +1772,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div>\r\n" - "<div> const TCGMemOp bswap = memop & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (memop & MO_SIZE) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -2186,7 +2186,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_ext8s_i64:</div>\r\n" - "<div> case INDEX_op_ext8s_i32:</div>\r\n" - "<div>- tcg_out_sxt(s, ext, MO_8, a0, a1);</div>\r\n" - "<div>+ tcg_out_sxt(s, ext, MO_UB, a0, a1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext16s_i64:</div>\r\n" - "<div> case INDEX_op_ext16s_i32:</div>\r\n" - "<div>@@ -2198,7 +2198,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext8u_i64:</div>\r\n" - "<div> case INDEX_op_ext8u_i32:</div>\r\n" - "<div>- tcg_out_uxt(s, MO_8, a0, a1);</div>\r\n" - "<div>+ tcg_out_uxt(s, MO_UB, a0, a1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext16u_i64:</div>\r\n" - "<div> case INDEX_op_ext16u_i32:</div>\r\n" - "<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>index ece88dc..542ffa8 100644</div>\r\n" - "<div>--- a/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>@@ -1429,7 +1429,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> datalo = lb->datalo_reg;</div>\r\n" - "<div> datahi = lb->datahi_reg;</div>\r\n" - "<div> switch (opc & MO_SIZE) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> argreg = tcg_out_arg_reg8(s, argreg, datalo);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1621,7 +1621,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div>\r\n" - "<div> TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & MO_SIZE) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_st8_r(s, cond, datalo, addrlo, addend);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1666,7 +1666,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div> TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & MO_SIZE) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>index 6ddeebf..0d68ba4 100644</div>\r\n" - "<div>--- a/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>@@ -888,7 +888,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> /* ??? With zero in a register, use PSHUFB. */</div>\r\n" - "<div> tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a);</div>\r\n" - "<div> a = r;</div>\r\n" - "<div>@@ -932,7 +932,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> tcg_out8(s, 0); /* imm8 */</div>\r\n" - "<div> tcg_out_dup_vec(s, type, vece, r, r);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset);</div>\r\n" - "<div> tcg_out8(s, 0); /* imm8 */</div>\r\n" - "<div> tcg_out_dup_vec(s, type, vece, r, r);</div>\r\n" - "<div>@@ -2154,7 +2154,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> switch (memop & MO_SIZE) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> /* In 32-bit mode, 8-bit stores can only happen from [abcd]x.</div>\r\n" - "<div> Use the scratch register if necessary. */</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) {</div>\r\n" - "<div>@@ -2901,7 +2901,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> tcg_debug_assert(vece != MO_64);</div>\r\n" - "<div> sub = 4;</div>\r\n" - "<div> gen_shift:</div>\r\n" - "<div>- tcg_debug_assert(vece != MO_8);</div>\r\n" - "<div>+ tcg_debug_assert(vece != MO_UB);</div>\r\n" - "<div> insn = shift_imm_insn[vece];</div>\r\n" - "<div> if (type == TCG_TYPE_V256) {</div>\r\n" - "<div> insn |= P_VEXL;</div>\r\n" - "<div>@@ -3273,12 +3273,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_shli_vec:</div>\r\n" - "<div> case INDEX_op_shri_vec:</div>\r\n" - "<div>- /* We must expand the operation for MO_8. */</div>\r\n" - "<div>- return vece == MO_8 ? -1 : 1;</div>\r\n" - "<div>+ /* We must expand the operation for MO_UB. */</div>\r\n" - "<div>+ return vece == MO_UB ? -1 : 1;</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_sari_vec:</div>\r\n" - "<div>- /* We must expand the operation for MO_8. */</div>\r\n" - "<div>- if (vece == MO_8) {</div>\r\n" - "<div>+ /* We must expand the operation for MO_UB. */</div>\r\n" - "<div>+ if (vece == MO_UB) {</div>\r\n" - "<div> return -1;</div>\r\n" - "<div> }</div>\r\n" - "<div> /* We can emulate this for MO_64, but it does not pay off</div>\r\n" - "<div>@@ -3301,8 +3301,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> return have_avx2 && vece == MO_32;</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_mul_vec:</div>\r\n" - "<div>- if (vece == MO_8) {</div>\r\n" - "<div>- /* We can expand the operation for MO_8. */</div>\r\n" - "<div>+ if (vece == MO_UB) {</div>\r\n" - "<div>+ /* We can expand the operation for MO_UB. */</div>\r\n" - "<div> return -1;</div>\r\n" - "<div> }</div>\r\n" - "<div> if (vece == MO_64) {</div>\r\n" - "<div>@@ -3332,7 +3332,7 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_vec t1, t2;</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece == MO_8);</div>\r\n" - "<div>+ tcg_debug_assert(vece == MO_UB);</div>\r\n" - "<div> </div>\r\n" - "<div> t1 = tcg_temp_new_vec(type);</div>\r\n" - "<div> t2 = tcg_temp_new_vec(type);</div>\r\n" - "<div>@@ -3346,9 +3346,9 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div>\r\n" - "<div> (3) Step 2 leaves high half zero such that PACKUSWB</div>\r\n" - "<div> (pack with unsigned saturation) does not modify</div>\r\n" - "<div> the quantity. */</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div>\r\n" - "<div> </div>\r\n" - "<div> if (shr) {</div>\r\n" - "<div>@@ -3361,7 +3361,7 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div>\r\n" - "<div> tcg_gen_shri_vec(MO_16, t2, t2, 8);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div> tcg_temp_free_vec(t2);</div>\r\n" - "<div>@@ -3373,17 +3373,17 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div>\r\n" - "<div> TCGv_vec t1, t2;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> /* Unpack to W, shift, and repack, as in expand_vec_shi. */</div>\r\n" - "<div> t1 = tcg_temp_new_vec(type);</div>\r\n" - "<div> t2 = tcg_temp_new_vec(type);</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div>\r\n" - "<div> tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);</div>\r\n" - "<div> tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_packss_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div> tcg_temp_free_vec(t2);</div>\r\n" - "<div>@@ -3425,7 +3425,7 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_vec t1, t2, t3, t4;</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece == MO_8);</div>\r\n" - "<div>+ tcg_debug_assert(vece == MO_UB);</div>\r\n" - "<div> </div>\r\n" - "<div> /*</div>\r\n" - "<div> * Unpack v1 bytes to words, 0 | x.</div>\r\n" - "<div>@@ -3442,13 +3442,13 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div>\r\n" - "<div> t1 = tcg_temp_new_vec(TCG_TYPE_V128);</div>\r\n" - "<div> t2 = tcg_temp_new_vec(TCG_TYPE_V128);</div>\r\n" - "<div> tcg_gen_dup16i_vec(t2, 0);</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));</div>\r\n" - "<div> tcg_gen_mul_vec(MO_16, t1, t1, t2);</div>\r\n" - "<div> tcg_gen_shri_vec(MO_16, t1, t1, 8);</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1));</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div> tcg_temp_free_vec(t2);</div>\r\n" - "<div>@@ -3461,19 +3461,19 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div>\r\n" - "<div> t3 = tcg_temp_new_vec(type);</div>\r\n" - "<div> t4 = tcg_temp_new_vec(type);</div>\r\n" - "<div> tcg_gen_dup16i_vec(t4, 0);</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));</div>\r\n" - "<div> tcg_gen_mul_vec(MO_16, t1, t1, t2);</div>\r\n" - "<div> tcg_gen_mul_vec(MO_16, t3, t3, t4);</div>\r\n" - "<div> tcg_gen_shri_vec(MO_16, t1, t1, 8);</div>\r\n" - "<div> tcg_gen_shri_vec(MO_16, t3, t3, 8);</div>\r\n" - "<div>- vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3));</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div> tcg_temp_free_vec(t2);</div>\r\n" - "<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>index 41bff32..c6d13ea 100644</div>\r\n" - "<div>--- a/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>@@ -1380,7 +1380,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);</div>\r\n" - "<div> }</div>\r\n" - "<div> switch (s_bits) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1566,7 +1566,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & (MO_SIZE | MO_BSWAP)) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SB, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>index 3e76bf5..9c60c0f 100644</div>\r\n" - "<div>--- a/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>@@ -1101,7 +1101,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);</div>\r\n" - "<div> switch (s_bits) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_ext8u(s, a2, a2);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1216,7 +1216,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> g_assert(!bswap);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & (MO_SSIZE)) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_opc_store(s, OPC_SB, base, lo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>index 10b1cea..479ee2e 100644</div>\r\n" - "<div>--- a/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>@@ -882,7 +882,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div>\r\n" - "<div> * required by the MO_* value op; do nothing for 64 bit.</div>\r\n" - "<div> */</div>\r\n" - "<div> switch (op & MO_SIZE) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_out_arithi(s, r, r, 0xff, ARITH_AND);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>index 17679b6..9658c36 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-gvec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>@@ -306,7 +306,7 @@ static void expand_clr(uint32_t dofs, uint32_t maxsz);</div>\r\n" - "<div> uint64_t (dup_const)(unsigned vece, uint64_t c)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> return 0x0101010101010101ull * (uint8_t)c;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div> return 0x0001000100010001ull * (uint16_t)c;</div>\r\n" - "<div>@@ -323,7 +323,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div>\r\n" - "<div> static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_ext8u_i32(out, in);</div>\r\n" - "<div> tcg_gen_muli_i32(out, out, 0x01010101);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -341,7 +341,7 @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div>\r\n" - "<div> static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_ext8u_i64(out, in);</div>\r\n" - "<div> tcg_gen_muli_i64(out, out, 0x0101010101010101ull);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -556,7 +556,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> t_32 = tcg_temp_new_i32();</div>\r\n" - "<div> if (in_64) {</div>\r\n" - "<div> tcg_gen_extrl_i64_i32(t_32, in_64);</div>\r\n" - "<div>- } else if (vece == MO_8) {</div>\r\n" - "<div>+ } else if (vece == MO_UB) {</div>\r\n" - "<div> tcg_gen_movi_i32(t_32, in_c & 0xff);</div>\r\n" - "<div> } else if (vece == MO_16) {</div>\r\n" - "<div> tcg_gen_movi_i32(t_32, in_c & 0xffff);</div>\r\n" - "<div>@@ -581,7 +581,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> /* Likewise, but with zero. */</div>\r\n" - "<div> static void expand_clr(uint32_t dofs, uint32_t maxsz)</div>\r\n" - "<div> {</div>\r\n" - "<div>- do_dup(MO_8, dofs, maxsz, maxsz, NULL, NULL, 0);</div>\r\n" - "<div>+ do_dup(MO_UB, dofs, maxsz, maxsz, NULL, NULL, 0);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Expand OPSZ bytes worth of two-operand operations using i32 elements. */</div>\r\n" - "<div>@@ -1456,7 +1456,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> } else if (vece <= MO_32) {</div>\r\n" - "<div> TCGv_i32 in = tcg_temp_new_i32();</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> tcg_gen_ld8u_i32(in, cpu_env, aofs);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -1533,7 +1533,7 @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> uint32_t maxsz, uint8_t x)</div>\r\n" - "<div> {</div>\r\n" - "<div> check_size_align(oprsz, maxsz, dofs);</div>\r\n" - "<div>- do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div>+ do_dup(MO_UB, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div>@@ -1572,7 +1572,7 @@ static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));</div>\r\n" - "<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UB, 0x80));</div>\r\n" - "<div> gen_addv_mask(d, a, b, m);</div>\r\n" - "<div> tcg_temp_free_i64(m);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -1608,7 +1608,7 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_add8,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_add16_i64,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_add16,</div>\r\n" - "<div>@@ -1639,7 +1639,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_adds8,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_add16_i64,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_adds16,</div>\r\n" - "<div>@@ -1680,7 +1680,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_subs8,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_sub16_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_subs16,</div>\r\n" - "<div>@@ -1725,7 +1725,7 @@ static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));</div>\r\n" - "<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UB, 0x80));</div>\r\n" - "<div> gen_subv_mask(d, a, b, m);</div>\r\n" - "<div> tcg_temp_free_i64(m);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -1759,7 +1759,7 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sub8,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_sub16_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sub16,</div>\r\n" - "<div>@@ -1791,7 +1791,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_mul8,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_mul16,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>@@ -1820,7 +1820,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_muls8,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_muls16,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>@@ -1858,7 +1858,7 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_ssadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ssadd8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_ssadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ssadd16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1884,7 +1884,7 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_sssub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sssub8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_sssub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sssub16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1926,7 +1926,7 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_usadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_usadd8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_usadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_usadd16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1970,7 +1970,7 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_ussub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ussub8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_ussub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ussub16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1998,7 +1998,7 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_smin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smin8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_smin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smin16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -2026,7 +2026,7 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_umin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umin8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_umin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umin16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -2054,7 +2054,7 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_smax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smax8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_smax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smax16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -2082,7 +2082,7 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_umax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umax8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_umax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umax16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -2120,7 +2120,7 @@ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));</div>\r\n" - "<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UB, 0x80));</div>\r\n" - "<div> gen_negv_mask(d, b, m);</div>\r\n" - "<div> tcg_temp_free_i64(m);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2155,7 +2155,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_neg_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_neg8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_neg16_i64,</div>\r\n" - "<div> .fniv = tcg_gen_neg_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_neg16,</div>\r\n" - "<div>@@ -2201,7 +2201,7 @@ static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece)</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_absv_mask(d, b, MO_8);</div>\r\n" - "<div>+ gen_absv_mask(d, b, MO_UB);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b)</div>\r\n" - "<div>@@ -2218,7 +2218,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_abs_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_abs8,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_abs16_i64,</div>\r\n" - "<div> .fniv = tcg_gen_abs_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_abs16,</div>\r\n" - "<div>@@ -2454,7 +2454,7 @@ void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_8, 0xff << c);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UB, 0xff << c);</div>\r\n" - "<div> tcg_gen_shli_i64(d, a, c);</div>\r\n" - "<div> tcg_gen_andi_i64(d, d, mask);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2475,7 +2475,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shli_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl8i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_shl16i_i64,</div>\r\n" - "<div> .fniv = tcg_gen_shli_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl16i,</div>\r\n" - "<div>@@ -2505,7 +2505,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_8, 0xff >> c);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UB, 0xff >> c);</div>\r\n" - "<div> tcg_gen_shri_i64(d, a, c);</div>\r\n" - "<div> tcg_gen_andi_i64(d, d, mask);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2526,7 +2526,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shri_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr8i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_shr16i_i64,</div>\r\n" - "<div> .fniv = tcg_gen_shri_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr16i,</div>\r\n" - "<div>@@ -2556,8 +2556,8 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t s_mask = dup_const(MO_8, 0x80 >> c);</div>\r\n" - "<div>- uint64_t c_mask = dup_const(MO_8, 0xff >> c);</div>\r\n" - "<div>+ uint64_t s_mask = dup_const(MO_UB, 0x80 >> c);</div>\r\n" - "<div>+ uint64_t c_mask = dup_const(MO_UB, 0xff >> c);</div>\r\n" - "<div> TCGv_i64 s = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_shri_i64(d, a, c);</div>\r\n" - "<div>@@ -2591,7 +2591,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sari_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar8i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fni8 = tcg_gen_vec_sar16i_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sari_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar16i,</div>\r\n" - "<div>@@ -2880,7 +2880,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_shlv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl8v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_shlv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl16v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -2943,7 +2943,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_shrv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr8v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_shrv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr16v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -3006,7 +3006,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_sarv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar8v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_8 },</div>\r\n" - "<div>+ .vece = MO_UB },</div>\r\n" - "<div> { .fniv = tcg_gen_sarv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar16v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -3129,7 +3129,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div>\r\n" - "<div> check_overlap_3(dofs, aofs, bofs, maxsz);</div>\r\n" - "<div> </div>\r\n" - "<div> if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {</div>\r\n" - "<div>- do_dup(MO_8, dofs, oprsz, maxsz,</div>\r\n" - "<div>+ do_dup(MO_UB, dofs, oprsz, maxsz,</div>\r\n" - "<div> NULL, NULL, -(cond == TCG_COND_ALWAYS));</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div>\r\n" - "<div>index 6714991..d7ffc9e 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-vec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-vec.c</div>\r\n" - "<div>@@ -275,7 +275,7 @@ void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)</div>\r\n" - "<div> {</div>\r\n" - "<div>- do_dupi_vec(r, MO_REG, dup_const(MO_8, a));</div>\r\n" - "<div>+ do_dupi_vec(r, MO_REG, dup_const(MO_UB, a));</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)</div>\r\n" - "<div>@@ -752,13 +752,13 @@ void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,</div>\r\n" - "<div> tcg_debug_assert(ct->base_type >= type);</div>\r\n" - "<div> </div>\r\n" - "<div> if (TCG_TARGET_HAS_bitsel_vec) {</div>\r\n" - "<div>- vec_gen_4(INDEX_op_bitsel_vec, type, MO_8,</div>\r\n" - "<div>+ vec_gen_4(INDEX_op_bitsel_vec, type, MO_UB,</div>\r\n" - "<div> temp_arg(rt), temp_arg(at), temp_arg(bt), temp_arg(ct));</div>\r\n" - "<div> } else {</div>\r\n" - "<div> TCGv_vec t = tcg_temp_new_vec(type);</div>\r\n" - "<div>- tcg_gen_and_vec(MO_8, t, a, b);</div>\r\n" - "<div>- tcg_gen_andc_vec(MO_8, r, c, a);</div>\r\n" - "<div>- tcg_gen_or_vec(MO_8, r, r, t);</div>\r\n" - "<div>+ tcg_gen_and_vec(MO_UB, t, a, b);</div>\r\n" - "<div>+ tcg_gen_andc_vec(MO_UB, r, c, a);</div>\r\n" - "<div>+ tcg_gen_or_vec(MO_UB, r, r, t);</div>\r\n" - "<div> tcg_temp_free_vec(t);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div>\r\n" - "<div>index 587d092..61eda33 100644</div>\r\n" - "<div>--- a/tcg/tcg-op.c</div>\r\n" - "<div>+++ b/tcg/tcg-op.c</div>\r\n" - "<div>@@ -2720,7 +2720,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div>\r\n" - "<div> (void)get_alignment_bits(op);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (op & MO_SIZE) {</div>\r\n" - "<div>- case MO_8:</div>\r\n" - "<div>+ case MO_UB:</div>\r\n" - "<div> op &= ~MO_BSWAP;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div>@@ -3024,7 +3024,7 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64);</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> static void * const table_cmpxchg[16] = {</div>\r\n" - "<div>- [MO_8] = gen_helper_atomic_cmpxchgb,</div>\r\n" - "<div>+ [MO_UB] = gen_helper_atomic_cmpxchgb,</div>\r\n" - "<div> [MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div>\r\n" - "<div> [MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div>\r\n" - "<div> [MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div>\r\n" - "<div>@@ -3248,7 +3248,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div>\r\n" - "<div> </div>\r\n" - "<div> #define GEN_ATOMIC_HELPER(NAME, OP, NEW) \\</div>\r\n" - "<div> static void * const table_##NAME[16] = { \\</div>\r\n" - "<div>- [MO_8] = gen_helper_atomic_##NAME##b, \\</div>\r\n" - "<div>+ [MO_UB] = gen_helper_atomic_##NAME##b, \\</div>\r\n" - "<div> [MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \\</div>\r\n" - "<div> [MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \\</div>\r\n" - "<div> [MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \\</div>\r\n" - "<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div>\r\n" - "<div>index b411e17..5636d6b 100644</div>\r\n" - "<div>--- a/tcg/tcg.h</div>\r\n" - "<div>+++ b/tcg/tcg.h</div>\r\n" - "<div>@@ -1302,7 +1302,7 @@ uint64_t dup_const(unsigned vece, uint64_t c);</div>\r\n" - "<div> </div>\r\n" - "<div> #define dup_const(VECE, C) \\</div>\r\n" - "<div> (__builtin_constant_p(VECE) \\</div>\r\n" - "<div>- ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \\</div>\r\n" - "<div>+ ? ((VECE) == MO_UB ? 0x0101010101010101ull * (uint8_t)(C) \\</div>\r\n" - "<div> : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \\</div>\r\n" - "<div> : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \\</div>\r\n" - "<div> : dup_const(VECE, C)) \\</div>\r\n" - "<div>-- </div>\r\n" - "<div>1.8.3.1</div>\r\n" - "<div><br>\r\n" - "<br>\r\n" - "</div>\r\n" - "<p><br>\r\n" - "</p>\r\n" - "</body>\r\n" - "</html>\r\n" -e8bb08d5cac4bde7f4def4372666aa53e1b3650fa7ed1db5576f6fc9628af804 +c264390e796265504f5bf08a1cd37759eca074602e1ab0ab0a28bad03c92ea39
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