diff for duplicates of <1563810016433.48708@bt.com> diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index b20f4fa..0000000 --- a/a/2.bin +++ /dev/null @@ -1,2465 +0,0 @@ -<html> -<head> -<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> -<style type="text/css" style="display:none"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style> -</head> -<body dir="ltr" style="font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;"> -<div><span style="font-size: 12pt;">Preparation for splitting MO_16 out from TCGMemOp into new accelerator</span></div> -<div>independent MemOp.</div> -<div><br> -</div> -<div>As MO_16 will be a value of MemOp, existing TCGMemOp comparisons and</div> -<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div> -<div><br> -</div> -<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div> -<div>---</div> -<div> target/arm/sve_helper.c | 4 +-</div> -<div> target/arm/translate-a64.c | 90 ++++++++--------</div> -<div> target/arm/translate-sve.c | 40 ++++----</div> -<div> target/arm/translate-vfp.inc.c | 2 +-</div> -<div> target/arm/translate.c | 32 +++---</div> -<div> target/i386/translate.c | 200 ++++++++++++++++++------------------</div> -<div> target/mips/translate.c | 2 +-</div> -<div> target/ppc/translate/vmx-impl.inc.c | 28 ++---</div> -<div> target/s390x/translate_vx.inc.c | 2 +-</div> -<div> target/s390x/vec.h | 4 +-</div> -<div> tcg/aarch64/tcg-target.inc.c | 20 ++--</div> -<div> tcg/arm/tcg-target.inc.c | 6 +-</div> -<div> tcg/i386/tcg-target.inc.c | 48 ++++-----</div> -<div> tcg/mips/tcg-target.inc.c | 6 +-</div> -<div> tcg/riscv/tcg-target.inc.c | 4 +-</div> -<div> tcg/sparc/tcg-target.inc.c | 2 +-</div> -<div> tcg/tcg-op-gvec.c | 72 ++++++-------</div> -<div> tcg/tcg-op-vec.c | 2 +-</div> -<div> tcg/tcg-op.c | 18 ++--</div> -<div> tcg/tcg.h | 2 +-</div> -<div> 20 files changed, 292 insertions(+), 292 deletions(-)</div> -<div><br> -</div> -<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div> -<div>index 4c7e11f..f6bef3d 100644</div> -<div>--- a/target/arm/sve_helper.c</div> -<div>+++ b/target/arm/sve_helper.c</div> -<div>@@ -1546,7 +1546,7 @@ void HELPER(sve_cpy_m_h)(void *vd, void *vn, void *vg,</div> -<div> uint64_t *d = vd, *n = vn;</div> -<div> uint8_t *pg = vg;</div> -<div> </div> -<div>- mm = dup_const(MO_16, mm);</div> -<div>+ mm = dup_const(MO_UW, mm);</div> -<div> for (i = 0; i < opr_sz; i += 1) {</div> -<div> uint64_t nn = n[i];</div> -<div> uint64_t pp = expand_pred_h(pg[H1(i)]);</div> -<div>@@ -1600,7 +1600,7 @@ void HELPER(sve_cpy_z_h)(void *vd, void *vg, uint64_t val, uint32_t desc)</div> -<div> uint64_t *d = vd;</div> -<div> uint8_t *pg = vg;</div> -<div> </div> -<div>- val = dup_const(MO_16, val);</div> -<div>+ val = dup_const(MO_UW, val);</div> -<div> for (i = 0; i < opr_sz; i += 1) {</div> -<div> d[i] = val & expand_pred_h(pg[H1(i)]);</div> -<div> }</div> -<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div> -<div>index f840b43..3acfccb 100644</div> -<div>--- a/target/arm/translate-a64.c</div> -<div>+++ b/target/arm/translate-a64.c</div> -<div>@@ -492,7 +492,7 @@ static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)</div> -<div> {</div> -<div> TCGv_i32 v = tcg_temp_new_i32();</div> -<div> </div> -<div>- tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));</div> -<div>+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_UW));</div> -<div> return v;</div> -<div> }</div> -<div> </div> -<div>@@ -996,7 +996,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> case MO_UB:</div> -<div> tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1005,7 +1005,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> case MO_SB:</div> -<div> tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_16|MO_SIGN:</div> -<div>+ case MO_SW:</div> -<div> tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_32|MO_SIGN:</div> -<div>@@ -1028,13 +1028,13 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div> -<div> case MO_UB:</div> -<div> tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_SB:</div> -<div> tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_16|MO_SIGN:</div> -<div>+ case MO_SW:</div> -<div> tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1055,7 +1055,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div> -<div> case MO_UB:</div> -<div> tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1077,7 +1077,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div> -<div> case MO_UB:</div> -<div> tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -5269,7 +5269,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div> -<div> bool cmp_with_zero, bool signal_all_nans)</div> -<div> {</div> -<div> TCGv_i64 tcg_flags = tcg_temp_new_i64();</div> -<div>- TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);</div> -<div>+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_UW);</div> -<div> </div> -<div> if (size == MO_64) {</div> -<div> TCGv_i64 tcg_vn, tcg_vm;</div> -<div>@@ -5306,7 +5306,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div> -<div> gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (signal_all_nans) {</div> -<div> gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);</div> -<div> } else {</div> -<div>@@ -5360,7 +5360,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)</div> -<div> size = MO_64;</div> -<div> break;</div> -<div> case 3:</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> if (dc_isar_feature(aa64_fp16, s)) {</div> -<div> break;</div> -<div> }</div> -<div>@@ -5411,7 +5411,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)</div> -<div> size = MO_64;</div> -<div> break;</div> -<div> case 3:</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> if (dc_isar_feature(aa64_fp16, s)) {</div> -<div> break;</div> -<div> }</div> -<div>@@ -5477,7 +5477,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div> -<div> sz = MO_64;</div> -<div> break;</div> -<div> case 3:</div> -<div>- sz = MO_16;</div> -<div>+ sz = MO_UW;</div> -<div> if (dc_isar_feature(aa64_fp16, s)) {</div> -<div> break;</div> -<div> }</div> -<div>@@ -6282,7 +6282,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div> -<div> sz = MO_64;</div> -<div> break;</div> -<div> case 3:</div> -<div>- sz = MO_16;</div> -<div>+ sz = MO_UW;</div> -<div> if (dc_isar_feature(aa64_fp16, s)) {</div> -<div> break;</div> -<div> }</div> -<div>@@ -6593,7 +6593,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)</div> -<div> break;</div> -<div> case 3:</div> -<div> /* 16 bit */</div> -<div>- tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));</div> -<div>+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_UW));</div> -<div> break;</div> -<div> default:</div> -<div> g_assert_not_reached();</div> -<div>@@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,</div> -<div> {</div> -<div> if (esize == size) {</div> -<div> int element;</div> -<div>- TCGMemOp msize = esize == 16 ? MO_16 : MO_32;</div> -<div>+ TCGMemOp msize = esize == 16 ? MO_UW : MO_32;</div> -<div> TCGv_i32 tcg_elem;</div> -<div> </div> -<div> /* We should have one register left here */</div> -<div>@@ -7204,7 +7204,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)</div> -<div> * Note that correct NaN propagation requires that we do these</div> -<div> * operations in exactly the order specified by the pseudocode.</div> -<div> */</div> -<div>- TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);</div> -<div>+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_UW);</div> -<div> int fpopcode = opcode | is_min << 4 | is_u << 5;</div> -<div> int vmap = (1 << elements) - 1;</div> -<div> TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,</div> -<div>@@ -7591,7 +7591,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)</div> -<div> } else {</div> -<div> if (o2) {</div> -<div> /* FMOV (vector, immediate) - half-precision */</div> -<div>- imm = vfp_expand_imm(MO_16, abcdefgh);</div> -<div>+ imm = vfp_expand_imm(MO_UW, abcdefgh);</div> -<div> /* now duplicate across the lanes */</div> -<div> imm = bitfield_replicate(imm, 16);</div> -<div> } else {</div> -<div>@@ -7699,7 +7699,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> } else {</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> }</div> -<div> } else {</div> -<div> size = extract32(size, 0, 1) ? MO_64 : MO_32;</div> -<div>@@ -7709,7 +7709,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div> -<div> return;</div> -<div> }</div> -<div> </div> -<div>- fpst = get_fpstatus_ptr(size == MO_16);</div> -<div>+ fpst = get_fpstatus_ptr(size == MO_UW);</div> -<div> break;</div> -<div> default:</div> -<div> unallocated_encoding(s);</div> -<div>@@ -7760,7 +7760,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div> -<div> read_vec_element_i32(s, tcg_op1, rn, 0, size);</div> -<div> read_vec_element_i32(s, tcg_op2, rn, 1, size);</div> -<div> </div> -<div>- if (size == MO_16) {</div> -<div>+ if (size == MO_UW) {</div> -<div> switch (opcode) {</div> -<div> case 0xc: /* FMAXNMP */</div> -<div> gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);</div> -<div>@@ -8222,7 +8222,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div> -<div> int elements, int is_signed,</div> -<div> int fracbits, int size)</div> -<div> {</div> -<div>- TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);</div> -<div>+ TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_UW);</div> -<div> TCGv_i32 tcg_shift = NULL;</div> -<div> </div> -<div> TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);</div> -<div>@@ -8281,7 +8281,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div> -<div> }</div> -<div> }</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (fracbits) {</div> -<div> if (is_signed) {</div> -<div> gen_helper_vfp_sltoh(tcg_float, tcg_int32,</div> -<div>@@ -8339,7 +8339,7 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,</div> -<div> } else if (immh & 4) {</div> -<div> size = MO_32;</div> -<div> } else if (immh & 2) {</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> if (!dc_isar_feature(aa64_fp16, s)) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div>@@ -8384,7 +8384,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div> -<div> } else if (immh & 0x4) {</div> -<div> size = MO_32;</div> -<div> } else if (immh & 0x2) {</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> if (!dc_isar_feature(aa64_fp16, s)) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div>@@ -8403,7 +8403,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div> -<div> assert(!(is_scalar && is_q));</div> -<div> </div> -<div> tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));</div> -<div>- tcg_fpstatus = get_fpstatus_ptr(size == MO_16);</div> -<div>+ tcg_fpstatus = get_fpstatus_ptr(size == MO_UW);</div> -<div> gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);</div> -<div> fracbits = (16 << size) - immhb;</div> -<div> tcg_shift = tcg_const_i32(fracbits);</div> -<div>@@ -8429,7 +8429,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div> -<div> int maxpass = is_scalar ? 1 : ((8 << is_q) >> size);</div> -<div> </div> -<div> switch (size) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (is_u) {</div> -<div> fn = gen_helper_vfp_touhh;</div> -<div> } else {</div> -<div>@@ -9388,7 +9388,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div> -<div> return;</div> -<div> }</div> -<div> </div> -<div>- fpst = get_fpstatus_ptr(size == MO_16);</div> -<div>+ fpst = get_fpstatus_ptr(size == MO_UW);</div> -<div> </div> -<div> if (is_double) {</div> -<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div> -<div>@@ -9440,7 +9440,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div> -<div> bool swap = false;</div> -<div> int pass, maxpasses;</div> -<div> </div> -<div>- if (size == MO_16) {</div> -<div>+ if (size == MO_UW) {</div> -<div> switch (opcode) {</div> -<div> case 0x2e: /* FCMLT (zero) */</div> -<div> swap = true;</div> -<div>@@ -11422,8 +11422,8 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div> -<div> int passreg = pass < (maxpass / 2) ? rn : rm;</div> -<div> int passelt = (pass << 1) & (maxpass - 1);</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);</div> -<div>- read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);</div> -<div>+ read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_UW);</div> -<div>+ read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_UW);</div> -<div> tcg_res[pass] = tcg_temp_new_i32();</div> -<div> </div> -<div> switch (fpopcode) {</div> -<div>@@ -11450,7 +11450,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < maxpass; pass++) {</div> -<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);</div> -<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_UW);</div> -<div> tcg_temp_free_i32(tcg_res[pass]);</div> -<div> }</div> -<div> </div> -<div>@@ -11463,15 +11463,15 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i32 tcg_op2 = tcg_temp_new_i32();</div> -<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);</div> -<div>- read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);</div> -<div>+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_UW);</div> -<div>+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_UW);</div> -<div> </div> -<div> switch (fpopcode) {</div> -<div> case 0x0: /* FMAXNM */</div> -<div> gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);</div> -<div> break;</div> -<div> case 0x1: /* FMLA */</div> -<div>- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div> -<div>+ read_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div> -<div> gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,</div> -<div> fpst);</div> -<div> break;</div> -<div>@@ -11496,7 +11496,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div> -<div> case 0x9: /* FMLS */</div> -<div> /* As usual for ARM, separate negation for fused multiply-add */</div> -<div> tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);</div> -<div>- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div> -<div>+ read_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div> -<div> gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,</div> -<div> fpst);</div> -<div> break;</div> -<div>@@ -11537,7 +11537,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div> -<div> g_assert_not_reached();</div> -<div> }</div> -<div> </div> -<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div> -<div> tcg_temp_free_i32(tcg_res);</div> -<div> tcg_temp_free_i32(tcg_op1);</div> -<div> tcg_temp_free_i32(tcg_op2);</div> -<div>@@ -11727,7 +11727,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div> -<div> for (pass = 0; pass < 4; pass++) {</div> -<div> tcg_res[pass] = tcg_temp_new_i32();</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);</div> -<div>+ read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_UW);</div> -<div> gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],</div> -<div> fpst, ahp);</div> -<div> }</div> -<div>@@ -11768,7 +11768,7 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div> -<div> </div> -<div> read_vec_element(s, tcg_tmp, rn, i, grp_size);</div> -<div> switch (grp_size) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -12499,7 +12499,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div> -<div> if (!fp_access_check(s)) {</div> -<div> return;</div> -<div> }</div> -<div>- handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);</div> -<div>+ handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_UW);</div> -<div> return;</div> -<div> }</div> -<div> break;</div> -<div>@@ -12508,7 +12508,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div> -<div> case 0x2e: /* FCMLT (zero) */</div> -<div> case 0x6c: /* FCMGE (zero) */</div> -<div> case 0x6d: /* FCMLE (zero) */</div> -<div>- handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);</div> -<div>+ handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_UW, rn, rd);</div> -<div> return;</div> -<div> case 0x3d: /* FRECPE */</div> -<div> case 0x3f: /* FRECPX */</div> -<div>@@ -12668,7 +12668,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div> -<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op, rn, pass, MO_16);</div> -<div>+ read_vec_element_i32(s, tcg_op, rn, pass, MO_UW);</div> -<div> </div> -<div> switch (fpop) {</div> -<div> case 0x1a: /* FCVTNS */</div> -<div>@@ -12715,7 +12715,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div> -<div> g_assert_not_reached();</div> -<div> }</div> -<div> </div> -<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div> -<div> </div> -<div> tcg_temp_free_i32(tcg_res);</div> -<div> tcg_temp_free_i32(tcg_op);</div> -<div>@@ -12839,7 +12839,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> }</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> /* is_fp, but we pass cpu_env not fp_status. */</div> -<div> break;</div> -<div> default:</div> -<div>@@ -12852,7 +12852,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> /* convert insn encoded size to TCGMemOp size */</div> -<div> switch (size) {</div> -<div> case 0: /* half-precision */</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> is_fp16 = true;</div> -<div> break;</div> -<div> case MO_32: /* single precision */</div> -<div>@@ -12899,7 +12899,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> /* Given TCGMemOp size, adjust register and indexing. */</div> -<div> switch (size) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> index = h << 2 | l << 1 | m;</div> -<div> break;</div> -<div> case MO_32:</div> -<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div> -<div>index ec5fb11..2bc1bd1 100644</div> -<div>--- a/target/arm/translate-sve.c</div> -<div>+++ b/target/arm/translate-sve.c</div> -<div>@@ -1679,7 +1679,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div> -<div> tcg_temp_free_i32(t32);</div> -<div> break;</div> -<div> </div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> t32 = tcg_temp_new_i32();</div> -<div> tcg_gen_extrl_i64_i32(t32, val);</div> -<div> if (d) {</div> -<div>@@ -3314,7 +3314,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_sve_subri_h,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16,</div> -<div>+ .vece = MO_UW,</div> -<div> .scalar_first = true },</div> -<div> { .fni4 = tcg_gen_sub_i32,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div>@@ -3468,7 +3468,7 @@ static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)</div> -<div> </div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -3494,7 +3494,7 @@ static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)</div> -<div> </div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -3526,7 +3526,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,</div> -<div> </div> -<div> tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));</div> -<div> tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));</div> -<div>- status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> </div> -<div> fn(temp, t_zn, t_pg, status, t_desc);</div> -<div> tcg_temp_free_ptr(t_zn);</div> -<div>@@ -3568,7 +3568,7 @@ DO_VPZ(FMAXV, fmaxv)</div> -<div> static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)</div> -<div> {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> </div> -<div> tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div>@@ -3616,7 +3616,7 @@ static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a,</div> -<div> gen_helper_gvec_3_ptr *fn)</div> -<div> {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> </div> -<div> tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div>@@ -3668,7 +3668,7 @@ static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a)</div> -<div> }</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -3708,7 +3708,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)</div> -<div> t_pg = tcg_temp_new_ptr();</div> -<div> tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));</div> -<div> tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));</div> -<div>- t_fpst = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ t_fpst = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0));</div> -<div> </div> -<div> fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);</div> -<div>@@ -3735,7 +3735,7 @@ static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,</div> -<div> }</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -3777,7 +3777,7 @@ static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a,</div> -<div> }</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -3844,7 +3844,7 @@ static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,</div> -<div> gen_helper_sve_fp2scalar *fn)</div> -<div> {</div> -<div> TCGv_i64 temp = tcg_const_i64(imm);</div> -<div>- do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn);</div> -<div>+ do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_UW, temp, fn);</div> -<div> tcg_temp_free_i64(temp);</div> -<div> }</div> -<div> </div> -<div>@@ -3893,7 +3893,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a,</div> -<div> }</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -3937,7 +3937,7 @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)</div> -<div> }</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -4044,7 +4044,7 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)</div> -<div> tcg_debug_assert(a->rd == a->ra);</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn),</div> -<div> vec_full_reg_offset(s, a->rm),</div> -<div>@@ -4186,7 +4186,7 @@ static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)</div> -<div> if (a->esz == 0) {</div> -<div> return false;</div> -<div> }</div> -<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,</div> -<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW,</div> -<div> frint_fns[a->esz - 1]);</div> -<div> }</div> -<div> </div> -<div>@@ -4200,7 +4200,7 @@ static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)</div> -<div> if (a->esz == 0) {</div> -<div> return false;</div> -<div> }</div> -<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);</div> -<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW, fns[a->esz - 1]);</div> -<div> }</div> -<div> </div> -<div> static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)</div> -<div>@@ -4211,7 +4211,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div> TCGv_i32 tmode = tcg_const_i32(mode);</div> -<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div> -<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div> -<div> </div> -<div> gen_helper_set_rmode(tmode, tmode, status);</div> -<div> </div> -<div>@@ -4262,7 +4262,7 @@ static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)</div> -<div> if (a->esz == 0) {</div> -<div> return false;</div> -<div> }</div> -<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);</div> -<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW, fns[a->esz - 1]);</div> -<div> }</div> -<div> </div> -<div> static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)</div> -<div>@@ -4275,7 +4275,7 @@ static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)</div> -<div> if (a->esz == 0) {</div> -<div> return false;</div> -<div> }</div> -<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);</div> -<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW, fns[a->esz - 1]);</div> -<div> }</div> -<div> </div> -<div> static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a)</div> -<div>diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c</div> -<div>index 092eb5e..549874c 100644</div> -<div>--- a/target/arm/translate-vfp.inc.c</div> -<div>+++ b/target/arm/translate-vfp.inc.c</div> -<div>@@ -52,7 +52,7 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8)</div> -<div> (extract32(imm8, 0, 6) << 3);</div> -<div> imm <<= 16;</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |</div> -<div> (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |</div> -<div> (extract32(imm8, 0, 6) << 6);</div> -<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div> -<div>index 39266cf..8d10922 100644</div> -<div>--- a/target/arm/translate.c</div> -<div>+++ b/target/arm/translate.c</div> -<div>@@ -1477,7 +1477,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div> -<div> case MO_UB:</div> -<div> tcg_gen_st8_i32(var, cpu_env, offset);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_st16_i32(var, cpu_env, offset);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1496,7 +1496,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div> -<div> case MO_UB:</div> -<div> tcg_gen_st8_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_st16_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -4267,7 +4267,7 @@ const GVecGen2i ssra_op[4] = {</div> -<div> .fniv = gen_ssra_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_ssra,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = gen_ssra32_i32,</div> -<div> .fniv = gen_ssra_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4325,7 +4325,7 @@ const GVecGen2i usra_op[4] = {</div> -<div> .fniv = gen_usra_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_usra,</div> -<div>- .vece = MO_16, },</div> -<div>+ .vece = MO_UW, },</div> -<div> { .fni4 = gen_usra32_i32,</div> -<div> .fniv = gen_usra_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4353,7 +4353,7 @@ static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div> </div> -<div> static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_16, 0xffff >> shift);</div> -<div>+ uint64_t mask = dup_const(MO_UW, 0xffff >> shift);</div> -<div> TCGv_i64 t = tcg_temp_new_i64();</div> -<div> </div> -<div> tcg_gen_shri_i64(t, a, shift);</div> -<div>@@ -4405,7 +4405,7 @@ const GVecGen2i sri_op[4] = {</div> -<div> .fniv = gen_shr_ins_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sri,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = gen_shr32_ins_i32,</div> -<div> .fniv = gen_shr_ins_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4433,7 +4433,7 @@ static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div> </div> -<div> static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_16, 0xffff << shift);</div> -<div>+ uint64_t mask = dup_const(MO_UW, 0xffff << shift);</div> -<div> TCGv_i64 t = tcg_temp_new_i64();</div> -<div> </div> -<div> tcg_gen_shli_i64(t, a, shift);</div> -<div>@@ -4483,7 +4483,7 @@ const GVecGen2i sli_op[4] = {</div> -<div> .fniv = gen_shl_ins_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sli,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = gen_shl32_ins_i32,</div> -<div> .fniv = gen_shl_ins_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4579,7 +4579,7 @@ const GVecGen3 mla_op[4] = {</div> -<div> .fniv = gen_mla_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mla,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = gen_mla32_i32,</div> -<div> .fniv = gen_mla_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4603,7 +4603,7 @@ const GVecGen3 mls_op[4] = {</div> -<div> .fniv = gen_mls_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mls,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = gen_mls32_i32,</div> -<div> .fniv = gen_mls_vec,</div> -<div> .load_dest = true,</div> -<div>@@ -4649,7 +4649,7 @@ const GVecGen3 cmtst_op[4] = {</div> -<div> { .fni4 = gen_helper_neon_tst_u16,</div> -<div> .fniv = gen_cmtst_vec,</div> -<div> .opt_opc = vecop_list_cmtst,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = gen_cmtst_i32,</div> -<div> .fniv = gen_cmtst_vec,</div> -<div> .opt_opc = vecop_list_cmtst,</div> -<div>@@ -4686,7 +4686,7 @@ const GVecGen4 uqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqadd_h,</div> -<div> .write_aofs = true,</div> -<div> .opt_opc = vecop_list_uqadd,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fniv = gen_uqadd_vec,</div> -<div> .fno = gen_helper_gvec_uqadd_s,</div> -<div> .write_aofs = true,</div> -<div>@@ -4724,7 +4724,7 @@ const GVecGen4 sqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqadd_h,</div> -<div> .opt_opc = vecop_list_sqadd,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fniv = gen_sqadd_vec,</div> -<div> .fno = gen_helper_gvec_sqadd_s,</div> -<div> .opt_opc = vecop_list_sqadd,</div> -<div>@@ -4762,7 +4762,7 @@ const GVecGen4 uqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqsub_h,</div> -<div> .opt_opc = vecop_list_uqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fniv = gen_uqsub_vec,</div> -<div> .fno = gen_helper_gvec_uqsub_s,</div> -<div> .opt_opc = vecop_list_uqsub,</div> -<div>@@ -4800,7 +4800,7 @@ const GVecGen4 sqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqsub_h,</div> -<div> .opt_opc = vecop_list_sqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fniv = gen_sqsub_vec,</div> -<div> .fno = gen_helper_gvec_sqsub_s,</div> -<div> .opt_opc = vecop_list_sqsub,</div> -<div>@@ -6876,7 +6876,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div> -<div> size = MO_UB;</div> -<div> element = (insn >> 17) & 7;</div> -<div> } else if (insn & (1 << 17)) {</div> -<div>- size = MO_16;</div> -<div>+ size = MO_UW;</div> -<div> element = (insn >> 18) & 3;</div> -<div> } else {</div> -<div> size = MO_32;</div> -<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div> -<div>index 0e45300..0535bae 100644</div> -<div>--- a/target/i386/translate.c</div> -<div>+++ b/target/i386/translate.c</div> -<div>@@ -323,7 +323,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int reg)</div> -<div> static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div> -<div> {</div> -<div> if (CODE64(s)) {</div> -<div>- return ot == MO_16 ? MO_16 : MO_64;</div> -<div>+ return ot == MO_UW ? MO_UW : MO_64;</div> -<div> } else {</div> -<div> return ot;</div> -<div> }</div> -<div>@@ -332,7 +332,7 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div> -<div> /* Select the size of the stack pointer. */</div> -<div> static inline TCGMemOp mo_stacksize(DisasContext *s)</div> -<div> {</div> -<div>- return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div> -<div>+ return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div> -<div> }</div> -<div> </div> -<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div> -<div>@@ -356,7 +356,7 @@ static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div> -<div> Used for decoding operand size of port opcodes. */</div> -<div> static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div> -<div> {</div> -<div>- return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_UB;</div> -<div>+ return b & 1 ? (ot == MO_UW ? MO_UW : MO_32) : MO_UB;</div> -<div> }</div> -<div> </div> -<div> static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div>@@ -369,7 +369,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div> tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -473,7 +473,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div> -<div> return;</div> -<div> }</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> /* 16 bit address */</div> -<div> tcg_gen_ext16u_tl(s->A0, a0);</div> -<div> a0 = s->A0;</div> -<div>@@ -530,7 +530,7 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div> -<div> tcg_gen_ext8u_tl(dst, src);</div> -<div> }</div> -<div> return dst;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (sign) {</div> -<div> tcg_gen_ext16s_tl(dst, src);</div> -<div> } else {</div> -<div>@@ -583,7 +583,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div> -<div> case MO_UB:</div> -<div> gen_helper_inb(v, cpu_env, n);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_helper_inw(v, cpu_env, n);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -600,7 +600,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div> -<div> case MO_UB:</div> -<div> gen_helper_outb(cpu_env, v, n);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_helper_outw(cpu_env, v, n);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -622,7 +622,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div> -<div> case MO_UB:</div> -<div> gen_helper_check_iob(cpu_env, s->tmp2_i32);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_helper_check_iow(cpu_env, s->tmp2_i32);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1562,7 +1562,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div> -<div> tcg_gen_ext8u_tl(s->T0, s->T0);</div> -<div> tcg_gen_muli_tl(s->T0, s->T0, 0x01010101);</div> -<div> goto do_long;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> /* Replicate the 16-bit input so that a 32-bit rotate works. */</div> -<div> tcg_gen_deposit_tl(s->T0, s->T0, s->T0, 16, 16);</div> -<div> goto do_long;</div> -<div>@@ -1664,7 +1664,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> case MO_UB:</div> -<div> mask = 7;</div> -<div> goto do_shifts;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> mask = 15;</div> -<div> do_shifts:</div> -<div> shift = op2 & mask;</div> -<div>@@ -1722,7 +1722,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> case MO_UB:</div> -<div> gen_helper_rcrb(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_helper_rcrw(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1741,7 +1741,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> case MO_UB:</div> -<div> gen_helper_rclb(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_helper_rclw(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1778,7 +1778,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> tcg_gen_andi_tl(count, count_in, mask);</div> -<div> </div> -<div> switch (ot) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> /* Note: we implement the Intel behaviour for shift count > 16.</div> -<div> This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A</div> -<div> portion by constructing it as a 32-bit value. */</div> -<div>@@ -1817,7 +1817,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> tcg_gen_shl_tl(s->T1, s->T1, s->tmp4);</div> -<div> } else {</div> -<div> tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0);</div> -<div>- if (ot == MO_16) {</div> -<div>+ if (ot == MO_UW) {</div> -<div> /* Only needed if count > 16, for Intel behaviour. */</div> -<div> tcg_gen_subfi_tl(s->tmp4, 33, count);</div> -<div> tcg_gen_shr_tl(s->tmp4, s->T1, s->tmp4);</div> -<div>@@ -2026,7 +2026,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,</div> -<div> }</div> -<div> break;</div> -<div> </div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (mod == 0) {</div> -<div> if (rm == 6) {</div> -<div> base = -1;</div> -<div>@@ -2187,7 +2187,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div> -<div> case MO_UB:</div> -<div> ret = x86_ldub_code(env, s);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> ret = x86_lduw_code(env, s);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -2400,12 +2400,12 @@ static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)</div> -<div> </div> -<div> static inline void gen_stack_A0(DisasContext *s)</div> -<div> {</div> -<div>- gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1);</div> -<div>+ gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_UW, cpu_regs[R_ESP], R_SS, -1);</div> -<div> }</div> -<div> </div> -<div> static void gen_pusha(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div> -<div>+ TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div> -<div> TCGMemOp d_ot = s->dflag;</div> -<div> int size = 1 << d_ot;</div> -<div> int i;</div> -<div>@@ -2421,7 +2421,7 @@ static void gen_pusha(DisasContext *s)</div> -<div> </div> -<div> static void gen_popa(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div> -<div>+ TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div> -<div> TCGMemOp d_ot = s->dflag;</div> -<div> int size = 1 << d_ot;</div> -<div> int i;</div> -<div>@@ -2443,7 +2443,7 @@ static void gen_popa(DisasContext *s)</div> -<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div> -<div> {</div> -<div> TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div> -<div>+ TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div> -<div> int size = 1 << d_ot;</div> -<div> </div> -<div> /* Push BP; compute FrameTemp into T1. */</div> -<div>@@ -3613,7 +3613,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> case 0xc4: /* pinsrw */</div> -<div> case 0x1c4:</div> -<div> s->rip_offset = 1;</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div> val = x86_ldub_code(env, s);</div> -<div> if (b1) {</div> -<div> val &= 7;</div> -<div>@@ -3786,7 +3786,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> if ((b & 0xff) == 0xf0) {</div> -<div> ot = MO_UB;</div> -<div> } else if (s->dflag != MO_64) {</div> -<div>- ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);</div> -<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div> -<div> } else {</div> -<div> ot = MO_64;</div> -<div> }</div> -<div>@@ -3815,7 +3815,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> if (s->dflag != MO_64) {</div> -<div>- ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);</div> -<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div> -<div> } else {</div> -<div> ot = MO_64;</div> -<div> }</div> -<div>@@ -4630,7 +4630,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* In 64-bit mode, the default data size is 32-bit. Select 64-bit</div> -<div> data with rex_w, and 16-bit data with 0x66; rex_w takes precedence</div> -<div> over 0x66 if both are present. */</div> -<div>- dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);</div> -<div>+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_32);</div> -<div> /* In 64-bit mode, 0x67 selects 32-bit addressing. */</div> -<div> aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);</div> -<div> } else {</div> -<div>@@ -4638,13 +4638,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {</div> -<div> dflag = MO_32;</div> -<div> } else {</div> -<div>- dflag = MO_16;</div> -<div>+ dflag = MO_UW;</div> -<div> }</div> -<div> /* In 16/32-bit mode, 0x67 selects the opposite addressing. */</div> -<div> if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {</div> -<div> aflag = MO_32;</div> -<div> } else {</div> -<div>- aflag = MO_16;</div> -<div>+ aflag = MO_UW;</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>@@ -4872,21 +4872,21 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tcg_gen_ext8u_tl(s->T1, s->T1);</div> -<div> /* XXX: use 32 bit mul which could be faster */</div> -<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div> -<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div> -<div> tcg_gen_andi_tl(cpu_cc_src, s->T0, 0xff00);</div> -<div> set_cc_op(s, CC_OP_MULB);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>- gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);</div> -<div>+ case MO_UW:</div> -<div>+ gen_op_mov_v_reg(s, MO_UW, s->T1, R_EAX);</div> -<div> tcg_gen_ext16u_tl(s->T0, s->T0);</div> -<div> tcg_gen_ext16u_tl(s->T1, s->T1);</div> -<div> /* XXX: use 32 bit mul which could be faster */</div> -<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div> -<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div> -<div> tcg_gen_shri_tl(s->T0, s->T0, 16);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EDX, s->T0);</div> -<div> tcg_gen_mov_tl(cpu_cc_src, s->T0);</div> -<div> set_cc_op(s, CC_OP_MULW);</div> -<div> break;</div> -<div>@@ -4921,24 +4921,24 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tcg_gen_ext8s_tl(s->T1, s->T1);</div> -<div> /* XXX: use 32 bit mul which could be faster */</div> -<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div> -<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div> -<div> tcg_gen_ext8s_tl(s->tmp0, s->T0);</div> -<div> tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);</div> -<div> set_cc_op(s, CC_OP_MULB);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>- gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);</div> -<div>+ case MO_UW:</div> -<div>+ gen_op_mov_v_reg(s, MO_UW, s->T1, R_EAX);</div> -<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div> -<div> tcg_gen_ext16s_tl(s->T1, s->T1);</div> -<div> /* XXX: use 32 bit mul which could be faster */</div> -<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div> -<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div> -<div> tcg_gen_ext16s_tl(s->tmp0, s->T0);</div> -<div> tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);</div> -<div> tcg_gen_shri_tl(s->T0, s->T0, 16);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EDX, s->T0);</div> -<div> set_cc_op(s, CC_OP_MULW);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -4972,7 +4972,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case MO_UB:</div> -<div> gen_helper_divb_AL(cpu_env, s->T0);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_helper_divw_AX(cpu_env, s->T0);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -4991,7 +4991,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case MO_UB:</div> -<div> gen_helper_idivb_AL(cpu_env, s->T0);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_helper_idivw_AX(cpu_env, s->T0);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -5026,7 +5026,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* operand size for jumps is 64 bit */</div> -<div> ot = MO_64;</div> -<div> } else if (op == 3 || op == 5) {</div> -<div>- ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16;</div> -<div>+ ot = dflag != MO_UW ? MO_32 + (rex_w == 1) : MO_UW;</div> -<div> } else if (op == 6) {</div> -<div> /* default push size is 64 bit */</div> -<div> ot = mo_pushpop(s, dflag);</div> -<div>@@ -5057,7 +5057,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> case 2: /* call Ev */</div> -<div> /* XXX: optimize if memory (no 'and' is necessary) */</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tcg_gen_ext16u_tl(s->T0, s->T0);</div> -<div> }</div> -<div> next_eip = s->pc - s->cs_base;</div> -<div>@@ -5070,7 +5070,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 3: /* lcall Ev */</div> -<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div> -<div> gen_add_A0_im(s, 1 << ot);</div> -<div>- gen_op_ld_v(s, MO_16, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UW, s->T0, s->A0);</div> -<div> do_lcall:</div> -<div> if (s->pe && !s->vm86) {</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div>@@ -5087,7 +5087,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_jr(s, s->tmp4);</div> -<div> break;</div> -<div> case 4: /* jmp Ev */</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tcg_gen_ext16u_tl(s->T0, s->T0);</div> -<div> }</div> -<div> gen_op_jmp_v(s->T0);</div> -<div>@@ -5097,7 +5097,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 5: /* ljmp Ev */</div> -<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div> -<div> gen_add_A0_im(s, 1 << ot);</div> -<div>- gen_op_ld_v(s, MO_16, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UW, s->T0, s->A0);</div> -<div> do_ljmp:</div> -<div> if (s->pe && !s->vm86) {</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div>@@ -5152,14 +5152,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> #endif</div> -<div> case MO_32:</div> -<div>- gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);</div> -<div>+ gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div> -<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div> -<div> gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> gen_op_mov_v_reg(s, MO_UB, s->T0, R_EAX);</div> -<div> tcg_gen_ext8s_tl(s->T0, s->T0);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div> -<div> break;</div> -<div> default:</div> -<div> tcg_abort();</div> -<div>@@ -5180,11 +5180,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tcg_gen_sari_tl(s->T0, s->T0, 31);</div> -<div> gen_op_mov_reg_v(s, MO_32, R_EDX, s->T0);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>- gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);</div> -<div>+ case MO_UW:</div> -<div>+ gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div> -<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div> -<div> tcg_gen_sari_tl(s->T0, s->T0, 15);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EDX, s->T0);</div> -<div> break;</div> -<div> default:</div> -<div> tcg_abort();</div> -<div>@@ -5538,7 +5538,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> reg = (modrm >> 3) & 7;</div> -<div> if (reg >= 6 || reg == R_CS)</div> -<div> goto illegal_op;</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div> gen_movl_seg_T0(s, reg);</div> -<div> /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */</div> -<div> if (s->base.is_jmp) {</div> -<div>@@ -5558,7 +5558,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (reg >= 6)</div> -<div> goto illegal_op;</div> -<div> gen_op_movl_T0_seg(s, reg);</div> -<div>- ot = mod == 3 ? dflag : MO_16;</div> -<div>+ ot = mod == 3 ? dflag : MO_UW;</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div> -<div> break;</div> -<div> </div> -<div>@@ -5734,7 +5734,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x1b5: /* lgs Gv */</div> -<div> op = R_GS;</div> -<div> do_lxx:</div> -<div>- ot = dflag != MO_16 ? MO_32 : MO_16;</div> -<div>+ ot = dflag != MO_UW ? MO_32 : MO_UW;</div> -<div> modrm = x86_ldub_code(env, s);</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div> mod = (modrm >> 6) & 3;</div> -<div>@@ -5744,7 +5744,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div> -<div> gen_add_A0_im(s, 1 << ot);</div> -<div> /* load the segment first to handle exceptions properly */</div> -<div>- gen_op_ld_v(s, MO_16, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UW, s->T0, s->A0);</div> -<div> gen_movl_seg_T0(s, op);</div> -<div> /* then put the data */</div> -<div> gen_op_mov_reg_v(s, ot, reg, s->T1);</div> -<div>@@ -6287,7 +6287,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0:</div> -<div> gen_helper_fnstsw(s->tmp2_i32, cpu_env);</div> -<div> tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);</div> -<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div> -<div> break;</div> -<div> default:</div> -<div> goto unknown_op;</div> -<div>@@ -6575,14 +6575,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> case 0xe8: /* call im */</div> -<div> {</div> -<div>- if (dflag != MO_16) {</div> -<div>+ if (dflag != MO_UW) {</div> -<div> tval = (int32_t)insn_get(env, s, MO_32);</div> -<div> } else {</div> -<div>- tval = (int16_t)insn_get(env, s, MO_16);</div> -<div>+ tval = (int16_t)insn_get(env, s, MO_UW);</div> -<div> }</div> -<div> next_eip = s->pc - s->cs_base;</div> -<div> tval += next_eip;</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tval &= 0xffff;</div> -<div> } else if (!CODE64(s)) {</div> -<div> tval &= 0xffffffff;</div> -<div>@@ -6601,20 +6601,20 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> goto illegal_op;</div> -<div> ot = dflag;</div> -<div> offset = insn_get(env, s, ot);</div> -<div>- selector = insn_get(env, s, MO_16);</div> -<div>+ selector = insn_get(env, s, MO_UW);</div> -<div> </div> -<div> tcg_gen_movi_tl(s->T0, selector);</div> -<div> tcg_gen_movi_tl(s->T1, offset);</div> -<div> }</div> -<div> goto do_lcall;</div> -<div> case 0xe9: /* jmp im */</div> -<div>- if (dflag != MO_16) {</div> -<div>+ if (dflag != MO_UW) {</div> -<div> tval = (int32_t)insn_get(env, s, MO_32);</div> -<div> } else {</div> -<div>- tval = (int16_t)insn_get(env, s, MO_16);</div> -<div>+ tval = (int16_t)insn_get(env, s, MO_UW);</div> -<div> }</div> -<div> tval += s->pc - s->cs_base;</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tval &= 0xffff;</div> -<div> } else if (!CODE64(s)) {</div> -<div> tval &= 0xffffffff;</div> -<div>@@ -6630,7 +6630,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> goto illegal_op;</div> -<div> ot = dflag;</div> -<div> offset = insn_get(env, s, ot);</div> -<div>- selector = insn_get(env, s, MO_16);</div> -<div>+ selector = insn_get(env, s, MO_UW);</div> -<div> </div> -<div> tcg_gen_movi_tl(s->T0, selector);</div> -<div> tcg_gen_movi_tl(s->T1, offset);</div> -<div>@@ -6639,7 +6639,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0xeb: /* jmp Jb */</div> -<div> tval = (int8_t)insn_get(env, s, MO_UB);</div> -<div> tval += s->pc - s->cs_base;</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tval &= 0xffff;</div> -<div> }</div> -<div> gen_jmp(s, tval);</div> -<div>@@ -6648,15 +6648,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tval = (int8_t)insn_get(env, s, MO_UB);</div> -<div> goto do_jcc;</div> -<div> case 0x180 ... 0x18f: /* jcc Jv */</div> -<div>- if (dflag != MO_16) {</div> -<div>+ if (dflag != MO_UW) {</div> -<div> tval = (int32_t)insn_get(env, s, MO_32);</div> -<div> } else {</div> -<div>- tval = (int16_t)insn_get(env, s, MO_16);</div> -<div>+ tval = (int16_t)insn_get(env, s, MO_UW);</div> -<div> }</div> -<div> do_jcc:</div> -<div> next_eip = s->pc - s->cs_base;</div> -<div> tval += next_eip;</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tval &= 0xffff;</div> -<div> }</div> -<div> gen_bnd_jmp(s);</div> -<div>@@ -6697,7 +6697,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> } else {</div> -<div> ot = gen_pop_T0(s);</div> -<div> if (s->cpl == 0) {</div> -<div>- if (dflag != MO_16) {</div> -<div>+ if (dflag != MO_UW) {</div> -<div> gen_helper_write_eflags(cpu_env, s->T0,</div> -<div> tcg_const_i32((TF_MASK | AC_MASK |</div> -<div> ID_MASK | NT_MASK |</div> -<div>@@ -6712,7 +6712,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> }</div> -<div> } else {</div> -<div> if (s->cpl <= s->iopl) {</div> -<div>- if (dflag != MO_16) {</div> -<div>+ if (dflag != MO_UW) {</div> -<div> gen_helper_write_eflags(cpu_env, s->T0,</div> -<div> tcg_const_i32((TF_MASK |</div> -<div> AC_MASK |</div> -<div>@@ -6729,7 +6729,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> & 0xffff));</div> -<div> }</div> -<div> } else {</div> -<div>- if (dflag != MO_16) {</div> -<div>+ if (dflag != MO_UW) {</div> -<div> gen_helper_write_eflags(cpu_env, s->T0,</div> -<div> tcg_const_i32((TF_MASK | AC_MASK |</div> -<div> ID_MASK | NT_MASK)));</div> -<div>@@ -7110,7 +7110,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_op_mov_v_reg(s, ot, s->T0, reg);</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div>- if (ot == MO_16) {</div> -<div>+ if (ot == MO_UW) {</div> -<div> gen_helper_boundw(cpu_env, s->A0, s->tmp2_i32);</div> -<div> } else {</div> -<div> gen_helper_boundl(cpu_env, s->A0, s->tmp2_i32);</div> -<div>@@ -7149,7 +7149,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tval = (int8_t)insn_get(env, s, MO_UB);</div> -<div> next_eip = s->pc - s->cs_base;</div> -<div> tval += next_eip;</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tval &= 0xffff;</div> -<div> }</div> -<div> </div> -<div>@@ -7291,7 +7291,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State, ldt.selector));</div> -<div>- ot = mod == 3 ? dflag : MO_16;</div> -<div>+ ot = mod == 3 ? dflag : MO_UW;</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div> -<div> break;</div> -<div> case 2: /* lldt */</div> -<div>@@ -7301,7 +7301,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);</div> -<div> } else {</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> gen_helper_lldt(cpu_env, s->tmp2_i32);</div> -<div> }</div> -<div>@@ -7312,7 +7312,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State, tr.selector));</div> -<div>- ot = mod == 3 ? dflag : MO_16;</div> -<div>+ ot = mod == 3 ? dflag : MO_UW;</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div> -<div> break;</div> -<div> case 3: /* ltr */</div> -<div>@@ -7322,7 +7322,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);</div> -<div> } else {</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> gen_helper_ltr(cpu_env, s->tmp2_i32);</div> -<div> }</div> -<div>@@ -7331,7 +7331,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 5: /* verw */</div> -<div> if (!s->pe || s->vm86)</div> -<div> goto illegal_op;</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div> gen_update_cc_op(s);</div> -<div> if (op == 4) {</div> -<div> gen_helper_verr(cpu_env, s->T0);</div> -<div>@@ -7353,10 +7353,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div> tcg_gen_ld32u_tl(s->T0,</div> -<div> cpu_env, offsetof(CPUX86State, gdt.limit));</div> -<div>- gen_op_st_v(s, MO_16, s->T0, s->A0);</div> -<div>+ gen_op_st_v(s, MO_UW, s->T0, s->A0);</div> -<div> gen_add_A0_im(s, 2);</div> -<div> tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base));</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div> gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>@@ -7408,10 +7408,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.limit));</div> -<div>- gen_op_st_v(s, MO_16, s->T0, s->A0);</div> -<div>+ gen_op_st_v(s, MO_UW, s->T0, s->A0);</div> -<div> gen_add_A0_im(s, 2);</div> -<div> tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base));</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div> gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>@@ -7558,10 +7558,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> }</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE);</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div>- gen_op_ld_v(s, MO_16, s->T1, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div> -<div> gen_add_A0_im(s, 2);</div> -<div> gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div> tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base));</div> -<div>@@ -7575,10 +7575,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> }</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE);</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div>- gen_op_ld_v(s, MO_16, s->T1, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div> -<div> gen_add_A0_im(s, 2);</div> -<div> gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>- if (dflag == MO_16) {</div> -<div>+ if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div> tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base));</div> -<div>@@ -7590,9 +7590,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0]));</div> -<div> if (CODE64(s)) {</div> -<div> mod = (modrm >> 6) & 3;</div> -<div>- ot = (mod != 3 ? MO_16 : s->dflag);</div> -<div>+ ot = (mod != 3 ? MO_UW : s->dflag);</div> -<div> } else {</div> -<div>- ot = MO_16;</div> -<div>+ ot = MO_UW;</div> -<div> }</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div> -<div> break;</div> -<div>@@ -7619,7 +7619,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> }</div> -<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div> gen_helper_lmsw(cpu_env, s->T0);</div> -<div> gen_jmp_im(s, s->pc - s->cs_base);</div> -<div> gen_eob(s);</div> -<div>@@ -7720,7 +7720,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> t0 = tcg_temp_local_new();</div> -<div> t1 = tcg_temp_local_new();</div> -<div> t2 = tcg_temp_local_new();</div> -<div>- ot = MO_16;</div> -<div>+ ot = MO_UW;</div> -<div> modrm = x86_ldub_code(env, s);</div> -<div> reg = (modrm >> 3) & 7;</div> -<div> mod = (modrm >> 6) & 3;</div> -<div>@@ -7765,10 +7765,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> TCGv t0;</div> -<div> if (!s->pe || s->vm86)</div> -<div> goto illegal_op;</div> -<div>- ot = dflag != MO_16 ? MO_32 : MO_16;</div> -<div>+ ot = dflag != MO_UW ? MO_32 : MO_UW;</div> -<div> modrm = x86_ldub_code(env, s);</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div> t0 = tcg_temp_local_new();</div> -<div> gen_update_cc_op(s);</div> -<div> if (b == 0x102) {</div> -<div>@@ -7813,7 +7813,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* bndcl */</div> -<div> if (reg >= 4</div> -<div> || (prefixes & PREFIX_LOCK)</div> -<div>- || s->aflag == MO_16) {</div> -<div>+ || s->aflag == MO_UW) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> gen_bndck(env, s, modrm, TCG_COND_LTU, cpu_bndl[reg]);</div> -<div>@@ -7821,7 +7821,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* bndcu */</div> -<div> if (reg >= 4</div> -<div> || (prefixes & PREFIX_LOCK)</div> -<div>- || s->aflag == MO_16) {</div> -<div>+ || s->aflag == MO_UW) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> TCGv_i64 notu = tcg_temp_new_i64();</div> -<div>@@ -7830,7 +7830,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tcg_temp_free_i64(notu);</div> -<div> } else if (prefixes & PREFIX_DATA) {</div> -<div> /* bndmov -- from reg/mem */</div> -<div>- if (reg >= 4 || s->aflag == MO_16) {</div> -<div>+ if (reg >= 4 || s->aflag == MO_UW) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> if (mod == 3) {</div> -<div>@@ -7865,7 +7865,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div> -<div> if (reg >= 4</div> -<div> || (prefixes & PREFIX_LOCK)</div> -<div>- || s->aflag == MO_16</div> -<div>+ || s->aflag == MO_UW</div> -<div> || a.base < -1) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div>@@ -7903,7 +7903,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* bndmk */</div> -<div> if (reg >= 4</div> -<div> || (prefixes & PREFIX_LOCK)</div> -<div>- || s->aflag == MO_16) {</div> -<div>+ || s->aflag == MO_UW) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div> -<div>@@ -7931,13 +7931,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* bndcn */</div> -<div> if (reg >= 4</div> -<div> || (prefixes & PREFIX_LOCK)</div> -<div>- || s->aflag == MO_16) {</div> -<div>+ || s->aflag == MO_UW) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]);</div> -<div> } else if (prefixes & PREFIX_DATA) {</div> -<div> /* bndmov -- to reg/mem */</div> -<div>- if (reg >= 4 || s->aflag == MO_16) {</div> -<div>+ if (reg >= 4 || s->aflag == MO_UW) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> if (mod == 3) {</div> -<div>@@ -7970,7 +7970,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div> -<div> if (reg >= 4</div> -<div> || (prefixes & PREFIX_LOCK)</div> -<div>- || s->aflag == MO_16</div> -<div>+ || s->aflag == MO_UW</div> -<div> || a.base < -1) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div>@@ -8341,7 +8341,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div> </div> -<div> if (s->prefix & PREFIX_DATA) {</div> -<div>- ot = MO_16;</div> -<div>+ ot = MO_UW;</div> -<div> } else {</div> -<div> ot = mo_64_32(dflag);</div> -<div> }</div> -<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div> -<div>index 20a9777..525c7fe 100644</div> -<div>--- a/target/mips/translate.c</div> -<div>+++ b/target/mips/translate.c</div> -<div>@@ -21087,7 +21087,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,</div> -<div> imm = sextract32(ctx->opcode, 11, 11);</div> -<div> imm = (int16_t)(imm << 6) >> 6;</div> -<div> if (rt != 0) {</div> -<div>- tcg_gen_movi_tl(cpu_gpr[rt], dup_const(MO_16, imm));</div> -<div>+ tcg_gen_movi_tl(cpu_gpr[rt], dup_const(MO_UW, imm));</div> -<div> }</div> -<div> }</div> -<div> break;</div> -<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div> -<div>index 4130dd1..71efef4 100644</div> -<div>--- a/target/ppc/translate/vmx-impl.inc.c</div> -<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div> -<div>@@ -406,29 +406,29 @@ static void glue(gen_, name)(DisasContext *ctx) \</div> -<div> GEN_VXFORM_V(vaddubm, MO_UB, tcg_gen_gvec_add, 0, 0);</div> -<div> GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \</div> -<div> vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div> -<div>-GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);</div> -<div>+GEN_VXFORM_V(vadduhm, MO_UW, tcg_gen_gvec_add, 0, 1);</div> -<div> GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);</div> -<div> GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div> -<div> GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div> -<div>-GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);</div> -<div>+GEN_VXFORM_V(vsubuhm, MO_UW, tcg_gen_gvec_sub, 0, 17);</div> -<div> GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);</div> -<div> GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div> -<div> GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div> -<div>-GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);</div> -<div>+GEN_VXFORM_V(vmaxuh, MO_UW, tcg_gen_gvec_umax, 1, 1);</div> -<div> GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);</div> -<div> GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div> -<div> GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div> -<div>-GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);</div> -<div>+GEN_VXFORM_V(vmaxsh, MO_UW, tcg_gen_gvec_smax, 1, 5);</div> -<div> GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);</div> -<div> GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div> -<div> GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div> -<div>-GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);</div> -<div>+GEN_VXFORM_V(vminuh, MO_UW, tcg_gen_gvec_umin, 1, 9);</div> -<div> GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);</div> -<div> GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div> -<div> GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div> -<div>-GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);</div> -<div>+GEN_VXFORM_V(vminsh, MO_UW, tcg_gen_gvec_smin, 1, 13);</div> -<div> GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);</div> -<div> GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div> -<div> GEN_VXFORM(vavgub, 1, 16);</div> -<div>@@ -531,18 +531,18 @@ GEN_VXFORM(vmulesb, 4, 12);</div> -<div> GEN_VXFORM(vmulesh, 4, 13);</div> -<div> GEN_VXFORM(vmulesw, 4, 14);</div> -<div> GEN_VXFORM_V(vslb, MO_UB, tcg_gen_gvec_shlv, 2, 4);</div> -<div>-GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);</div> -<div>+GEN_VXFORM_V(vslh, MO_UW, tcg_gen_gvec_shlv, 2, 5);</div> -<div> GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);</div> -<div> GEN_VXFORM(vrlwnm, 2, 6);</div> -<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div> -<div> GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div> -<div>-GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);</div> -<div>+GEN_VXFORM_V(vsrh, MO_UW, tcg_gen_gvec_shrv, 2, 9);</div> -<div> GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);</div> -<div> GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div> -<div> GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div> -<div>-GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);</div> -<div>+GEN_VXFORM_V(vsrah, MO_UW, tcg_gen_gvec_sarv, 2, 13);</div> -<div> GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);</div> -<div> GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div> -<div> GEN_VXFORM(vsrv, 2, 28);</div> -<div>@@ -592,18 +592,18 @@ static void glue(gen_, NAME)(DisasContext *ctx) \</div> -<div> GEN_VXFORM_SAT(vaddubs, MO_UB, add, usadd, 0, 8);</div> -<div> GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \</div> -<div> vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div> -<div>-GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);</div> -<div>+GEN_VXFORM_SAT(vadduhs, MO_UW, add, usadd, 0, 9);</div> -<div> GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vmul10euq, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);</div> -<div> GEN_VXFORM_SAT(vaddsbs, MO_UB, add, ssadd, 0, 12);</div> -<div>-GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);</div> -<div>+GEN_VXFORM_SAT(vaddshs, MO_UW, add, ssadd, 0, 13);</div> -<div> GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);</div> -<div> GEN_VXFORM_SAT(vsububs, MO_UB, sub, ussub, 0, 24);</div> -<div>-GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);</div> -<div>+GEN_VXFORM_SAT(vsubuhs, MO_UW, sub, ussub, 0, 25);</div> -<div> GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);</div> -<div> GEN_VXFORM_SAT(vsubsbs, MO_UB, sub, sssub, 0, 28);</div> -<div>-GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);</div> -<div>+GEN_VXFORM_SAT(vsubshs, MO_UW, sub, sssub, 0, 29);</div> -<div> GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);</div> -<div> GEN_VXFORM(vadduqm, 0, 4);</div> -<div> GEN_VXFORM(vaddcuq, 0, 5);</div> -<div>@@ -913,7 +913,7 @@ static void glue(gen_, name)(DisasContext *ctx) \</div> -<div> }</div> -<div> </div> -<div> GEN_VXFORM_VSPLT(vspltb, MO_UB, 6, 8);</div> -<div>-GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);</div> -<div>+GEN_VXFORM_VSPLT(vsplth, MO_UW, 6, 9);</div> -<div> GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);</div> -<div> GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);</div> -<div> GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);</div> -<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div> -<div>index bb424c8..65da6b3 100644</div> -<div>--- a/target/s390x/translate_vx.inc.c</div> -<div>+++ b/target/s390x/translate_vx.inc.c</div> -<div>@@ -47,7 +47,7 @@</div> -<div> #define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)</div> -<div> </div> -<div> #define ES_8 MO_UB</div> -<div>-#define ES_16 MO_16</div> -<div>+#define ES_16 MO_UW</div> -<div> #define ES_32 MO_32</div> -<div> #define ES_64 MO_64</div> -<div> #define ES_128 4</div> -<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div> -<div>index b813054..28e1b1d 100644</div> -<div>--- a/target/s390x/vec.h</div> -<div>+++ b/target/s390x/vec.h</div> -<div>@@ -78,7 +78,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div> -<div> switch (es) {</div> -<div> case MO_UB:</div> -<div> return s390_vec_read_element8(v, enr);</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> return s390_vec_read_element16(v, enr);</div> -<div> case MO_32:</div> -<div> return s390_vec_read_element32(v, enr);</div> -<div>@@ -124,7 +124,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div> -<div> case MO_UB:</div> -<div> s390_vec_write_element8(v, enr, data);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> s390_vec_write_element16(v, enr, data);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div> -<div>index e4e0845..3d90c4b 100644</div> -<div>--- a/tcg/aarch64/tcg-target.inc.c</div> -<div>+++ b/tcg/aarch64/tcg-target.inc.c</div> -<div>@@ -430,20 +430,20 @@ typedef enum {</div> -<div> /* Load/store register. Described here as 3.3.12, but the helper</div> -<div> that emits them can transform to 3.3.10 or 3.3.13. */</div> -<div> I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div> -<div>- I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,</div> -<div>+ I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_UW << 30,</div> -<div> I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,</div> -<div> I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div> -<div> </div> -<div> I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div> -<div>- I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,</div> -<div>+ I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_UW << 30,</div> -<div> I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,</div> -<div> I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div> -<div> </div> -<div> I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div> -<div>- I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,</div> -<div>+ I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_UW << 30,</div> -<div> </div> -<div> I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_UB << 30,</div> -<div>- I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,</div> -<div>+ I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_UW << 30,</div> -<div> I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,</div> -<div> </div> -<div> I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,</div> -<div>@@ -870,7 +870,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div> -<div> </div> -<div> /*</div> -<div> * Test all bytes 0x00 or 0xff second. This can match cases that</div> -<div>- * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.</div> -<div>+ * might otherwise take 2 or 3 insns for MO_UW or MO_32 below.</div> -<div> */</div> -<div> for (i = imm8 = 0; i < 8; i++) {</div> -<div> uint8_t byte = v64 >> (i * 8);</div> -<div>@@ -889,7 +889,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div> -<div> * cannot find an expansion there's no point checking a larger</div> -<div> * width because we already know by replication it cannot match.</div> -<div> */</div> -<div>- if (v64 == dup_const(MO_16, v64)) {</div> -<div>+ if (v64 == dup_const(MO_UW, v64)) {</div> -<div> uint16_t v16 = v64;</div> -<div> </div> -<div> if (is_shimm16(v16, &cmode, &imm8)) {</div> -<div>@@ -1733,7 +1733,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div> -<div> if (bswap) {</div> -<div> tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);</div> -<div> tcg_out_rev16(s, data_r, data_r);</div> -<div>- tcg_out_sxt(s, ext, MO_16, data_r, data_r);</div> -<div>+ tcg_out_sxt(s, ext, MO_UW, data_r, data_r);</div> -<div> } else {</div> -<div> tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),</div> -<div> data_r, addr_r, otype, off_r);</div> -<div>@@ -1775,7 +1775,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div> -<div> case MO_UB:</div> -<div> tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (bswap && data_r != TCG_REG_XZR) {</div> -<div> tcg_out_rev16(s, TCG_REG_TMP, data_r);</div> -<div> data_r = TCG_REG_TMP;</div> -<div>@@ -2190,7 +2190,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div> -<div> break;</div> -<div> case INDEX_op_ext16s_i64:</div> -<div> case INDEX_op_ext16s_i32:</div> -<div>- tcg_out_sxt(s, ext, MO_16, a0, a1);</div> -<div>+ tcg_out_sxt(s, ext, MO_UW, a0, a1);</div> -<div> break;</div> -<div> case INDEX_op_ext_i32_i64:</div> -<div> case INDEX_op_ext32s_i64:</div> -<div>@@ -2202,7 +2202,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div> -<div> break;</div> -<div> case INDEX_op_ext16u_i64:</div> -<div> case INDEX_op_ext16u_i32:</div> -<div>- tcg_out_uxt(s, MO_16, a0, a1);</div> -<div>+ tcg_out_uxt(s, MO_UW, a0, a1);</div> -<div> break;</div> -<div> case INDEX_op_extu_i32_i64:</div> -<div> case INDEX_op_ext32u_i64:</div> -<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div> -<div>index 542ffa8..0bd400e 100644</div> -<div>--- a/tcg/arm/tcg-target.inc.c</div> -<div>+++ b/tcg/arm/tcg-target.inc.c</div> -<div>@@ -1432,7 +1432,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> case MO_UB:</div> -<div> argreg = tcg_out_arg_reg8(s, argreg, datalo);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> argreg = tcg_out_arg_reg16(s, argreg, datalo);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1624,7 +1624,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div> -<div> case MO_UB:</div> -<div> tcg_out_st8_r(s, cond, datalo, addrlo, addend);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (bswap) {</div> -<div> tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo);</div> -<div> tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);</div> -<div>@@ -1669,7 +1669,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div> -<div> case MO_UB:</div> -<div> tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (bswap) {</div> -<div> tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo);</div> -<div> tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);</div> -<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div> -<div>index 0d68ba4..31c3664 100644</div> -<div>--- a/tcg/i386/tcg-target.inc.c</div> -<div>+++ b/tcg/i386/tcg-target.inc.c</div> -<div>@@ -893,7 +893,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a);</div> -<div> a = r;</div> -<div> /* FALLTHRU */</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a);</div> -<div> a = r;</div> -<div> /* FALLTHRU */</div> -<div>@@ -927,7 +927,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> case MO_32:</div> -<div> tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset);</div> -<div> tcg_out8(s, 0); /* imm8 */</div> -<div> tcg_out_dup_vec(s, type, vece, r, r);</div> -<div>@@ -2164,7 +2164,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div> -<div> tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,</div> -<div> datalo, base, index, 0, ofs);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> if (bswap) {</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);</div> -<div> tcg_out_rolw_8(s, scratch);</div> -<div>@@ -2747,15 +2747,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div> -<div> OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2</div> -<div> };</div> -<div> static int const shlv_insn[4] = {</div> -<div>- /* TODO: AVX512 adds support for MO_16. */</div> -<div>+ /* TODO: AVX512 adds support for MO_UW. */</div> -<div> OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ</div> -<div> };</div> -<div> static int const shrv_insn[4] = {</div> -<div>- /* TODO: AVX512 adds support for MO_16. */</div> -<div>+ /* TODO: AVX512 adds support for MO_UW. */</div> -<div> OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ</div> -<div> };</div> -<div> static int const sarv_insn[4] = {</div> -<div>- /* TODO: AVX512 adds support for MO_16, MO_64. */</div> -<div>+ /* TODO: AVX512 adds support for MO_UW, MO_64. */</div> -<div> OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2</div> -<div> };</div> -<div> static int const shls_insn[4] = {</div> -<div>@@ -2925,7 +2925,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div> -<div> sub = args[3];</div> -<div> goto gen_simd_imm8;</div> -<div> case INDEX_op_x86_blend_vec:</div> -<div>- if (vece == MO_16) {</div> -<div>+ if (vece == MO_UW) {</div> -<div> insn = OPC_PBLENDW;</div> -<div> } else if (vece == MO_32) {</div> -<div> insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);</div> -<div>@@ -3290,9 +3290,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> </div> -<div> case INDEX_op_shls_vec:</div> -<div> case INDEX_op_shrs_vec:</div> -<div>- return vece >= MO_16;</div> -<div>+ return vece >= MO_UW;</div> -<div> case INDEX_op_sars_vec:</div> -<div>- return vece >= MO_16 && vece <= MO_32;</div> -<div>+ return vece >= MO_UW && vece <= MO_32;</div> -<div> </div> -<div> case INDEX_op_shlv_vec:</div> -<div> case INDEX_op_shrv_vec:</div> -<div>@@ -3314,7 +3314,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> case INDEX_op_usadd_vec:</div> -<div> case INDEX_op_sssub_vec:</div> -<div> case INDEX_op_ussub_vec:</div> -<div>- return vece <= MO_16;</div> -<div>+ return vece <= MO_UW;</div> -<div> case INDEX_op_smin_vec:</div> -<div> case INDEX_op_smax_vec:</div> -<div> case INDEX_op_umin_vec:</div> -<div>@@ -3352,13 +3352,13 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div> -<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div> -<div> </div> -<div> if (shr) {</div> -<div>- tcg_gen_shri_vec(MO_16, t1, t1, imm + 8);</div> -<div>- tcg_gen_shri_vec(MO_16, t2, t2, imm + 8);</div> -<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, imm + 8);</div> -<div>+ tcg_gen_shri_vec(MO_UW, t2, t2, imm + 8);</div> -<div> } else {</div> -<div>- tcg_gen_shli_vec(MO_16, t1, t1, imm + 8);</div> -<div>- tcg_gen_shli_vec(MO_16, t2, t2, imm + 8);</div> -<div>- tcg_gen_shri_vec(MO_16, t1, t1, 8);</div> -<div>- tcg_gen_shri_vec(MO_16, t2, t2, 8);</div> -<div>+ tcg_gen_shli_vec(MO_UW, t1, t1, imm + 8);</div> -<div>+ tcg_gen_shli_vec(MO_UW, t2, t2, imm + 8);</div> -<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, 8);</div> -<div>+ tcg_gen_shri_vec(MO_UW, t2, t2, 8);</div> -<div> }</div> -<div> </div> -<div> vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div> -<div>@@ -3381,8 +3381,8 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div> -<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div> -<div> vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div> -<div>- tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);</div> -<div>- tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);</div> -<div>+ tcg_gen_sari_vec(MO_UW, t1, t1, imm + 8);</div> -<div>+ tcg_gen_sari_vec(MO_UW, t2, t2, imm + 8);</div> -<div> vec_gen_3(INDEX_op_x86_packss_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));</div> -<div> tcg_temp_free_vec(t1);</div> -<div>@@ -3446,8 +3446,8 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div> -<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));</div> -<div> vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_UB,</div> -<div> tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));</div> -<div>- tcg_gen_mul_vec(MO_16, t1, t1, t2);</div> -<div>- tcg_gen_shri_vec(MO_16, t1, t1, 8);</div> -<div>+ tcg_gen_mul_vec(MO_UW, t1, t1, t2);</div> -<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, 8);</div> -<div> vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_UB,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1));</div> -<div> tcg_temp_free_vec(t1);</div> -<div>@@ -3469,10 +3469,10 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div> -<div> tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));</div> -<div> vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));</div> -<div>- tcg_gen_mul_vec(MO_16, t1, t1, t2);</div> -<div>- tcg_gen_mul_vec(MO_16, t3, t3, t4);</div> -<div>- tcg_gen_shri_vec(MO_16, t1, t1, 8);</div> -<div>- tcg_gen_shri_vec(MO_16, t3, t3, 8);</div> -<div>+ tcg_gen_mul_vec(MO_UW, t1, t1, t2);</div> -<div>+ tcg_gen_mul_vec(MO_UW, t3, t3, t4);</div> -<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, 8);</div> -<div>+ tcg_gen_shri_vec(MO_UW, t3, t3, 8);</div> -<div> vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3));</div> -<div> tcg_temp_free_vec(t1);</div> -<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div> -<div>index c6d13ea..1780cb1 100644</div> -<div>--- a/tcg/mips/tcg-target.inc.c</div> -<div>+++ b/tcg/mips/tcg-target.inc.c</div> -<div>@@ -1383,7 +1383,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> case MO_UB:</div> -<div> i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -1570,12 +1570,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> tcg_out_opc_imm(s, OPC_SB, lo, base, 0);</div> -<div> break;</div> -<div> </div> -<div>- case MO_16 | MO_BSWAP:</div> -<div>+ case MO_UW | MO_BSWAP:</div> -<div> tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);</div> -<div> tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);</div> -<div> lo = TCG_TMP1;</div> -<div> /* FALLTHRU */</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_out_opc_imm(s, OPC_SH, lo, base, 0);</div> -<div> break;</div> -<div> </div> -<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div> -<div>index 9c60c0f..20bc19d 100644</div> -<div>--- a/tcg/riscv/tcg-target.inc.c</div> -<div>+++ b/tcg/riscv/tcg-target.inc.c</div> -<div>@@ -1104,7 +1104,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> case MO_UB:</div> -<div> tcg_out_ext8u(s, a2, a2);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_out_ext16u(s, a2, a2);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -1219,7 +1219,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> case MO_UB:</div> -<div> tcg_out_opc_store(s, OPC_SB, base, lo, 0);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_out_opc_store(s, OPC_SH, base, lo, 0);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div> -<div>index 479ee2e..85550b5 100644</div> -<div>--- a/tcg/sparc/tcg-target.inc.c</div> -<div>+++ b/tcg/sparc/tcg-target.inc.c</div> -<div>@@ -885,7 +885,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div> -<div> case MO_UB:</div> -<div> tcg_out_arithi(s, r, r, 0xff, ARITH_AND);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_out_arithi(s, r, r, 16, SHIFT_SLL);</div> -<div> tcg_out_arithi(s, r, r, 16, SHIFT_SRL);</div> -<div> break;</div> -<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div> -<div>index 9658c36..da409f5 100644</div> -<div>--- a/tcg/tcg-op-gvec.c</div> -<div>+++ b/tcg/tcg-op-gvec.c</div> -<div>@@ -308,7 +308,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div> -<div> switch (vece) {</div> -<div> case MO_UB:</div> -<div> return 0x0101010101010101ull * (uint8_t)c;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> return 0x0001000100010001ull * (uint16_t)c;</div> -<div> case MO_32:</div> -<div> return 0x0000000100000001ull * (uint32_t)c;</div> -<div>@@ -327,7 +327,7 @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div> -<div> tcg_gen_ext8u_i32(out, in);</div> -<div> tcg_gen_muli_i32(out, out, 0x01010101);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_deposit_i32(out, in, in, 16, 16);</div> -<div> break;</div> -<div> case MO_32:</div> -<div>@@ -345,7 +345,7 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div> -<div> tcg_gen_ext8u_i64(out, in);</div> -<div> tcg_gen_muli_i64(out, out, 0x0101010101010101ull);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_ext16u_i64(out, in);</div> -<div> tcg_gen_muli_i64(out, out, 0x0001000100010001ull);</div> -<div> break;</div> -<div>@@ -558,7 +558,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> tcg_gen_extrl_i64_i32(t_32, in_64);</div> -<div> } else if (vece == MO_UB) {</div> -<div> tcg_gen_movi_i32(t_32, in_c & 0xff);</div> -<div>- } else if (vece == MO_16) {</div> -<div>+ } else if (vece == MO_UW) {</div> -<div> tcg_gen_movi_i32(t_32, in_c & 0xffff);</div> -<div> } else {</div> -<div> tcg_gen_movi_i32(t_32, in_c);</div> -<div>@@ -1459,7 +1459,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> case MO_UB:</div> -<div> tcg_gen_ld8u_i32(in, cpu_env, aofs);</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_ld16u_i32(in, cpu_env, aofs);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -1526,7 +1526,7 @@ void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,</div> -<div> uint32_t maxsz, uint16_t x)</div> -<div> {</div> -<div> check_size_align(oprsz, maxsz, dofs);</div> -<div>- do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div>+ do_dup(MO_UW, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,</div> -<div>@@ -1579,7 +1579,7 @@ void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div> -<div> </div> -<div> void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div> -<div> {</div> -<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));</div> -<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UW, 0x8000));</div> -<div> gen_addv_mask(d, a, b, m);</div> -<div> tcg_temp_free_i64(m);</div> -<div> }</div> -<div>@@ -1613,7 +1613,7 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_add16,</div> -<div> .opt_opc = vecop_list_add,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_add_i32,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_add32,</div> -<div>@@ -1644,7 +1644,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_adds16,</div> -<div> .opt_opc = vecop_list_add,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_add_i32,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_adds32,</div> -<div>@@ -1685,7 +1685,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_subs16,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_sub_i32,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_subs32,</div> -<div>@@ -1732,7 +1732,7 @@ void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div> -<div> </div> -<div> void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div> -<div> {</div> -<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));</div> -<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UW, 0x8000));</div> -<div> gen_subv_mask(d, a, b, m);</div> -<div> tcg_temp_free_i64(m);</div> -<div> }</div> -<div>@@ -1764,7 +1764,7 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_sub16,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_sub_i32,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_sub32,</div> -<div>@@ -1795,7 +1795,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_mul16,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_mul_i32,</div> -<div> .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_mul32,</div> -<div>@@ -1824,7 +1824,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_muls16,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_mul_i32,</div> -<div> .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_muls32,</div> -<div>@@ -1862,7 +1862,7 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_ssadd_vec,</div> -<div> .fno = gen_helper_gvec_ssadd16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fniv = tcg_gen_ssadd_vec,</div> -<div> .fno = gen_helper_gvec_ssadd32,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1888,7 +1888,7 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_sssub_vec,</div> -<div> .fno = gen_helper_gvec_sssub16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fniv = tcg_gen_sssub_vec,</div> -<div> .fno = gen_helper_gvec_sssub32,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1930,7 +1930,7 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_usadd_vec,</div> -<div> .fno = gen_helper_gvec_usadd16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_usadd_i32,</div> -<div> .fniv = tcg_gen_usadd_vec,</div> -<div> .fno = gen_helper_gvec_usadd32,</div> -<div>@@ -1974,7 +1974,7 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_ussub_vec,</div> -<div> .fno = gen_helper_gvec_ussub16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_ussub_i32,</div> -<div> .fniv = tcg_gen_ussub_vec,</div> -<div> .fno = gen_helper_gvec_ussub32,</div> -<div>@@ -2002,7 +2002,7 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_smin_vec,</div> -<div> .fno = gen_helper_gvec_smin16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_smin_i32,</div> -<div> .fniv = tcg_gen_smin_vec,</div> -<div> .fno = gen_helper_gvec_smin32,</div> -<div>@@ -2030,7 +2030,7 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_umin_vec,</div> -<div> .fno = gen_helper_gvec_umin16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_umin_i32,</div> -<div> .fniv = tcg_gen_umin_vec,</div> -<div> .fno = gen_helper_gvec_umin32,</div> -<div>@@ -2058,7 +2058,7 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_smax_vec,</div> -<div> .fno = gen_helper_gvec_smax16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_smax_i32,</div> -<div> .fniv = tcg_gen_smax_vec,</div> -<div> .fno = gen_helper_gvec_smax32,</div> -<div>@@ -2086,7 +2086,7 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_umax_vec,</div> -<div> .fno = gen_helper_gvec_umax16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_umax_i32,</div> -<div> .fniv = tcg_gen_umax_vec,</div> -<div> .fno = gen_helper_gvec_umax32,</div> -<div>@@ -2127,7 +2127,7 @@ void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)</div> -<div> </div> -<div> void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b)</div> -<div> {</div> -<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));</div> -<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UW, 0x8000));</div> -<div> gen_negv_mask(d, b, m);</div> -<div> tcg_temp_free_i64(m);</div> -<div> }</div> -<div>@@ -2160,7 +2160,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_neg_vec,</div> -<div> .fno = gen_helper_gvec_neg16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_neg_i32,</div> -<div> .fniv = tcg_gen_neg_vec,</div> -<div> .fno = gen_helper_gvec_neg32,</div> -<div>@@ -2206,7 +2206,7 @@ static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b)</div> -<div> </div> -<div> static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b)</div> -<div> {</div> -<div>- gen_absv_mask(d, b, MO_16);</div> -<div>+ gen_absv_mask(d, b, MO_UW);</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div>@@ -2223,7 +2223,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_abs_vec,</div> -<div> .fno = gen_helper_gvec_abs16,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_abs_i32,</div> -<div> .fniv = tcg_gen_abs_vec,</div> -<div> .fno = gen_helper_gvec_abs32,</div> -<div>@@ -2461,7 +2461,7 @@ void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> </div> -<div> void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_16, 0xffff << c);</div> -<div>+ uint64_t mask = dup_const(MO_UW, 0xffff << c);</div> -<div> tcg_gen_shli_i64(d, a, c);</div> -<div> tcg_gen_andi_i64(d, d, mask);</div> -<div> }</div> -<div>@@ -2480,7 +2480,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shli_vec,</div> -<div> .fno = gen_helper_gvec_shl16i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_shli_i32,</div> -<div> .fniv = tcg_gen_shli_vec,</div> -<div> .fno = gen_helper_gvec_shl32i,</div> -<div>@@ -2512,7 +2512,7 @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> </div> -<div> void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> {</div> -<div>- uint64_t mask = dup_const(MO_16, 0xffff >> c);</div> -<div>+ uint64_t mask = dup_const(MO_UW, 0xffff >> c);</div> -<div> tcg_gen_shri_i64(d, a, c);</div> -<div> tcg_gen_andi_i64(d, d, mask);</div> -<div> }</div> -<div>@@ -2531,7 +2531,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shri_vec,</div> -<div> .fno = gen_helper_gvec_shr16i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_shri_i32,</div> -<div> .fniv = tcg_gen_shri_vec,</div> -<div> .fno = gen_helper_gvec_shr32i,</div> -<div>@@ -2570,8 +2570,8 @@ void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> </div> -<div> void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div> -<div> {</div> -<div>- uint64_t s_mask = dup_const(MO_16, 0x8000 >> c);</div> -<div>- uint64_t c_mask = dup_const(MO_16, 0xffff >> c);</div> -<div>+ uint64_t s_mask = dup_const(MO_UW, 0x8000 >> c);</div> -<div>+ uint64_t c_mask = dup_const(MO_UW, 0xffff >> c);</div> -<div> TCGv_i64 s = tcg_temp_new_i64();</div> -<div> </div> -<div> tcg_gen_shri_i64(d, a, c);</div> -<div>@@ -2596,7 +2596,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sari_vec,</div> -<div> .fno = gen_helper_gvec_sar16i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_sari_i32,</div> -<div> .fniv = tcg_gen_sari_vec,</div> -<div> .fno = gen_helper_gvec_sar32i,</div> -<div>@@ -2884,7 +2884,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_shlv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shl16v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_shl_mod_i32,</div> -<div> .fniv = tcg_gen_shlv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shl32v,</div> -<div>@@ -2947,7 +2947,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_shrv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shr16v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_shr_mod_i32,</div> -<div> .fniv = tcg_gen_shrv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shr32v,</div> -<div>@@ -3010,7 +3010,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_sarv_mod_vec,</div> -<div> .fno = gen_helper_gvec_sar16v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_16 },</div> -<div>+ .vece = MO_UW },</div> -<div> { .fni4 = tcg_gen_sar_mod_i32,</div> -<div> .fniv = tcg_gen_sarv_mod_vec,</div> -<div> .fno = gen_helper_gvec_sar32v,</div> -<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div> -<div>index d7ffc9e..b0a4d98 100644</div> -<div>--- a/tcg/tcg-op-vec.c</div> -<div>+++ b/tcg/tcg-op-vec.c</div> -<div>@@ -270,7 +270,7 @@ void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)</div> -<div> </div> -<div> void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)</div> -<div> {</div> -<div>- do_dupi_vec(r, MO_REG, dup_const(MO_16, a));</div> -<div>+ do_dupi_vec(r, MO_REG, dup_const(MO_UW, a));</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)</div> -<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div> -<div>index 61eda33..21d448c 100644</div> -<div>--- a/tcg/tcg-op.c</div> -<div>+++ b/tcg/tcg-op.c</div> -<div>@@ -2723,7 +2723,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div> -<div> case MO_UB:</div> -<div> op &= ~MO_BSWAP;</div> -<div> break;</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> break;</div> -<div> case MO_32:</div> -<div> if (!is64) {</div> -<div>@@ -2810,7 +2810,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> </div> -<div> if ((orig_memop ^ memop) & MO_BSWAP) {</div> -<div> switch (orig_memop & MO_SIZE) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_bswap16_i32(val, val);</div> -<div> if (orig_memop & MO_SIGN) {</div> -<div> tcg_gen_ext16s_i32(val, val);</div> -<div>@@ -2837,7 +2837,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {</div> -<div> swap = tcg_temp_new_i32();</div> -<div> switch (memop & MO_SIZE) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_ext16u_i32(swap, val);</div> -<div> tcg_gen_bswap16_i32(swap, swap);</div> -<div> break;</div> -<div>@@ -2890,7 +2890,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> </div> -<div> if ((orig_memop ^ memop) & MO_BSWAP) {</div> -<div> switch (orig_memop & MO_SIZE) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_bswap16_i64(val, val);</div> -<div> if (orig_memop & MO_SIGN) {</div> -<div> tcg_gen_ext16s_i64(val, val);</div> -<div>@@ -2928,7 +2928,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {</div> -<div> swap = tcg_temp_new_i64();</div> -<div> switch (memop & MO_SIZE) {</div> -<div>- case MO_16:</div> -<div>+ case MO_UW:</div> -<div> tcg_gen_ext16u_i64(swap, val);</div> -<div> tcg_gen_bswap16_i64(swap, swap);</div> -<div> break;</div> -<div>@@ -3025,8 +3025,8 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64);</div> -<div> </div> -<div> static void * const table_cmpxchg[16] = {</div> -<div> [MO_UB] = gen_helper_atomic_cmpxchgb,</div> -<div>- [MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div> -<div>- [MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div> -<div>+ [MO_UW | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div> -<div>+ [MO_UW | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div> -<div> [MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div> -<div> [MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div> -<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div> -<div>@@ -3249,8 +3249,8 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div> -<div> #define GEN_ATOMIC_HELPER(NAME, OP, NEW) \</div> -<div> static void * const table_##NAME[16] = { \</div> -<div> [MO_UB] = gen_helper_atomic_##NAME##b, \</div> -<div>- [MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \</div> -<div>- [MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \</div> -<div>+ [MO_UW | MO_LE] = gen_helper_atomic_##NAME##w_le, \</div> -<div>+ [MO_UW | MO_BE] = gen_helper_atomic_##NAME##w_be, \</div> -<div> [MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \</div> -<div> [MO_32 | MO_BE] = gen_helper_atomic_##NAME##l_be, \</div> -<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \</div> -<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div> -<div>index 5636d6b..a378887 100644</div> -<div>--- a/tcg/tcg.h</div> -<div>+++ b/tcg/tcg.h</div> -<div>@@ -1303,7 +1303,7 @@ uint64_t dup_const(unsigned vece, uint64_t c);</div> -<div> #define dup_const(VECE, C) \</div> -<div> (__builtin_constant_p(VECE) \</div> -<div> ? ((VECE) == MO_UB ? 0x0101010101010101ull * (uint8_t)(C) \</div> -<div>- : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \</div> -<div>+ : (VECE) == MO_UW ? 0x0001000100010001ull * (uint16_t)(C) \</div> -<div> : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \</div> -<div> : dup_const(VECE, C)) \</div> -<div> : dup_const(VECE, C))</div> -<div>-- </div> -<div>1.8.3.1</div> -<div><br> -<br> -</div> -<p><br> -</p> -</body> -</html> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index e54d0ae..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/html; charset="iso-8859-1" -Content-Transfer-Encoding: quoted-printable diff --git a/a/content_digest b/N1/content_digest index 02cce66..9415335 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,34 +1,34 @@ "ref\0e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net\0" "From\0<tony.nguyen@bt.com>\0" - "Subject\0[Qemu-riscv] [Qemu-devel] [PATCH v2 02/20] tcg: Replace MO_16 with MO_UW alias\0" + "Subject\0[Qemu-devel] [PATCH v2 02/20] tcg: Replace MO_16 with MO_UW alias\0" "Date\0Mon, 22 Jul 2019 15:40:17 +0000\0" "To\0<qemu-devel@nongnu.org>\0" - "Cc\0<peter.maydell@linaro.org>" - <walling@linux.ibm.com> - <david@redhat.com> - <palmer@sifive.com> - <mark.cave-ayland@ilande.co.uk> - <Alistair.Francis@wdc.com> - <arikalo@wavecomp.com> - <mst@redhat.com> - <pasic@linux.ibm.com> - <borntraeger@de.ibm.com> - <rth@twiddle.net> - <atar4qemu@gmail.com> - <ehabkost@redhat.com> - <sw@weilnetz.de> - <alex.williamson@redhat.com> - <qemu-arm@nongnu.org> - <david@gibson.dropbear.id.au> - <qemu-riscv@nongnu.org> - <cohuck@redhat.com> - <claudio.fontana@huawei.com> - <qemu-s390x@nongnu.org> - <qemu-ppc@nongnu.org> - <amarkovic@wavecomp.com> - <pbonzini@redhat.com> - " <aurelien@aurel32.net>\0" - "\01:1\0" + "Cc\0peter.maydell@linaro.org" + walling@linux.ibm.com + mst@redhat.com + palmer@sifive.com + mark.cave-ayland@ilande.co.uk + Alistair.Francis@wdc.com + arikalo@wavecomp.com + david@redhat.com + pasic@linux.ibm.com + borntraeger@de.ibm.com + rth@twiddle.net + atar4qemu@gmail.com + ehabkost@redhat.com + sw@weilnetz.de + qemu-s390x@nongnu.org + qemu-arm@nongnu.org + david@gibson.dropbear.id.au + qemu-riscv@nongnu.org + cohuck@redhat.com + claudio.fontana@huawei.com + alex.williamson@redhat.com + qemu-ppc@nongnu.org + amarkovic@wavecomp.com + pbonzini@redhat.com + " aurelien@aurel32.net\0" + "\00:1\0" "b\0" "Preparation for splitting MO_16 out from TCGMemOp into new accelerator\n" "independent MemOp.\n" @@ -2479,2472 +2479,5 @@ " : dup_const(VECE, C))\n" "--\n" 1.8.3.1 - "\01:2\0" - "b\0" - "<html>\r\n" - "<head>\r\n" - "<meta http-equiv=\"Content-Type\" content=\"text/html; charset=iso-8859-1\">\r\n" - "<style type=\"text/css\" style=\"display:none\"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style>\r\n" - "</head>\r\n" - "<body dir=\"ltr\" style=\"font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;\">\r\n" - "<div><span style=\"font-size: 12pt;\">Preparation for splitting MO_16 out from TCGMemOp into new accelerator</span></div>\r\n" - "<div>independent MemOp.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>As MO_16 will be a value of MemOp, existing TCGMemOp comparisons and</div>\r\n" - "<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div>\r\n" - "<div>---</div>\r\n" - "<div> target/arm/sve_helper.c | 4 +-</div>\r\n" - "<div> target/arm/translate-a64.c | 90 ++++++++--------</div>\r\n" - "<div> target/arm/translate-sve.c | 40 ++++----</div>\r\n" - "<div> target/arm/translate-vfp.inc.c | 2 +-</div>\r\n" - "<div> target/arm/translate.c | 32 +++---</div>\r\n" - "<div> target/i386/translate.c | 200 ++++++++++++++++++------------------</div>\r\n" - "<div> target/mips/translate.c | 2 +-</div>\r\n" - "<div> target/ppc/translate/vmx-impl.inc.c | 28 ++---</div>\r\n" - "<div> target/s390x/translate_vx.inc.c | 2 +-</div>\r\n" - "<div> target/s390x/vec.h | 4 +-</div>\r\n" - "<div> tcg/aarch64/tcg-target.inc.c | 20 ++--</div>\r\n" - "<div> tcg/arm/tcg-target.inc.c | 6 +-</div>\r\n" - "<div> tcg/i386/tcg-target.inc.c | 48 ++++-----</div>\r\n" - "<div> tcg/mips/tcg-target.inc.c | 6 +-</div>\r\n" - "<div> tcg/riscv/tcg-target.inc.c | 4 +-</div>\r\n" - "<div> tcg/sparc/tcg-target.inc.c | 2 +-</div>\r\n" - "<div> tcg/tcg-op-gvec.c | 72 ++++++-------</div>\r\n" - "<div> tcg/tcg-op-vec.c | 2 +-</div>\r\n" - "<div> tcg/tcg-op.c | 18 ++--</div>\r\n" - "<div> tcg/tcg.h | 2 +-</div>\r\n" - "<div> 20 files changed, 292 insertions(+), 292 deletions(-)</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div>\r\n" - "<div>index 4c7e11f..f6bef3d 100644</div>\r\n" - "<div>--- a/target/arm/sve_helper.c</div>\r\n" - "<div>+++ b/target/arm/sve_helper.c</div>\r\n" - "<div>@@ -1546,7 +1546,7 @@ void HELPER(sve_cpy_m_h)(void *vd, void *vn, void *vg,</div>\r\n" - "<div> uint64_t *d = vd, *n = vn;</div>\r\n" - "<div> uint8_t *pg = vg;</div>\r\n" - "<div> </div>\r\n" - "<div>- mm = dup_const(MO_16, mm);</div>\r\n" - "<div>+ mm = dup_const(MO_UW, mm);</div>\r\n" - "<div> for (i = 0; i < opr_sz; i += 1) {</div>\r\n" - "<div> uint64_t nn = n[i];</div>\r\n" - "<div> uint64_t pp = expand_pred_h(pg[H1(i)]);</div>\r\n" - "<div>@@ -1600,7 +1600,7 @@ void HELPER(sve_cpy_z_h)(void *vd, void *vg, uint64_t val, uint32_t desc)</div>\r\n" - "<div> uint64_t *d = vd;</div>\r\n" - "<div> uint8_t *pg = vg;</div>\r\n" - "<div> </div>\r\n" - "<div>- val = dup_const(MO_16, val);</div>\r\n" - "<div>+ val = dup_const(MO_UW, val);</div>\r\n" - "<div> for (i = 0; i < opr_sz; i += 1) {</div>\r\n" - "<div> d[i] = val & expand_pred_h(pg[H1(i)]);</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div>\r\n" - "<div>index f840b43..3acfccb 100644</div>\r\n" - "<div>--- a/target/arm/translate-a64.c</div>\r\n" - "<div>+++ b/target/arm/translate-a64.c</div>\r\n" - "<div>@@ -492,7 +492,7 @@ static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 v = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));</div>\r\n" - "<div>+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_UW));</div>\r\n" - "<div> return v;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -996,7 +996,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1005,7 +1005,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_SB:</div>\r\n" - "<div> tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16|MO_SIGN:</div>\r\n" - "<div>+ case MO_SW:</div>\r\n" - "<div> tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32|MO_SIGN:</div>\r\n" - "<div>@@ -1028,13 +1028,13 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_SB:</div>\r\n" - "<div> tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16|MO_SIGN:</div>\r\n" - "<div>+ case MO_SW:</div>\r\n" - "<div> tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1055,7 +1055,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1077,7 +1077,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -5269,7 +5269,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div>\r\n" - "<div> bool cmp_with_zero, bool signal_all_nans)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 tcg_flags = tcg_temp_new_i64();</div>\r\n" - "<div>- TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);</div>\r\n" - "<div>+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> if (size == MO_64) {</div>\r\n" - "<div> TCGv_i64 tcg_vn, tcg_vm;</div>\r\n" - "<div>@@ -5306,7 +5306,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div>\r\n" - "<div> gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (signal_all_nans) {</div>\r\n" - "<div> gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -5360,7 +5360,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_64;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> if (dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -5411,7 +5411,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_64;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> if (dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -5477,7 +5477,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> sz = MO_64;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div>- sz = MO_16;</div>\r\n" - "<div>+ sz = MO_UW;</div>\r\n" - "<div> if (dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6282,7 +6282,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> sz = MO_64;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div>- sz = MO_16;</div>\r\n" - "<div>+ sz = MO_UW;</div>\r\n" - "<div> if (dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6593,7 +6593,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div> /* 16 bit */</div>\r\n" - "<div>- tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));</div>\r\n" - "<div>+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_UW));</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div>@@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,</div>\r\n" - "<div> {</div>\r\n" - "<div> if (esize == size) {</div>\r\n" - "<div> int element;</div>\r\n" - "<div>- TCGMemOp msize = esize == 16 ? MO_16 : MO_32;</div>\r\n" - "<div>+ TCGMemOp msize = esize == 16 ? MO_UW : MO_32;</div>\r\n" - "<div> TCGv_i32 tcg_elem;</div>\r\n" - "<div> </div>\r\n" - "<div> /* We should have one register left here */</div>\r\n" - "<div>@@ -7204,7 +7204,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> * Note that correct NaN propagation requires that we do these</div>\r\n" - "<div> * operations in exactly the order specified by the pseudocode.</div>\r\n" - "<div> */</div>\r\n" - "<div>- TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);</div>\r\n" - "<div>+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_UW);</div>\r\n" - "<div> int fpopcode = opcode | is_min << 4 | is_u << 5;</div>\r\n" - "<div> int vmap = (1 << elements) - 1;</div>\r\n" - "<div> TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,</div>\r\n" - "<div>@@ -7591,7 +7591,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> } else {</div>\r\n" - "<div> if (o2) {</div>\r\n" - "<div> /* FMOV (vector, immediate) - half-precision */</div>\r\n" - "<div>- imm = vfp_expand_imm(MO_16, abcdefgh);</div>\r\n" - "<div>+ imm = vfp_expand_imm(MO_UW, abcdefgh);</div>\r\n" - "<div> /* now duplicate across the lanes */</div>\r\n" - "<div> imm = bitfield_replicate(imm, 16);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -7699,7 +7699,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div> size = extract32(size, 0, 1) ? MO_64 : MO_32;</div>\r\n" - "<div>@@ -7709,7 +7709,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- fpst = get_fpstatus_ptr(size == MO_16);</div>\r\n" - "<div>+ fpst = get_fpstatus_ptr(size == MO_UW);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div>@@ -7760,7 +7760,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> read_vec_element_i32(s, tcg_op1, rn, 0, size);</div>\r\n" - "<div> read_vec_element_i32(s, tcg_op2, rn, 1, size);</div>\r\n" - "<div> </div>\r\n" - "<div>- if (size == MO_16) {</div>\r\n" - "<div>+ if (size == MO_UW) {</div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0xc: /* FMAXNMP */</div>\r\n" - "<div> gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);</div>\r\n" - "<div>@@ -8222,7 +8222,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div>\r\n" - "<div> int elements, int is_signed,</div>\r\n" - "<div> int fracbits, int size)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);</div>\r\n" - "<div>+ TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_UW);</div>\r\n" - "<div> TCGv_i32 tcg_shift = NULL;</div>\r\n" - "<div> </div>\r\n" - "<div> TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);</div>\r\n" - "<div>@@ -8281,7 +8281,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (fracbits) {</div>\r\n" - "<div> if (is_signed) {</div>\r\n" - "<div> gen_helper_vfp_sltoh(tcg_float, tcg_int32,</div>\r\n" - "<div>@@ -8339,7 +8339,7 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> } else if (immh & 4) {</div>\r\n" - "<div> size = MO_32;</div>\r\n" - "<div> } else if (immh & 2) {</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> if (!dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -8384,7 +8384,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> } else if (immh & 0x4) {</div>\r\n" - "<div> size = MO_32;</div>\r\n" - "<div> } else if (immh & 0x2) {</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> if (!dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -8403,7 +8403,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> assert(!(is_scalar && is_q));</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));</div>\r\n" - "<div>- tcg_fpstatus = get_fpstatus_ptr(size == MO_16);</div>\r\n" - "<div>+ tcg_fpstatus = get_fpstatus_ptr(size == MO_UW);</div>\r\n" - "<div> gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);</div>\r\n" - "<div> fracbits = (16 << size) - immhb;</div>\r\n" - "<div> tcg_shift = tcg_const_i32(fracbits);</div>\r\n" - "<div>@@ -8429,7 +8429,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> int maxpass = is_scalar ? 1 : ((8 << is_q) >> size);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (is_u) {</div>\r\n" - "<div> fn = gen_helper_vfp_touhh;</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -9388,7 +9388,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- fpst = get_fpstatus_ptr(size == MO_16);</div>\r\n" - "<div>+ fpst = get_fpstatus_ptr(size == MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> if (is_double) {</div>\r\n" - "<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div>\r\n" - "<div>@@ -9440,7 +9440,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div>\r\n" - "<div> bool swap = false;</div>\r\n" - "<div> int pass, maxpasses;</div>\r\n" - "<div> </div>\r\n" - "<div>- if (size == MO_16) {</div>\r\n" - "<div>+ if (size == MO_UW) {</div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0x2e: /* FCMLT (zero) */</div>\r\n" - "<div> swap = true;</div>\r\n" - "<div>@@ -11422,8 +11422,8 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> int passreg = pass < (maxpass / 2) ? rn : rm;</div>\r\n" - "<div> int passelt = (pass << 1) & (maxpass - 1);</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_UW);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_UW);</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div> switch (fpopcode) {</div>\r\n" - "<div>@@ -11450,7 +11450,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < maxpass; pass++) {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_UW);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -11463,15 +11463,15 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i32 tcg_op2 = tcg_temp_new_i32();</div>\r\n" - "<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_UW);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (fpopcode) {</div>\r\n" - "<div> case 0x0: /* FMAXNM */</div>\r\n" - "<div> gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x1: /* FMLA */</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div>\r\n" - "<div> gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,</div>\r\n" - "<div> fpst);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -11496,7 +11496,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> case 0x9: /* FMLS */</div>\r\n" - "<div> /* As usual for ARM, separate negation for fused multiply-add */</div>\r\n" - "<div> tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div>\r\n" - "<div> gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,</div>\r\n" - "<div> fpst);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -11537,7 +11537,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op1);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op2);</div>\r\n" - "<div>@@ -11727,7 +11727,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div>\r\n" - "<div> for (pass = 0; pass < 4; pass++) {</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_UW);</div>\r\n" - "<div> gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],</div>\r\n" - "<div> fpst, ahp);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -11768,7 +11768,7 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> </div>\r\n" - "<div> read_vec_element(s, tcg_tmp, rn, i, grp_size);</div>\r\n" - "<div> switch (grp_size) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -12499,7 +12499,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> if (!fp_access_check(s)) {</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>- handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);</div>\r\n" - "<div>+ handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_UW);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -12508,7 +12508,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> case 0x2e: /* FCMLT (zero) */</div>\r\n" - "<div> case 0x6c: /* FCMGE (zero) */</div>\r\n" - "<div> case 0x6d: /* FCMLE (zero) */</div>\r\n" - "<div>- handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);</div>\r\n" - "<div>+ handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_UW, rn, rd);</div>\r\n" - "<div> return;</div>\r\n" - "<div> case 0x3d: /* FRECPE */</div>\r\n" - "<div> case 0x3f: /* FRECPX */</div>\r\n" - "<div>@@ -12668,7 +12668,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div>\r\n" - "<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op, rn, pass, MO_16);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op, rn, pass, MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (fpop) {</div>\r\n" - "<div> case 0x1a: /* FCVTNS */</div>\r\n" - "<div>@@ -12715,7 +12715,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_16);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i32(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op);</div>\r\n" - "<div>@@ -12839,7 +12839,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> /* is_fp, but we pass cpu_env not fp_status. */</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -12852,7 +12852,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> /* convert insn encoded size to TCGMemOp size */</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div> case 0: /* half-precision */</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> is_fp16 = true;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32: /* single precision */</div>\r\n" - "<div>@@ -12899,7 +12899,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> /* Given TCGMemOp size, adjust register and indexing. */</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> index = h << 2 | l << 1 | m;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div>\r\n" - "<div>index ec5fb11..2bc1bd1 100644</div>\r\n" - "<div>--- a/target/arm/translate-sve.c</div>\r\n" - "<div>+++ b/target/arm/translate-sve.c</div>\r\n" - "<div>@@ -1679,7 +1679,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div>\r\n" - "<div> tcg_temp_free_i32(t32);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> t32 = tcg_temp_new_i32();</div>\r\n" - "<div> tcg_gen_extrl_i64_i32(t32, val);</div>\r\n" - "<div> if (d) {</div>\r\n" - "<div>@@ -3314,7 +3314,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_sve_subri_h,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16,</div>\r\n" - "<div>+ .vece = MO_UW,</div>\r\n" - "<div> .scalar_first = true },</div>\r\n" - "<div> { .fni4 = tcg_gen_sub_i32,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div>@@ -3468,7 +3468,7 @@ static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)</div>\r\n" - "<div> </div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -3494,7 +3494,7 @@ static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)</div>\r\n" - "<div> </div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -3526,7 +3526,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));</div>\r\n" - "<div> tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));</div>\r\n" - "<div>- status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> fn(temp, t_zn, t_pg, status, t_desc);</div>\r\n" - "<div> tcg_temp_free_ptr(t_zn);</div>\r\n" - "<div>@@ -3568,7 +3568,7 @@ DO_VPZ(FMAXV, fmaxv)</div>\r\n" - "<div> static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)</div>\r\n" - "<div> {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div>@@ -3616,7 +3616,7 @@ static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a,</div>\r\n" - "<div> gen_helper_gvec_3_ptr *fn)</div>\r\n" - "<div> {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div>@@ -3668,7 +3668,7 @@ static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a)</div>\r\n" - "<div> }</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -3708,7 +3708,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)</div>\r\n" - "<div> t_pg = tcg_temp_new_ptr();</div>\r\n" - "<div> tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));</div>\r\n" - "<div> tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));</div>\r\n" - "<div>- t_fpst = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ t_fpst = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0));</div>\r\n" - "<div> </div>\r\n" - "<div> fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);</div>\r\n" - "<div>@@ -3735,7 +3735,7 @@ static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,</div>\r\n" - "<div> }</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -3777,7 +3777,7 @@ static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a,</div>\r\n" - "<div> }</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -3844,7 +3844,7 @@ static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,</div>\r\n" - "<div> gen_helper_sve_fp2scalar *fn)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 temp = tcg_const_i64(imm);</div>\r\n" - "<div>- do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn);</div>\r\n" - "<div>+ do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_UW, temp, fn);</div>\r\n" - "<div> tcg_temp_free_i64(temp);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3893,7 +3893,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a,</div>\r\n" - "<div> }</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -3937,7 +3937,7 @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)</div>\r\n" - "<div> }</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -4044,7 +4044,7 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)</div>\r\n" - "<div> tcg_debug_assert(a->rd == a->ra);</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rm),</div>\r\n" - "<div>@@ -4186,7 +4186,7 @@ static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)</div>\r\n" - "<div> if (a->esz == 0) {</div>\r\n" - "<div> return false;</div>\r\n" - "<div> }</div>\r\n" - "<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,</div>\r\n" - "<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW,</div>\r\n" - "<div> frint_fns[a->esz - 1]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -4200,7 +4200,7 @@ static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)</div>\r\n" - "<div> if (a->esz == 0) {</div>\r\n" - "<div> return false;</div>\r\n" - "<div> }</div>\r\n" - "<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);</div>\r\n" - "<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW, fns[a->esz - 1]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)</div>\r\n" - "<div>@@ -4211,7 +4211,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div> TCGv_i32 tmode = tcg_const_i32(mode);</div>\r\n" - "<div>- TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);</div>\r\n" - "<div>+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> gen_helper_set_rmode(tmode, tmode, status);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -4262,7 +4262,7 @@ static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)</div>\r\n" - "<div> if (a->esz == 0) {</div>\r\n" - "<div> return false;</div>\r\n" - "<div> }</div>\r\n" - "<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);</div>\r\n" - "<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW, fns[a->esz - 1]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)</div>\r\n" - "<div>@@ -4275,7 +4275,7 @@ static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)</div>\r\n" - "<div> if (a->esz == 0) {</div>\r\n" - "<div> return false;</div>\r\n" - "<div> }</div>\r\n" - "<div>- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);</div>\r\n" - "<div>+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_UW, fns[a->esz - 1]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a)</div>\r\n" - "<div>diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>index 092eb5e..549874c 100644</div>\r\n" - "<div>--- a/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>+++ b/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>@@ -52,7 +52,7 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8)</div>\r\n" - "<div> (extract32(imm8, 0, 6) << 3);</div>\r\n" - "<div> imm <<= 16;</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |</div>\r\n" - "<div> (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |</div>\r\n" - "<div> (extract32(imm8, 0, 6) << 6);</div>\r\n" - "<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div>\r\n" - "<div>index 39266cf..8d10922 100644</div>\r\n" - "<div>--- a/target/arm/translate.c</div>\r\n" - "<div>+++ b/target/arm/translate.c</div>\r\n" - "<div>@@ -1477,7 +1477,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i32(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i32(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1496,7 +1496,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_gen_st8_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -4267,7 +4267,7 @@ const GVecGen2i ssra_op[4] = {</div>\r\n" - "<div> .fniv = gen_ssra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_ssra,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = gen_ssra32_i32,</div>\r\n" - "<div> .fniv = gen_ssra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4325,7 +4325,7 @@ const GVecGen2i usra_op[4] = {</div>\r\n" - "<div> .fniv = gen_usra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_usra,</div>\r\n" - "<div>- .vece = MO_16, },</div>\r\n" - "<div>+ .vece = MO_UW, },</div>\r\n" - "<div> { .fni4 = gen_usra32_i32,</div>\r\n" - "<div> .fniv = gen_usra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4353,7 +4353,7 @@ static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_16, 0xffff >> shift);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UW, 0xffff >> shift);</div>\r\n" - "<div> TCGv_i64 t = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_shri_i64(t, a, shift);</div>\r\n" - "<div>@@ -4405,7 +4405,7 @@ const GVecGen2i sri_op[4] = {</div>\r\n" - "<div> .fniv = gen_shr_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sri,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = gen_shr32_ins_i32,</div>\r\n" - "<div> .fniv = gen_shr_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4433,7 +4433,7 @@ static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_16, 0xffff << shift);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UW, 0xffff << shift);</div>\r\n" - "<div> TCGv_i64 t = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_shli_i64(t, a, shift);</div>\r\n" - "<div>@@ -4483,7 +4483,7 @@ const GVecGen2i sli_op[4] = {</div>\r\n" - "<div> .fniv = gen_shl_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sli,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = gen_shl32_ins_i32,</div>\r\n" - "<div> .fniv = gen_shl_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4579,7 +4579,7 @@ const GVecGen3 mla_op[4] = {</div>\r\n" - "<div> .fniv = gen_mla_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mla,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = gen_mla32_i32,</div>\r\n" - "<div> .fniv = gen_mla_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4603,7 +4603,7 @@ const GVecGen3 mls_op[4] = {</div>\r\n" - "<div> .fniv = gen_mls_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mls,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = gen_mls32_i32,</div>\r\n" - "<div> .fniv = gen_mls_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>@@ -4649,7 +4649,7 @@ const GVecGen3 cmtst_op[4] = {</div>\r\n" - "<div> { .fni4 = gen_helper_neon_tst_u16,</div>\r\n" - "<div> .fniv = gen_cmtst_vec,</div>\r\n" - "<div> .opt_opc = vecop_list_cmtst,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = gen_cmtst_i32,</div>\r\n" - "<div> .fniv = gen_cmtst_vec,</div>\r\n" - "<div> .opt_opc = vecop_list_cmtst,</div>\r\n" - "<div>@@ -4686,7 +4686,7 @@ const GVecGen4 uqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqadd_h,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div> .opt_opc = vecop_list_uqadd,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fniv = gen_uqadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_uqadd_s,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>@@ -4724,7 +4724,7 @@ const GVecGen4 sqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqadd_h,</div>\r\n" - "<div> .opt_opc = vecop_list_sqadd,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fniv = gen_sqadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sqadd_s,</div>\r\n" - "<div> .opt_opc = vecop_list_sqadd,</div>\r\n" - "<div>@@ -4762,7 +4762,7 @@ const GVecGen4 uqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqsub_h,</div>\r\n" - "<div> .opt_opc = vecop_list_uqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fniv = gen_uqsub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_uqsub_s,</div>\r\n" - "<div> .opt_opc = vecop_list_uqsub,</div>\r\n" - "<div>@@ -4800,7 +4800,7 @@ const GVecGen4 sqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqsub_h,</div>\r\n" - "<div> .opt_opc = vecop_list_sqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fniv = gen_sqsub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sqsub_s,</div>\r\n" - "<div> .opt_opc = vecop_list_sqsub,</div>\r\n" - "<div>@@ -6876,7 +6876,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_UB;</div>\r\n" - "<div> element = (insn >> 17) & 7;</div>\r\n" - "<div> } else if (insn & (1 << 17)) {</div>\r\n" - "<div>- size = MO_16;</div>\r\n" - "<div>+ size = MO_UW;</div>\r\n" - "<div> element = (insn >> 18) & 3;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> size = MO_32;</div>\r\n" - "<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div>\r\n" - "<div>index 0e45300..0535bae 100644</div>\r\n" - "<div>--- a/target/i386/translate.c</div>\r\n" - "<div>+++ b/target/i386/translate.c</div>\r\n" - "<div>@@ -323,7 +323,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int reg)</div>\r\n" - "<div> static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (CODE64(s)) {</div>\r\n" - "<div>- return ot == MO_16 ? MO_16 : MO_64;</div>\r\n" - "<div>+ return ot == MO_UW ? MO_UW : MO_64;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> return ot;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -332,7 +332,7 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> /* Select the size of the stack pointer. */</div>\r\n" - "<div> static inline TCGMemOp mo_stacksize(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>+ return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div>\r\n" - "<div>@@ -356,7 +356,7 @@ static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div>\r\n" - "<div> Used for decoding operand size of port opcodes. */</div>\r\n" - "<div> static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_UB;</div>\r\n" - "<div>+ return b & 1 ? (ot == MO_UW ? MO_UW : MO_32) : MO_UB;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div>@@ -369,7 +369,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div> tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -473,7 +473,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> /* 16 bit address */</div>\r\n" - "<div> tcg_gen_ext16u_tl(s->A0, a0);</div>\r\n" - "<div> a0 = s->A0;</div>\r\n" - "<div>@@ -530,7 +530,7 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div>\r\n" - "<div> tcg_gen_ext8u_tl(dst, src);</div>\r\n" - "<div> }</div>\r\n" - "<div> return dst;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (sign) {</div>\r\n" - "<div> tcg_gen_ext16s_tl(dst, src);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -583,7 +583,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> gen_helper_inb(v, cpu_env, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_helper_inw(v, cpu_env, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -600,7 +600,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> gen_helper_outb(cpu_env, v, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_helper_outw(cpu_env, v, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -622,7 +622,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> gen_helper_check_iob(cpu_env, s->tmp2_i32);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_helper_check_iow(cpu_env, s->tmp2_i32);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1562,7 +1562,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div>\r\n" - "<div> tcg_gen_ext8u_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_muli_tl(s->T0, s->T0, 0x01010101);</div>\r\n" - "<div> goto do_long;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> /* Replicate the 16-bit input so that a 32-bit rotate works. */</div>\r\n" - "<div> tcg_gen_deposit_tl(s->T0, s->T0, s->T0, 16, 16);</div>\r\n" - "<div> goto do_long;</div>\r\n" - "<div>@@ -1664,7 +1664,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> mask = 7;</div>\r\n" - "<div> goto do_shifts;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> mask = 15;</div>\r\n" - "<div> do_shifts:</div>\r\n" - "<div> shift = op2 & mask;</div>\r\n" - "<div>@@ -1722,7 +1722,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> gen_helper_rcrb(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_helper_rcrw(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1741,7 +1741,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> gen_helper_rclb(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_helper_rclw(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1778,7 +1778,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> tcg_gen_andi_tl(count, count_in, mask);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> /* Note: we implement the Intel behaviour for shift count > 16.</div>\r\n" - "<div> This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A</div>\r\n" - "<div> portion by constructing it as a 32-bit value. */</div>\r\n" - "<div>@@ -1817,7 +1817,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> tcg_gen_shl_tl(s->T1, s->T1, s->tmp4);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0);</div>\r\n" - "<div>- if (ot == MO_16) {</div>\r\n" - "<div>+ if (ot == MO_UW) {</div>\r\n" - "<div> /* Only needed if count > 16, for Intel behaviour. */</div>\r\n" - "<div> tcg_gen_subfi_tl(s->tmp4, 33, count);</div>\r\n" - "<div> tcg_gen_shr_tl(s->tmp4, s->T1, s->tmp4);</div>\r\n" - "<div>@@ -2026,7 +2026,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (mod == 0) {</div>\r\n" - "<div> if (rm == 6) {</div>\r\n" - "<div> base = -1;</div>\r\n" - "<div>@@ -2187,7 +2187,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> ret = x86_ldub_code(env, s);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> ret = x86_lduw_code(env, s);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -2400,12 +2400,12 @@ static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void gen_stack_A0(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1);</div>\r\n" - "<div>+ gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_UW, cpu_regs[R_ESP], R_SS, -1);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_pusha(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>+ TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div> TCGMemOp d_ot = s->dflag;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> int i;</div>\r\n" - "<div>@@ -2421,7 +2421,7 @@ static void gen_pusha(DisasContext *s)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_popa(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>+ TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div> TCGMemOp d_ot = s->dflag;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> int i;</div>\r\n" - "<div>@@ -2443,7 +2443,7 @@ static void gen_popa(DisasContext *s)</div>\r\n" - "<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>+ TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Push BP; compute FrameTemp into T1. */</div>\r\n" - "<div>@@ -3613,7 +3613,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> case 0xc4: /* pinsrw */</div>\r\n" - "<div> case 0x1c4:</div>\r\n" - "<div> s->rip_offset = 1;</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div> val = x86_ldub_code(env, s);</div>\r\n" - "<div> if (b1) {</div>\r\n" - "<div> val &= 7;</div>\r\n" - "<div>@@ -3786,7 +3786,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> if ((b & 0xff) == 0xf0) {</div>\r\n" - "<div> ot = MO_UB;</div>\r\n" - "<div> } else if (s->dflag != MO_64) {</div>\r\n" - "<div>- ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);</div>\r\n" - "<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -3815,7 +3815,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> if (s->dflag != MO_64) {</div>\r\n" - "<div>- ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);</div>\r\n" - "<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -4630,7 +4630,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* In 64-bit mode, the default data size is 32-bit. Select 64-bit</div>\r\n" - "<div> data with rex_w, and 16-bit data with 0x66; rex_w takes precedence</div>\r\n" - "<div> over 0x66 if both are present. */</div>\r\n" - "<div>- dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);</div>\r\n" - "<div>+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_32);</div>\r\n" - "<div> /* In 64-bit mode, 0x67 selects 32-bit addressing. */</div>\r\n" - "<div> aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -4638,13 +4638,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {</div>\r\n" - "<div> dflag = MO_32;</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- dflag = MO_16;</div>\r\n" - "<div>+ dflag = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> /* In 16/32-bit mode, 0x67 selects the opposite addressing. */</div>\r\n" - "<div> if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {</div>\r\n" - "<div> aflag = MO_32;</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- aflag = MO_16;</div>\r\n" - "<div>+ aflag = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -4872,21 +4872,21 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tcg_gen_ext8u_tl(s->T1, s->T1);</div>\r\n" - "<div> /* XXX: use 32 bit mul which could be faster */</div>\r\n" - "<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div>\r\n" - "<div> tcg_gen_andi_tl(cpu_cc_src, s->T0, 0xff00);</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULB);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UW, s->T1, R_EAX);</div>\r\n" - "<div> tcg_gen_ext16u_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_ext16u_tl(s->T1, s->T1);</div>\r\n" - "<div> /* XXX: use 32 bit mul which could be faster */</div>\r\n" - "<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div>\r\n" - "<div> tcg_gen_shri_tl(s->T0, s->T0, 16);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EDX, s->T0);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_src, s->T0);</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULW);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -4921,24 +4921,24 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tcg_gen_ext8s_tl(s->T1, s->T1);</div>\r\n" - "<div> /* XXX: use 32 bit mul which could be faster */</div>\r\n" - "<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div>\r\n" - "<div> tcg_gen_ext8s_tl(s->tmp0, s->T0);</div>\r\n" - "<div> tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULB);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UW, s->T1, R_EAX);</div>\r\n" - "<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_ext16s_tl(s->T1, s->T1);</div>\r\n" - "<div> /* XXX: use 32 bit mul which could be faster */</div>\r\n" - "<div> tcg_gen_mul_tl(s->T0, s->T0, s->T1);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_dst, s->T0);</div>\r\n" - "<div> tcg_gen_ext16s_tl(s->tmp0, s->T0);</div>\r\n" - "<div> tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);</div>\r\n" - "<div> tcg_gen_shri_tl(s->T0, s->T0, 16);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EDX, s->T0);</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULW);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -4972,7 +4972,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> gen_helper_divb_AL(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_helper_divw_AX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -4991,7 +4991,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> gen_helper_idivb_AL(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_helper_idivw_AX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -5026,7 +5026,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* operand size for jumps is 64 bit */</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> } else if (op == 3 || op == 5) {</div>\r\n" - "<div>- ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16;</div>\r\n" - "<div>+ ot = dflag != MO_UW ? MO_32 + (rex_w == 1) : MO_UW;</div>\r\n" - "<div> } else if (op == 6) {</div>\r\n" - "<div> /* default push size is 64 bit */</div>\r\n" - "<div> ot = mo_pushpop(s, dflag);</div>\r\n" - "<div>@@ -5057,7 +5057,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 2: /* call Ev */</div>\r\n" - "<div> /* XXX: optimize if memory (no 'and' is necessary) */</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_ext16u_tl(s->T0, s->T0);</div>\r\n" - "<div> }</div>\r\n" - "<div> next_eip = s->pc - s->cs_base;</div>\r\n" - "<div>@@ -5070,7 +5070,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 3: /* lcall Ev */</div>\r\n" - "<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 1 << ot);</div>\r\n" - "<div>- gen_op_ld_v(s, MO_16, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UW, s->T0, s->A0);</div>\r\n" - "<div> do_lcall:</div>\r\n" - "<div> if (s->pe && !s->vm86) {</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div>@@ -5087,7 +5087,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_jr(s, s->tmp4);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 4: /* jmp Ev */</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_ext16u_tl(s->T0, s->T0);</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_op_jmp_v(s->T0);</div>\r\n" - "<div>@@ -5097,7 +5097,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 5: /* ljmp Ev */</div>\r\n" - "<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 1 << ot);</div>\r\n" - "<div>- gen_op_ld_v(s, MO_16, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UW, s->T0, s->A0);</div>\r\n" - "<div> do_ljmp:</div>\r\n" - "<div> if (s->pe && !s->vm86) {</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div>@@ -5152,14 +5152,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div>\r\n" - "<div> gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> gen_op_mov_v_reg(s, MO_UB, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext8s_tl(s->T0, s->T0);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div> tcg_abort();</div>\r\n" - "<div>@@ -5180,11 +5180,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tcg_gen_sari_tl(s->T0, s->T0, 31);</div>\r\n" - "<div> gen_op_mov_reg_v(s, MO_32, R_EDX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_sari_tl(s->T0, s->T0, 15);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EDX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div> tcg_abort();</div>\r\n" - "<div>@@ -5538,7 +5538,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> reg = (modrm >> 3) & 7;</div>\r\n" - "<div> if (reg >= 6 || reg == R_CS)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div> gen_movl_seg_T0(s, reg);</div>\r\n" - "<div> /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */</div>\r\n" - "<div> if (s->base.is_jmp) {</div>\r\n" - "<div>@@ -5558,7 +5558,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (reg >= 6)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> gen_op_movl_T0_seg(s, reg);</div>\r\n" - "<div>- ot = mod == 3 ? dflag : MO_16;</div>\r\n" - "<div>+ ot = mod == 3 ? dflag : MO_UW;</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -5734,7 +5734,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x1b5: /* lgs Gv */</div>\r\n" - "<div> op = R_GS;</div>\r\n" - "<div> do_lxx:</div>\r\n" - "<div>- ot = dflag != MO_16 ? MO_32 : MO_16;</div>\r\n" - "<div>+ ot = dflag != MO_UW ? MO_32 : MO_UW;</div>\r\n" - "<div> modrm = x86_ldub_code(env, s);</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div> mod = (modrm >> 6) & 3;</div>\r\n" - "<div>@@ -5744,7 +5744,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 1 << ot);</div>\r\n" - "<div> /* load the segment first to handle exceptions properly */</div>\r\n" - "<div>- gen_op_ld_v(s, MO_16, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UW, s->T0, s->A0);</div>\r\n" - "<div> gen_movl_seg_T0(s, op);</div>\r\n" - "<div> /* then put the data */</div>\r\n" - "<div> gen_op_mov_reg_v(s, ot, reg, s->T1);</div>\r\n" - "<div>@@ -6287,7 +6287,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0:</div>\r\n" - "<div> gen_helper_fnstsw(s->tmp2_i32, cpu_env);</div>\r\n" - "<div> tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UW, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div> goto unknown_op;</div>\r\n" - "<div>@@ -6575,14 +6575,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0xe8: /* call im */</div>\r\n" - "<div> {</div>\r\n" - "<div>- if (dflag != MO_16) {</div>\r\n" - "<div>+ if (dflag != MO_UW) {</div>\r\n" - "<div> tval = (int32_t)insn_get(env, s, MO_32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- tval = (int16_t)insn_get(env, s, MO_16);</div>\r\n" - "<div>+ tval = (int16_t)insn_get(env, s, MO_UW);</div>\r\n" - "<div> }</div>\r\n" - "<div> next_eip = s->pc - s->cs_base;</div>\r\n" - "<div> tval += next_eip;</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tval &= 0xffff;</div>\r\n" - "<div> } else if (!CODE64(s)) {</div>\r\n" - "<div> tval &= 0xffffffff;</div>\r\n" - "<div>@@ -6601,20 +6601,20 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> ot = dflag;</div>\r\n" - "<div> offset = insn_get(env, s, ot);</div>\r\n" - "<div>- selector = insn_get(env, s, MO_16);</div>\r\n" - "<div>+ selector = insn_get(env, s, MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_movi_tl(s->T0, selector);</div>\r\n" - "<div> tcg_gen_movi_tl(s->T1, offset);</div>\r\n" - "<div> }</div>\r\n" - "<div> goto do_lcall;</div>\r\n" - "<div> case 0xe9: /* jmp im */</div>\r\n" - "<div>- if (dflag != MO_16) {</div>\r\n" - "<div>+ if (dflag != MO_UW) {</div>\r\n" - "<div> tval = (int32_t)insn_get(env, s, MO_32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- tval = (int16_t)insn_get(env, s, MO_16);</div>\r\n" - "<div>+ tval = (int16_t)insn_get(env, s, MO_UW);</div>\r\n" - "<div> }</div>\r\n" - "<div> tval += s->pc - s->cs_base;</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tval &= 0xffff;</div>\r\n" - "<div> } else if (!CODE64(s)) {</div>\r\n" - "<div> tval &= 0xffffffff;</div>\r\n" - "<div>@@ -6630,7 +6630,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> ot = dflag;</div>\r\n" - "<div> offset = insn_get(env, s, ot);</div>\r\n" - "<div>- selector = insn_get(env, s, MO_16);</div>\r\n" - "<div>+ selector = insn_get(env, s, MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_movi_tl(s->T0, selector);</div>\r\n" - "<div> tcg_gen_movi_tl(s->T1, offset);</div>\r\n" - "<div>@@ -6639,7 +6639,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0xeb: /* jmp Jb */</div>\r\n" - "<div> tval = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> tval += s->pc - s->cs_base;</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tval &= 0xffff;</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_jmp(s, tval);</div>\r\n" - "<div>@@ -6648,15 +6648,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tval = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> goto do_jcc;</div>\r\n" - "<div> case 0x180 ... 0x18f: /* jcc Jv */</div>\r\n" - "<div>- if (dflag != MO_16) {</div>\r\n" - "<div>+ if (dflag != MO_UW) {</div>\r\n" - "<div> tval = (int32_t)insn_get(env, s, MO_32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- tval = (int16_t)insn_get(env, s, MO_16);</div>\r\n" - "<div>+ tval = (int16_t)insn_get(env, s, MO_UW);</div>\r\n" - "<div> }</div>\r\n" - "<div> do_jcc:</div>\r\n" - "<div> next_eip = s->pc - s->cs_base;</div>\r\n" - "<div> tval += next_eip;</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tval &= 0xffff;</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_bnd_jmp(s);</div>\r\n" - "<div>@@ -6697,7 +6697,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> } else {</div>\r\n" - "<div> ot = gen_pop_T0(s);</div>\r\n" - "<div> if (s->cpl == 0) {</div>\r\n" - "<div>- if (dflag != MO_16) {</div>\r\n" - "<div>+ if (dflag != MO_UW) {</div>\r\n" - "<div> gen_helper_write_eflags(cpu_env, s->T0,</div>\r\n" - "<div> tcg_const_i32((TF_MASK | AC_MASK |</div>\r\n" - "<div> ID_MASK | NT_MASK |</div>\r\n" - "<div>@@ -6712,7 +6712,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div> if (s->cpl <= s->iopl) {</div>\r\n" - "<div>- if (dflag != MO_16) {</div>\r\n" - "<div>+ if (dflag != MO_UW) {</div>\r\n" - "<div> gen_helper_write_eflags(cpu_env, s->T0,</div>\r\n" - "<div> tcg_const_i32((TF_MASK |</div>\r\n" - "<div> AC_MASK |</div>\r\n" - "<div>@@ -6729,7 +6729,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> & 0xffff));</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- if (dflag != MO_16) {</div>\r\n" - "<div>+ if (dflag != MO_UW) {</div>\r\n" - "<div> gen_helper_write_eflags(cpu_env, s->T0,</div>\r\n" - "<div> tcg_const_i32((TF_MASK | AC_MASK |</div>\r\n" - "<div> ID_MASK | NT_MASK)));</div>\r\n" - "<div>@@ -7110,7 +7110,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_op_mov_v_reg(s, ot, s->T0, reg);</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div>- if (ot == MO_16) {</div>\r\n" - "<div>+ if (ot == MO_UW) {</div>\r\n" - "<div> gen_helper_boundw(cpu_env, s->A0, s->tmp2_i32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> gen_helper_boundl(cpu_env, s->A0, s->tmp2_i32);</div>\r\n" - "<div>@@ -7149,7 +7149,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tval = (int8_t)insn_get(env, s, MO_UB);</div>\r\n" - "<div> next_eip = s->pc - s->cs_base;</div>\r\n" - "<div> tval += next_eip;</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tval &= 0xffff;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -7291,7 +7291,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State, ldt.selector));</div>\r\n" - "<div>- ot = mod == 3 ? dflag : MO_16;</div>\r\n" - "<div>+ ot = mod == 3 ? dflag : MO_UW;</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 2: /* lldt */</div>\r\n" - "<div>@@ -7301,7 +7301,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> gen_helper_lldt(cpu_env, s->tmp2_i32);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -7312,7 +7312,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State, tr.selector));</div>\r\n" - "<div>- ot = mod == 3 ? dflag : MO_16;</div>\r\n" - "<div>+ ot = mod == 3 ? dflag : MO_UW;</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3: /* ltr */</div>\r\n" - "<div>@@ -7322,7 +7322,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> gen_helper_ltr(cpu_env, s->tmp2_i32);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -7331,7 +7331,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 5: /* verw */</div>\r\n" - "<div> if (!s->pe || s->vm86)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div> gen_update_cc_op(s);</div>\r\n" - "<div> if (op == 4) {</div>\r\n" - "<div> gen_helper_verr(cpu_env, s->T0);</div>\r\n" - "<div>@@ -7353,10 +7353,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0,</div>\r\n" - "<div> cpu_env, offsetof(CPUX86State, gdt.limit));</div>\r\n" - "<div>- gen_op_st_v(s, MO_16, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_st_v(s, MO_UW, s->T0, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 2);</div>\r\n" - "<div> tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base));</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>@@ -7408,10 +7408,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.limit));</div>\r\n" - "<div>- gen_op_st_v(s, MO_16, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_st_v(s, MO_UW, s->T0, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 2);</div>\r\n" - "<div> tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base));</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>@@ -7558,10 +7558,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE);</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div>- gen_op_ld_v(s, MO_16, s->T1, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 2);</div>\r\n" - "<div> gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base));</div>\r\n" - "<div>@@ -7575,10 +7575,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE);</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div>- gen_op_ld_v(s, MO_16, s->T1, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 2);</div>\r\n" - "<div> gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>- if (dflag == MO_16) {</div>\r\n" - "<div>+ if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base));</div>\r\n" - "<div>@@ -7590,9 +7590,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0]));</div>\r\n" - "<div> if (CODE64(s)) {</div>\r\n" - "<div> mod = (modrm >> 6) & 3;</div>\r\n" - "<div>- ot = (mod != 3 ? MO_16 : s->dflag);</div>\r\n" - "<div>+ ot = (mod != 3 ? MO_UW : s->dflag);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- ot = MO_16;</div>\r\n" - "<div>+ ot = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -7619,7 +7619,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div> gen_helper_lmsw(cpu_env, s->T0);</div>\r\n" - "<div> gen_jmp_im(s, s->pc - s->cs_base);</div>\r\n" - "<div> gen_eob(s);</div>\r\n" - "<div>@@ -7720,7 +7720,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> t0 = tcg_temp_local_new();</div>\r\n" - "<div> t1 = tcg_temp_local_new();</div>\r\n" - "<div> t2 = tcg_temp_local_new();</div>\r\n" - "<div>- ot = MO_16;</div>\r\n" - "<div>+ ot = MO_UW;</div>\r\n" - "<div> modrm = x86_ldub_code(env, s);</div>\r\n" - "<div> reg = (modrm >> 3) & 7;</div>\r\n" - "<div> mod = (modrm >> 6) & 3;</div>\r\n" - "<div>@@ -7765,10 +7765,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> TCGv t0;</div>\r\n" - "<div> if (!s->pe || s->vm86)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div>- ot = dflag != MO_16 ? MO_32 : MO_16;</div>\r\n" - "<div>+ ot = dflag != MO_UW ? MO_32 : MO_UW;</div>\r\n" - "<div> modrm = x86_ldub_code(env, s);</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div> t0 = tcg_temp_local_new();</div>\r\n" - "<div> gen_update_cc_op(s);</div>\r\n" - "<div> if (b == 0x102) {</div>\r\n" - "<div>@@ -7813,7 +7813,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* bndcl */</div>\r\n" - "<div> if (reg >= 4</div>\r\n" - "<div> || (prefixes & PREFIX_LOCK)</div>\r\n" - "<div>- || s->aflag == MO_16) {</div>\r\n" - "<div>+ || s->aflag == MO_UW) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_bndck(env, s, modrm, TCG_COND_LTU, cpu_bndl[reg]);</div>\r\n" - "<div>@@ -7821,7 +7821,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* bndcu */</div>\r\n" - "<div> if (reg >= 4</div>\r\n" - "<div> || (prefixes & PREFIX_LOCK)</div>\r\n" - "<div>- || s->aflag == MO_16) {</div>\r\n" - "<div>+ || s->aflag == MO_UW) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> TCGv_i64 notu = tcg_temp_new_i64();</div>\r\n" - "<div>@@ -7830,7 +7830,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tcg_temp_free_i64(notu);</div>\r\n" - "<div> } else if (prefixes & PREFIX_DATA) {</div>\r\n" - "<div> /* bndmov -- from reg/mem */</div>\r\n" - "<div>- if (reg >= 4 || s->aflag == MO_16) {</div>\r\n" - "<div>+ if (reg >= 4 || s->aflag == MO_UW) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> if (mod == 3) {</div>\r\n" - "<div>@@ -7865,7 +7865,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div>\r\n" - "<div> if (reg >= 4</div>\r\n" - "<div> || (prefixes & PREFIX_LOCK)</div>\r\n" - "<div>- || s->aflag == MO_16</div>\r\n" - "<div>+ || s->aflag == MO_UW</div>\r\n" - "<div> || a.base < -1) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -7903,7 +7903,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* bndmk */</div>\r\n" - "<div> if (reg >= 4</div>\r\n" - "<div> || (prefixes & PREFIX_LOCK)</div>\r\n" - "<div>- || s->aflag == MO_16) {</div>\r\n" - "<div>+ || s->aflag == MO_UW) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div>\r\n" - "<div>@@ -7931,13 +7931,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* bndcn */</div>\r\n" - "<div> if (reg >= 4</div>\r\n" - "<div> || (prefixes & PREFIX_LOCK)</div>\r\n" - "<div>- || s->aflag == MO_16) {</div>\r\n" - "<div>+ || s->aflag == MO_UW) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]);</div>\r\n" - "<div> } else if (prefixes & PREFIX_DATA) {</div>\r\n" - "<div> /* bndmov -- to reg/mem */</div>\r\n" - "<div>- if (reg >= 4 || s->aflag == MO_16) {</div>\r\n" - "<div>+ if (reg >= 4 || s->aflag == MO_UW) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> if (mod == 3) {</div>\r\n" - "<div>@@ -7970,7 +7970,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div>\r\n" - "<div> if (reg >= 4</div>\r\n" - "<div> || (prefixes & PREFIX_LOCK)</div>\r\n" - "<div>- || s->aflag == MO_16</div>\r\n" - "<div>+ || s->aflag == MO_UW</div>\r\n" - "<div> || a.base < -1) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -8341,7 +8341,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div> </div>\r\n" - "<div> if (s->prefix & PREFIX_DATA) {</div>\r\n" - "<div>- ot = MO_16;</div>\r\n" - "<div>+ ot = MO_UW;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> ot = mo_64_32(dflag);</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div>\r\n" - "<div>index 20a9777..525c7fe 100644</div>\r\n" - "<div>--- a/target/mips/translate.c</div>\r\n" - "<div>+++ b/target/mips/translate.c</div>\r\n" - "<div>@@ -21087,7 +21087,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,</div>\r\n" - "<div> imm = sextract32(ctx->opcode, 11, 11);</div>\r\n" - "<div> imm = (int16_t)(imm << 6) >> 6;</div>\r\n" - "<div> if (rt != 0) {</div>\r\n" - "<div>- tcg_gen_movi_tl(cpu_gpr[rt], dup_const(MO_16, imm));</div>\r\n" - "<div>+ tcg_gen_movi_tl(cpu_gpr[rt], dup_const(MO_UW, imm));</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>index 4130dd1..71efef4 100644</div>\r\n" - "<div>--- a/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>@@ -406,29 +406,29 @@ static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div> GEN_VXFORM_V(vaddubm, MO_UB, tcg_gen_gvec_add, 0, 0);</div>\r\n" - "<div> GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \\</div>\r\n" - "<div> vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div>\r\n" - "<div>-GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);</div>\r\n" - "<div>+GEN_VXFORM_V(vadduhm, MO_UW, tcg_gen_gvec_add, 0, 1);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);</div>\r\n" - "<div> GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div>\r\n" - "<div> GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div>\r\n" - "<div>-GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);</div>\r\n" - "<div>+GEN_VXFORM_V(vsubuhm, MO_UW, tcg_gen_gvec_sub, 0, 17);</div>\r\n" - "<div> GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);</div>\r\n" - "<div> GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxuh, MO_UW, tcg_gen_gvec_umax, 1, 1);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxsh, MO_UW, tcg_gen_gvec_smax, 1, 5);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div>\r\n" - "<div> GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div>\r\n" - "<div>-GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);</div>\r\n" - "<div>+GEN_VXFORM_V(vminuh, MO_UW, tcg_gen_gvec_umin, 1, 9);</div>\r\n" - "<div> GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);</div>\r\n" - "<div> GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div>\r\n" - "<div> GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div>\r\n" - "<div>-GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);</div>\r\n" - "<div>+GEN_VXFORM_V(vminsh, MO_UW, tcg_gen_gvec_smin, 1, 13);</div>\r\n" - "<div> GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div>\r\n" - "<div> GEN_VXFORM(vavgub, 1, 16);</div>\r\n" - "<div>@@ -531,18 +531,18 @@ GEN_VXFORM(vmulesb, 4, 12);</div>\r\n" - "<div> GEN_VXFORM(vmulesh, 4, 13);</div>\r\n" - "<div> GEN_VXFORM(vmulesw, 4, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vslb, MO_UB, tcg_gen_gvec_shlv, 2, 4);</div>\r\n" - "<div>-GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);</div>\r\n" - "<div>+GEN_VXFORM_V(vslh, MO_UW, tcg_gen_gvec_shlv, 2, 5);</div>\r\n" - "<div> GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);</div>\r\n" - "<div> GEN_VXFORM(vrlwnm, 2, 6);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div>\r\n" - "<div> GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div>\r\n" - "<div>-GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);</div>\r\n" - "<div>+GEN_VXFORM_V(vsrh, MO_UW, tcg_gen_gvec_shrv, 2, 9);</div>\r\n" - "<div> GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);</div>\r\n" - "<div> GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div>\r\n" - "<div> GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div>\r\n" - "<div>-GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);</div>\r\n" - "<div>+GEN_VXFORM_V(vsrah, MO_UW, tcg_gen_gvec_sarv, 2, 13);</div>\r\n" - "<div> GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div>\r\n" - "<div> GEN_VXFORM(vsrv, 2, 28);</div>\r\n" - "<div>@@ -592,18 +592,18 @@ static void glue(gen_, NAME)(DisasContext *ctx) \\</div>\r\n" - "<div> GEN_VXFORM_SAT(vaddubs, MO_UB, add, usadd, 0, 8);</div>\r\n" - "<div> GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \\</div>\r\n" - "<div> vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)</div>\r\n" - "<div>-GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vadduhs, MO_UW, add, usadd, 0, 9);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vmul10euq, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);</div>\r\n" - "<div> GEN_VXFORM_SAT(vaddsbs, MO_UB, add, ssadd, 0, 12);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vaddshs, MO_UW, add, ssadd, 0, 13);</div>\r\n" - "<div> GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsububs, MO_UB, sub, ussub, 0, 24);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vsubuhs, MO_UW, sub, ussub, 0, 25);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubsbs, MO_UB, sub, sssub, 0, 28);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vsubshs, MO_UW, sub, sssub, 0, 29);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);</div>\r\n" - "<div> GEN_VXFORM(vadduqm, 0, 4);</div>\r\n" - "<div> GEN_VXFORM(vaddcuq, 0, 5);</div>\r\n" - "<div>@@ -913,7 +913,7 @@ static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> GEN_VXFORM_VSPLT(vspltb, MO_UB, 6, 8);</div>\r\n" - "<div>-GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);</div>\r\n" - "<div>+GEN_VXFORM_VSPLT(vsplth, MO_UW, 6, 9);</div>\r\n" - "<div> GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);</div>\r\n" - "<div> GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);</div>\r\n" - "<div> GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);</div>\r\n" - "<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>index bb424c8..65da6b3 100644</div>\r\n" - "<div>--- a/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>+++ b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>@@ -47,7 +47,7 @@</div>\r\n" - "<div> #define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)</div>\r\n" - "<div> </div>\r\n" - "<div> #define ES_8 MO_UB</div>\r\n" - "<div>-#define ES_16 MO_16</div>\r\n" - "<div>+#define ES_16 MO_UW</div>\r\n" - "<div> #define ES_32 MO_32</div>\r\n" - "<div> #define ES_64 MO_64</div>\r\n" - "<div> #define ES_128 4</div>\r\n" - "<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div>\r\n" - "<div>index b813054..28e1b1d 100644</div>\r\n" - "<div>--- a/target/s390x/vec.h</div>\r\n" - "<div>+++ b/target/s390x/vec.h</div>\r\n" - "<div>@@ -78,7 +78,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div>\r\n" - "<div> switch (es) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> return s390_vec_read_element8(v, enr);</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> return s390_vec_read_element16(v, enr);</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div> return s390_vec_read_element32(v, enr);</div>\r\n" - "<div>@@ -124,7 +124,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> s390_vec_write_element8(v, enr, data);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> s390_vec_write_element16(v, enr, data);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>index e4e0845..3d90c4b 100644</div>\r\n" - "<div>--- a/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>@@ -430,20 +430,20 @@ typedef enum {</div>\r\n" - "<div> /* Load/store register. Described here as 3.3.12, but the helper</div>\r\n" - "<div> that emits them can transform to 3.3.10 or 3.3.13. */</div>\r\n" - "<div> I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div>\r\n" - "<div>- I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,</div>\r\n" - "<div>+ I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_UW << 30,</div>\r\n" - "<div> I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,</div>\r\n" - "<div> I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div>\r\n" - "<div>- I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,</div>\r\n" - "<div>+ I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_UW << 30,</div>\r\n" - "<div> I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,</div>\r\n" - "<div> I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div>\r\n" - "<div>- I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,</div>\r\n" - "<div>+ I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_UW << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_UB << 30,</div>\r\n" - "<div>- I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,</div>\r\n" - "<div>+ I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_UW << 30,</div>\r\n" - "<div> I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,</div>\r\n" - "<div>@@ -870,7 +870,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div>\r\n" - "<div> </div>\r\n" - "<div> /*</div>\r\n" - "<div> * Test all bytes 0x00 or 0xff second. This can match cases that</div>\r\n" - "<div>- * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.</div>\r\n" - "<div>+ * might otherwise take 2 or 3 insns for MO_UW or MO_32 below.</div>\r\n" - "<div> */</div>\r\n" - "<div> for (i = imm8 = 0; i < 8; i++) {</div>\r\n" - "<div> uint8_t byte = v64 >> (i * 8);</div>\r\n" - "<div>@@ -889,7 +889,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div>\r\n" - "<div> * cannot find an expansion there's no point checking a larger</div>\r\n" - "<div> * width because we already know by replication it cannot match.</div>\r\n" - "<div> */</div>\r\n" - "<div>- if (v64 == dup_const(MO_16, v64)) {</div>\r\n" - "<div>+ if (v64 == dup_const(MO_UW, v64)) {</div>\r\n" - "<div> uint16_t v16 = v64;</div>\r\n" - "<div> </div>\r\n" - "<div> if (is_shimm16(v16, &cmode, &imm8)) {</div>\r\n" - "<div>@@ -1733,7 +1733,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> tcg_out_rev16(s, data_r, data_r);</div>\r\n" - "<div>- tcg_out_sxt(s, ext, MO_16, data_r, data_r);</div>\r\n" - "<div>+ tcg_out_sxt(s, ext, MO_UW, data_r, data_r);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),</div>\r\n" - "<div> data_r, addr_r, otype, off_r);</div>\r\n" - "<div>@@ -1775,7 +1775,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (bswap && data_r != TCG_REG_XZR) {</div>\r\n" - "<div> tcg_out_rev16(s, TCG_REG_TMP, data_r);</div>\r\n" - "<div> data_r = TCG_REG_TMP;</div>\r\n" - "<div>@@ -2190,7 +2190,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext16s_i64:</div>\r\n" - "<div> case INDEX_op_ext16s_i32:</div>\r\n" - "<div>- tcg_out_sxt(s, ext, MO_16, a0, a1);</div>\r\n" - "<div>+ tcg_out_sxt(s, ext, MO_UW, a0, a1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext_i32_i64:</div>\r\n" - "<div> case INDEX_op_ext32s_i64:</div>\r\n" - "<div>@@ -2202,7 +2202,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext16u_i64:</div>\r\n" - "<div> case INDEX_op_ext16u_i32:</div>\r\n" - "<div>- tcg_out_uxt(s, MO_16, a0, a1);</div>\r\n" - "<div>+ tcg_out_uxt(s, MO_UW, a0, a1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_extu_i32_i64:</div>\r\n" - "<div> case INDEX_op_ext32u_i64:</div>\r\n" - "<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>index 542ffa8..0bd400e 100644</div>\r\n" - "<div>--- a/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>@@ -1432,7 +1432,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> argreg = tcg_out_arg_reg8(s, argreg, datalo);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> argreg = tcg_out_arg_reg16(s, argreg, datalo);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1624,7 +1624,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_out_st8_r(s, cond, datalo, addrlo, addend);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo);</div>\r\n" - "<div> tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);</div>\r\n" - "<div>@@ -1669,7 +1669,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo);</div>\r\n" - "<div> tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);</div>\r\n" - "<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>index 0d68ba4..31c3664 100644</div>\r\n" - "<div>--- a/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>@@ -893,7 +893,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a);</div>\r\n" - "<div> a = r;</div>\r\n" - "<div> /* FALLTHRU */</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a);</div>\r\n" - "<div> a = r;</div>\r\n" - "<div> /* FALLTHRU */</div>\r\n" - "<div>@@ -927,7 +927,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div> tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset);</div>\r\n" - "<div> tcg_out8(s, 0); /* imm8 */</div>\r\n" - "<div> tcg_out_dup_vec(s, type, vece, r, r);</div>\r\n" - "<div>@@ -2164,7 +2164,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,</div>\r\n" - "<div> datalo, base, index, 0, ofs);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);</div>\r\n" - "<div> tcg_out_rolw_8(s, scratch);</div>\r\n" - "<div>@@ -2747,15 +2747,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2</div>\r\n" - "<div> };</div>\r\n" - "<div> static int const shlv_insn[4] = {</div>\r\n" - "<div>- /* TODO: AVX512 adds support for MO_16. */</div>\r\n" - "<div>+ /* TODO: AVX512 adds support for MO_UW. */</div>\r\n" - "<div> OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ</div>\r\n" - "<div> };</div>\r\n" - "<div> static int const shrv_insn[4] = {</div>\r\n" - "<div>- /* TODO: AVX512 adds support for MO_16. */</div>\r\n" - "<div>+ /* TODO: AVX512 adds support for MO_UW. */</div>\r\n" - "<div> OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ</div>\r\n" - "<div> };</div>\r\n" - "<div> static int const sarv_insn[4] = {</div>\r\n" - "<div>- /* TODO: AVX512 adds support for MO_16, MO_64. */</div>\r\n" - "<div>+ /* TODO: AVX512 adds support for MO_UW, MO_64. */</div>\r\n" - "<div> OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2</div>\r\n" - "<div> };</div>\r\n" - "<div> static int const shls_insn[4] = {</div>\r\n" - "<div>@@ -2925,7 +2925,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> sub = args[3];</div>\r\n" - "<div> goto gen_simd_imm8;</div>\r\n" - "<div> case INDEX_op_x86_blend_vec:</div>\r\n" - "<div>- if (vece == MO_16) {</div>\r\n" - "<div>+ if (vece == MO_UW) {</div>\r\n" - "<div> insn = OPC_PBLENDW;</div>\r\n" - "<div> } else if (vece == MO_32) {</div>\r\n" - "<div> insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);</div>\r\n" - "<div>@@ -3290,9 +3290,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_shls_vec:</div>\r\n" - "<div> case INDEX_op_shrs_vec:</div>\r\n" - "<div>- return vece >= MO_16;</div>\r\n" - "<div>+ return vece >= MO_UW;</div>\r\n" - "<div> case INDEX_op_sars_vec:</div>\r\n" - "<div>- return vece >= MO_16 && vece <= MO_32;</div>\r\n" - "<div>+ return vece >= MO_UW && vece <= MO_32;</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_shlv_vec:</div>\r\n" - "<div> case INDEX_op_shrv_vec:</div>\r\n" - "<div>@@ -3314,7 +3314,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> case INDEX_op_usadd_vec:</div>\r\n" - "<div> case INDEX_op_sssub_vec:</div>\r\n" - "<div> case INDEX_op_ussub_vec:</div>\r\n" - "<div>- return vece <= MO_16;</div>\r\n" - "<div>+ return vece <= MO_UW;</div>\r\n" - "<div> case INDEX_op_smin_vec:</div>\r\n" - "<div> case INDEX_op_smax_vec:</div>\r\n" - "<div> case INDEX_op_umin_vec:</div>\r\n" - "<div>@@ -3352,13 +3352,13 @@ static void expand_vec_shi(TCGType type, unsigned vece, bool shr,</div>\r\n" - "<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div>\r\n" - "<div> </div>\r\n" - "<div> if (shr) {</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_16, t1, t1, imm + 8);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_16, t2, t2, imm + 8);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, imm + 8);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UW, t2, t2, imm + 8);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- tcg_gen_shli_vec(MO_16, t1, t1, imm + 8);</div>\r\n" - "<div>- tcg_gen_shli_vec(MO_16, t2, t2, imm + 8);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_16, t1, t1, 8);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_16, t2, t2, 8);</div>\r\n" - "<div>+ tcg_gen_shli_vec(MO_UW, t1, t1, imm + 8);</div>\r\n" - "<div>+ tcg_gen_shli_vec(MO_UW, t2, t2, imm + 8);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, 8);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UW, t2, t2, 8);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div>\r\n" - "<div>@@ -3381,8 +3381,8 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div>\r\n" - "<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div>\r\n" - "<div> vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));</div>\r\n" - "<div>- tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);</div>\r\n" - "<div>- tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);</div>\r\n" - "<div>+ tcg_gen_sari_vec(MO_UW, t1, t1, imm + 8);</div>\r\n" - "<div>+ tcg_gen_sari_vec(MO_UW, t2, t2, imm + 8);</div>\r\n" - "<div> vec_gen_3(INDEX_op_x86_packss_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div>@@ -3446,8 +3446,8 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div>\r\n" - "<div> tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));</div>\r\n" - "<div> vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));</div>\r\n" - "<div>- tcg_gen_mul_vec(MO_16, t1, t1, t2);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_16, t1, t1, 8);</div>\r\n" - "<div>+ tcg_gen_mul_vec(MO_UW, t1, t1, t2);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, 8);</div>\r\n" - "<div> vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1));</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div>@@ -3469,10 +3469,10 @@ static void expand_vec_mul(TCGType type, unsigned vece,</div>\r\n" - "<div> tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));</div>\r\n" - "<div> vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));</div>\r\n" - "<div>- tcg_gen_mul_vec(MO_16, t1, t1, t2);</div>\r\n" - "<div>- tcg_gen_mul_vec(MO_16, t3, t3, t4);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_16, t1, t1, 8);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_16, t3, t3, 8);</div>\r\n" - "<div>+ tcg_gen_mul_vec(MO_UW, t1, t1, t2);</div>\r\n" - "<div>+ tcg_gen_mul_vec(MO_UW, t3, t3, t4);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UW, t1, t1, 8);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UW, t3, t3, 8);</div>\r\n" - "<div> vec_gen_3(INDEX_op_x86_packus_vec, type, MO_UB,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3));</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>index c6d13ea..1780cb1 100644</div>\r\n" - "<div>--- a/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>@@ -1383,7 +1383,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -1570,12 +1570,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SB, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_16 | MO_BSWAP:</div>\r\n" - "<div>+ case MO_UW | MO_BSWAP:</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);</div>\r\n" - "<div> tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);</div>\r\n" - "<div> lo = TCG_TMP1;</div>\r\n" - "<div> /* FALLTHRU */</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SH, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>index 9c60c0f..20bc19d 100644</div>\r\n" - "<div>--- a/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>@@ -1104,7 +1104,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_out_ext8u(s, a2, a2);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_out_ext16u(s, a2, a2);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -1219,7 +1219,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_out_opc_store(s, OPC_SB, base, lo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_out_opc_store(s, OPC_SH, base, lo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>index 479ee2e..85550b5 100644</div>\r\n" - "<div>--- a/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>@@ -885,7 +885,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_out_arithi(s, r, r, 0xff, ARITH_AND);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_out_arithi(s, r, r, 16, SHIFT_SLL);</div>\r\n" - "<div> tcg_out_arithi(s, r, r, 16, SHIFT_SRL);</div>\r\n" - "<div> break;</div>\r\n" - "<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>index 9658c36..da409f5 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-gvec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>@@ -308,7 +308,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> return 0x0101010101010101ull * (uint8_t)c;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> return 0x0001000100010001ull * (uint16_t)c;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div> return 0x0000000100000001ull * (uint32_t)c;</div>\r\n" - "<div>@@ -327,7 +327,7 @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div>\r\n" - "<div> tcg_gen_ext8u_i32(out, in);</div>\r\n" - "<div> tcg_gen_muli_i32(out, out, 0x01010101);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_deposit_i32(out, in, in, 16, 16);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div>@@ -345,7 +345,7 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div>\r\n" - "<div> tcg_gen_ext8u_i64(out, in);</div>\r\n" - "<div> tcg_gen_muli_i64(out, out, 0x0101010101010101ull);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_ext16u_i64(out, in);</div>\r\n" - "<div> tcg_gen_muli_i64(out, out, 0x0001000100010001ull);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -558,7 +558,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> tcg_gen_extrl_i64_i32(t_32, in_64);</div>\r\n" - "<div> } else if (vece == MO_UB) {</div>\r\n" - "<div> tcg_gen_movi_i32(t_32, in_c & 0xff);</div>\r\n" - "<div>- } else if (vece == MO_16) {</div>\r\n" - "<div>+ } else if (vece == MO_UW) {</div>\r\n" - "<div> tcg_gen_movi_i32(t_32, in_c & 0xffff);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_movi_i32(t_32, in_c);</div>\r\n" - "<div>@@ -1459,7 +1459,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> tcg_gen_ld8u_i32(in, cpu_env, aofs);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_ld16u_i32(in, cpu_env, aofs);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -1526,7 +1526,7 @@ void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> uint32_t maxsz, uint16_t x)</div>\r\n" - "<div> {</div>\r\n" - "<div> check_size_align(oprsz, maxsz, dofs);</div>\r\n" - "<div>- do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div>+ do_dup(MO_UW, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div>@@ -1579,7 +1579,7 @@ void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));</div>\r\n" - "<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UW, 0x8000));</div>\r\n" - "<div> gen_addv_mask(d, a, b, m);</div>\r\n" - "<div> tcg_temp_free_i64(m);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -1613,7 +1613,7 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_add16,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_add_i32,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_add32,</div>\r\n" - "<div>@@ -1644,7 +1644,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_adds16,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_add_i32,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_adds32,</div>\r\n" - "<div>@@ -1685,7 +1685,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_subs16,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_sub_i32,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_subs32,</div>\r\n" - "<div>@@ -1732,7 +1732,7 @@ void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));</div>\r\n" - "<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UW, 0x8000));</div>\r\n" - "<div> gen_subv_mask(d, a, b, m);</div>\r\n" - "<div> tcg_temp_free_i64(m);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -1764,7 +1764,7 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sub16,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_sub_i32,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sub32,</div>\r\n" - "<div>@@ -1795,7 +1795,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_mul16,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_mul_i32,</div>\r\n" - "<div> .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_mul32,</div>\r\n" - "<div>@@ -1824,7 +1824,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_muls16,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_mul_i32,</div>\r\n" - "<div> .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_muls32,</div>\r\n" - "<div>@@ -1862,7 +1862,7 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_ssadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ssadd16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fniv = tcg_gen_ssadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ssadd32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1888,7 +1888,7 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_sssub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sssub16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fniv = tcg_gen_sssub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sssub32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1930,7 +1930,7 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_usadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_usadd16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_usadd_i32,</div>\r\n" - "<div> .fniv = tcg_gen_usadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_usadd32,</div>\r\n" - "<div>@@ -1974,7 +1974,7 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_ussub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ussub16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_ussub_i32,</div>\r\n" - "<div> .fniv = tcg_gen_ussub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ussub32,</div>\r\n" - "<div>@@ -2002,7 +2002,7 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_smin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smin16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_smin_i32,</div>\r\n" - "<div> .fniv = tcg_gen_smin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smin32,</div>\r\n" - "<div>@@ -2030,7 +2030,7 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_umin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umin16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_umin_i32,</div>\r\n" - "<div> .fniv = tcg_gen_umin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umin32,</div>\r\n" - "<div>@@ -2058,7 +2058,7 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_smax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smax16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_smax_i32,</div>\r\n" - "<div> .fniv = tcg_gen_smax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smax32,</div>\r\n" - "<div>@@ -2086,7 +2086,7 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_umax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umax16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_umax_i32,</div>\r\n" - "<div> .fniv = tcg_gen_umax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umax32,</div>\r\n" - "<div>@@ -2127,7 +2127,7 @@ void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));</div>\r\n" - "<div>+ TCGv_i64 m = tcg_const_i64(dup_const(MO_UW, 0x8000));</div>\r\n" - "<div> gen_negv_mask(d, b, m);</div>\r\n" - "<div> tcg_temp_free_i64(m);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2160,7 +2160,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_neg_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_neg16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_neg_i32,</div>\r\n" - "<div> .fniv = tcg_gen_neg_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_neg32,</div>\r\n" - "<div>@@ -2206,7 +2206,7 @@ static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b)</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_absv_mask(d, b, MO_16);</div>\r\n" - "<div>+ gen_absv_mask(d, b, MO_UW);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div>@@ -2223,7 +2223,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_abs_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_abs16,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_abs_i32,</div>\r\n" - "<div> .fniv = tcg_gen_abs_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_abs32,</div>\r\n" - "<div>@@ -2461,7 +2461,7 @@ void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_16, 0xffff << c);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UW, 0xffff << c);</div>\r\n" - "<div> tcg_gen_shli_i64(d, a, c);</div>\r\n" - "<div> tcg_gen_andi_i64(d, d, mask);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2480,7 +2480,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shli_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl16i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_shli_i32,</div>\r\n" - "<div> .fniv = tcg_gen_shli_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl32i,</div>\r\n" - "<div>@@ -2512,7 +2512,7 @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t mask = dup_const(MO_16, 0xffff >> c);</div>\r\n" - "<div>+ uint64_t mask = dup_const(MO_UW, 0xffff >> c);</div>\r\n" - "<div> tcg_gen_shri_i64(d, a, c);</div>\r\n" - "<div> tcg_gen_andi_i64(d, d, mask);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2531,7 +2531,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shri_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr16i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_shri_i32,</div>\r\n" - "<div> .fniv = tcg_gen_shri_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr32i,</div>\r\n" - "<div>@@ -2570,8 +2570,8 @@ void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)</div>\r\n" - "<div> {</div>\r\n" - "<div>- uint64_t s_mask = dup_const(MO_16, 0x8000 >> c);</div>\r\n" - "<div>- uint64_t c_mask = dup_const(MO_16, 0xffff >> c);</div>\r\n" - "<div>+ uint64_t s_mask = dup_const(MO_UW, 0x8000 >> c);</div>\r\n" - "<div>+ uint64_t c_mask = dup_const(MO_UW, 0xffff >> c);</div>\r\n" - "<div> TCGv_i64 s = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_shri_i64(d, a, c);</div>\r\n" - "<div>@@ -2596,7 +2596,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sari_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar16i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_sari_i32,</div>\r\n" - "<div> .fniv = tcg_gen_sari_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar32i,</div>\r\n" - "<div>@@ -2884,7 +2884,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_shlv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl16v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_shl_mod_i32,</div>\r\n" - "<div> .fniv = tcg_gen_shlv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl32v,</div>\r\n" - "<div>@@ -2947,7 +2947,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_shrv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr16v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_shr_mod_i32,</div>\r\n" - "<div> .fniv = tcg_gen_shrv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr32v,</div>\r\n" - "<div>@@ -3010,7 +3010,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_sarv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar16v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_16 },</div>\r\n" - "<div>+ .vece = MO_UW },</div>\r\n" - "<div> { .fni4 = tcg_gen_sar_mod_i32,</div>\r\n" - "<div> .fniv = tcg_gen_sarv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar32v,</div>\r\n" - "<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div>\r\n" - "<div>index d7ffc9e..b0a4d98 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-vec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-vec.c</div>\r\n" - "<div>@@ -270,7 +270,7 @@ void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)</div>\r\n" - "<div> {</div>\r\n" - "<div>- do_dupi_vec(r, MO_REG, dup_const(MO_16, a));</div>\r\n" - "<div>+ do_dupi_vec(r, MO_REG, dup_const(MO_UW, a));</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)</div>\r\n" - "<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div>\r\n" - "<div>index 61eda33..21d448c 100644</div>\r\n" - "<div>--- a/tcg/tcg-op.c</div>\r\n" - "<div>+++ b/tcg/tcg-op.c</div>\r\n" - "<div>@@ -2723,7 +2723,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div> op &= ~MO_BSWAP;</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_32:</div>\r\n" - "<div> if (!is64) {</div>\r\n" - "<div>@@ -2810,7 +2810,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> </div>\r\n" - "<div> if ((orig_memop ^ memop) & MO_BSWAP) {</div>\r\n" - "<div> switch (orig_memop & MO_SIZE) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_bswap16_i32(val, val);</div>\r\n" - "<div> if (orig_memop & MO_SIGN) {</div>\r\n" - "<div> tcg_gen_ext16s_i32(val, val);</div>\r\n" - "<div>@@ -2837,7 +2837,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {</div>\r\n" - "<div> swap = tcg_temp_new_i32();</div>\r\n" - "<div> switch (memop & MO_SIZE) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_ext16u_i32(swap, val);</div>\r\n" - "<div> tcg_gen_bswap16_i32(swap, swap);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -2890,7 +2890,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> </div>\r\n" - "<div> if ((orig_memop ^ memop) & MO_BSWAP) {</div>\r\n" - "<div> switch (orig_memop & MO_SIZE) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_bswap16_i64(val, val);</div>\r\n" - "<div> if (orig_memop & MO_SIGN) {</div>\r\n" - "<div> tcg_gen_ext16s_i64(val, val);</div>\r\n" - "<div>@@ -2928,7 +2928,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {</div>\r\n" - "<div> swap = tcg_temp_new_i64();</div>\r\n" - "<div> switch (memop & MO_SIZE) {</div>\r\n" - "<div>- case MO_16:</div>\r\n" - "<div>+ case MO_UW:</div>\r\n" - "<div> tcg_gen_ext16u_i64(swap, val);</div>\r\n" - "<div> tcg_gen_bswap16_i64(swap, swap);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -3025,8 +3025,8 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64);</div>\r\n" - "<div> </div>\r\n" - "<div> static void * const table_cmpxchg[16] = {</div>\r\n" - "<div> [MO_UB] = gen_helper_atomic_cmpxchgb,</div>\r\n" - "<div>- [MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div>\r\n" - "<div>- [MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div>\r\n" - "<div>+ [MO_UW | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div>\r\n" - "<div>+ [MO_UW | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div>\r\n" - "<div> [MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div>\r\n" - "<div> [MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div>\r\n" - "<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div>\r\n" - "<div>@@ -3249,8 +3249,8 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div>\r\n" - "<div> #define GEN_ATOMIC_HELPER(NAME, OP, NEW) \\</div>\r\n" - "<div> static void * const table_##NAME[16] = { \\</div>\r\n" - "<div> [MO_UB] = gen_helper_atomic_##NAME##b, \\</div>\r\n" - "<div>- [MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \\</div>\r\n" - "<div>- [MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \\</div>\r\n" - "<div>+ [MO_UW | MO_LE] = gen_helper_atomic_##NAME##w_le, \\</div>\r\n" - "<div>+ [MO_UW | MO_BE] = gen_helper_atomic_##NAME##w_be, \\</div>\r\n" - "<div> [MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \\</div>\r\n" - "<div> [MO_32 | MO_BE] = gen_helper_atomic_##NAME##l_be, \\</div>\r\n" - "<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \\</div>\r\n" - "<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div>\r\n" - "<div>index 5636d6b..a378887 100644</div>\r\n" - "<div>--- a/tcg/tcg.h</div>\r\n" - "<div>+++ b/tcg/tcg.h</div>\r\n" - "<div>@@ -1303,7 +1303,7 @@ uint64_t dup_const(unsigned vece, uint64_t c);</div>\r\n" - "<div> #define dup_const(VECE, C) \\</div>\r\n" - "<div> (__builtin_constant_p(VECE) \\</div>\r\n" - "<div> ? ((VECE) == MO_UB ? 0x0101010101010101ull * (uint8_t)(C) \\</div>\r\n" - "<div>- : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \\</div>\r\n" - "<div>+ : (VECE) == MO_UW ? 0x0001000100010001ull * (uint16_t)(C) \\</div>\r\n" - "<div> : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \\</div>\r\n" - "<div> : dup_const(VECE, C)) \\</div>\r\n" - "<div> : dup_const(VECE, C))</div>\r\n" - "<div>-- </div>\r\n" - "<div>1.8.3.1</div>\r\n" - "<div><br>\r\n" - "<br>\r\n" - "</div>\r\n" - "<p><br>\r\n" - "</p>\r\n" - "</body>\r\n" - "</html>\r\n" -88603b8d0818ee5289ca16617b1d83de7a3ef5279dde76d600ecf6d443ac8a16 +5da4946578f33e04b9693eef8172da6f1b05e7905763aadbb5899c46ac91a6e8
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