diff for duplicates of <1563810105644.28725@bt.com> diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index 400197d..0000000 --- a/a/2.bin +++ /dev/null @@ -1,2387 +0,0 @@ -<html> -<head> -<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> -<style type="text/css" style="display:none"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style> -</head> -<body dir="ltr" style="font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;"> -<p></p> -<div><span style="font-size: 12pt;">Preparation for splitting MO_32 out from TCGMemOp into new accelerator</span><br> -</div> -<div>independent MemOp.</div> -<div><br> -</div> -<div>As MO_32 will be a value of MemOp, existing TCGMemOp comparisons and</div> -<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div> -<div><br> -</div> -<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div> -<div>---</div> -<div> target/arm/sve_helper.c | 6 +-</div> -<div> target/arm/translate-a64.c | 148 +++++++++++++++++------------------</div> -<div> target/arm/translate-sve.c | 12 +--</div> -<div> target/arm/translate-vfp.inc.c | 4 +-</div> -<div> target/arm/translate.c | 34 ++++----</div> -<div> target/i386/translate.c | 150 ++++++++++++++++++------------------</div> -<div> target/ppc/translate/vmx-impl.inc.c | 28 +++----</div> -<div> target/ppc/translate/vsx-impl.inc.c | 4 +-</div> -<div> target/s390x/translate.c | 4 +-</div> -<div> target/s390x/translate_vx.inc.c | 2 +-</div> -<div> target/s390x/vec.h | 4 +-</div> -<div> tcg/aarch64/tcg-target.inc.c | 20 ++---</div> -<div> tcg/arm/tcg-target.inc.c | 6 +-</div> -<div> tcg/i386/tcg-target.inc.c | 28 +++----</div> -<div> tcg/mips/tcg-target.inc.c | 6 +-</div> -<div> tcg/ppc/tcg-target.inc.c | 2 +-</div> -<div> tcg/riscv/tcg-target.inc.c | 2 +-</div> -<div> tcg/sparc/tcg-target.inc.c | 2 +-</div> -<div> tcg/tcg-op-gvec.c | 64 +++++++--------</div> -<div> tcg/tcg-op-vec.c | 6 +-</div> -<div> tcg/tcg-op.c | 18 ++---</div> -<div> tcg/tcg.h | 2 +-</div> -<div> 22 files changed, 276 insertions(+), 276 deletions(-)</div> -<div><br> -</div> -<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div> -<div>index f6bef3d..fa705c4 100644</div> -<div>--- a/target/arm/sve_helper.c</div> -<div>+++ b/target/arm/sve_helper.c</div> -<div>@@ -1561,7 +1561,7 @@ void HELPER(sve_cpy_m_s)(void *vd, void *vn, void *vg,</div> -<div> uint64_t *d = vd, *n = vn;</div> -<div> uint8_t *pg = vg;</div> -<div> </div> -<div>- mm = dup_const(MO_32, mm);</div> -<div>+ mm = dup_const(MO_UL, mm);</div> -<div> for (i = 0; i < opr_sz; i += 1) {</div> -<div> uint64_t nn = n[i];</div> -<div> uint64_t pp = expand_pred_s(pg[H1(i)]);</div> -<div>@@ -1612,7 +1612,7 @@ void HELPER(sve_cpy_z_s)(void *vd, void *vg, uint64_t val, uint32_t desc)</div> -<div> uint64_t *d = vd;</div> -<div> uint8_t *pg = vg;</div> -<div> </div> -<div>- val = dup_const(MO_32, val);</div> -<div>+ val = dup_const(MO_UL, val);</div> -<div> for (i = 0; i < opr_sz; i += 1) {</div> -<div> d[i] = val & expand_pred_s(pg[H1(i)]);</div> -<div> }</div> -<div>@@ -5123,7 +5123,7 @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,</div> -<div> target_ulong addr;</div> -<div> </div> -<div> /* Skip to the first true predicate. */</div> -<div>- reg_off = find_next_active(vg, 0, reg_max, MO_32);</div> -<div>+ reg_off = find_next_active(vg, 0, reg_max, MO_UL);</div> -<div> if (likely(reg_off < reg_max)) {</div> -<div> /* Perform one normal read, which will fault or not. */</div> -<div> set_helper_retaddr(ra);</div> -<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div> -<div>index 3acfccb..0b92e6d 100644</div> -<div>--- a/target/arm/translate-a64.c</div> -<div>+++ b/target/arm/translate-a64.c</div> -<div>@@ -484,7 +484,7 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)</div> -<div> {</div> -<div> TCGv_i32 v = tcg_temp_new_i32();</div> -<div> </div> -<div>- tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32));</div> -<div>+ tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_UL));</div> -<div> return v;</div> -<div> }</div> -<div> </div> -<div>@@ -999,7 +999,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> case MO_UW:</div> -<div> tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_SB:</div> -<div>@@ -1008,7 +1008,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> case MO_SW:</div> -<div> tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_32|MO_SIGN:</div> -<div>+ case MO_SL:</div> -<div> tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -1037,8 +1037,8 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div> -<div> case MO_SW:</div> -<div> tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>- case MO_32|MO_SIGN:</div> -<div>+ case MO_UL:</div> -<div>+ case MO_SL:</div> -<div> tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -1058,7 +1058,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div> -<div> case MO_UW:</div> -<div> tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -1080,7 +1080,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div> -<div> case MO_UW:</div> -<div> tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_st_i32(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -5299,7 +5299,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div> -<div> }</div> -<div> </div> -<div> switch (size) {</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (signal_all_nans) {</div> -<div> gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);</div> -<div> } else {</div> -<div>@@ -5354,7 +5354,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> switch (type) {</div> -<div> case 0:</div> -<div>- size = MO_32;</div> -<div>+ size = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div> size = MO_64;</div> -<div>@@ -5405,7 +5405,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> switch (type) {</div> -<div> case 0:</div> -<div>- size = MO_32;</div> -<div>+ size = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div> size = MO_64;</div> -<div>@@ -5471,7 +5471,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> switch (type) {</div> -<div> case 0:</div> -<div>- sz = MO_32;</div> -<div>+ sz = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div> sz = MO_64;</div> -<div>@@ -6276,7 +6276,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> switch (type) {</div> -<div> case 0:</div> -<div>- sz = MO_32;</div> -<div>+ sz = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div> sz = MO_64;</div> -<div>@@ -6581,7 +6581,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)</div> -<div> switch (type) {</div> -<div> case 0:</div> -<div> /* 32 bit */</div> -<div>- tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32));</div> -<div>+ tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_UL));</div> -<div> break;</div> -<div> case 1:</div> -<div> /* 64 bit */</div> -<div>@@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,</div> -<div> {</div> -<div> if (esize == size) {</div> -<div> int element;</div> -<div>- TCGMemOp msize = esize == 16 ? MO_UW : MO_32;</div> -<div>+ TCGMemOp msize = esize == 16 ? MO_UW : MO_UL;</div> -<div> TCGv_i32 tcg_elem;</div> -<div> </div> -<div> /* We should have one register left here */</div> -<div>@@ -7702,7 +7702,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div> -<div> size = MO_UW;</div> -<div> }</div> -<div> } else {</div> -<div>- size = extract32(size, 0, 1) ? MO_64 : MO_32;</div> -<div>+ size = extract32(size, 0, 1) ? MO_64 : MO_UL;</div> -<div> }</div> -<div> </div> -<div> if (!fp_access_check(s)) {</div> -<div>@@ -8181,7 +8181,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div> -<div> }</div> -<div> };</div> -<div> NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];</div> -<div>- TCGMemOp memop = scalar ? size : MO_32;</div> -<div>+ TCGMemOp memop = scalar ? size : MO_UL;</div> -<div> int maxpass = scalar ? 1 : is_q ? 4 : 2;</div> -<div> </div> -<div> for (pass = 0; pass < maxpass; pass++) {</div> -<div>@@ -8204,7 +8204,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div> -<div> }</div> -<div> write_fp_sreg(s, rd, tcg_op);</div> -<div> } else {</div> -<div>- write_vec_element_i32(s, tcg_op, rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_op, rd, pass, MO_UL);</div> -<div> }</div> -<div> </div> -<div> tcg_temp_free_i32(tcg_op);</div> -<div>@@ -8264,7 +8264,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div> -<div> read_vec_element_i32(s, tcg_int32, rn, pass, mop);</div> -<div> </div> -<div> switch (size) {</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (fracbits) {</div> -<div> if (is_signed) {</div> -<div> gen_helper_vfp_sltos(tcg_float, tcg_int32,</div> -<div>@@ -8337,7 +8337,7 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,</div> -<div> return;</div> -<div> }</div> -<div> } else if (immh & 4) {</div> -<div>- size = MO_32;</div> -<div>+ size = MO_UL;</div> -<div> } else if (immh & 2) {</div> -<div> size = MO_UW;</div> -<div> if (!dc_isar_feature(aa64_fp16, s)) {</div> -<div>@@ -8382,7 +8382,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div> -<div> return;</div> -<div> }</div> -<div> } else if (immh & 0x4) {</div> -<div>- size = MO_32;</div> -<div>+ size = MO_UL;</div> -<div> } else if (immh & 0x2) {</div> -<div> size = MO_UW;</div> -<div> if (!dc_isar_feature(aa64_fp16, s)) {</div> -<div>@@ -8436,7 +8436,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div> -<div> fn = gen_helper_vfp_toshh;</div> -<div> }</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (is_u) {</div> -<div> fn = gen_helper_vfp_touls;</div> -<div> } else {</div> -<div>@@ -8588,8 +8588,8 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);</div> -<div>- read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);</div> -<div>+ read_vec_element(s, tcg_op1, rn, 0, MO_SL);</div> -<div>+ read_vec_element(s, tcg_op2, rm, 0, MO_SL);</div> -<div> </div> -<div> tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);</div> -<div> gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);</div> -<div>@@ -8631,7 +8631,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)</div> -<div> case 0x9: /* SQDMLAL, SQDMLAL2 */</div> -<div> {</div> -<div> TCGv_i64 tcg_op3 = tcg_temp_new_i64();</div> -<div>- read_vec_element(s, tcg_op3, rd, 0, MO_32);</div> -<div>+ read_vec_element(s, tcg_op3, rd, 0, MO_UL);</div> -<div> gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,</div> -<div> tcg_res, tcg_op3);</div> -<div> tcg_temp_free_i64(tcg_op3);</div> -<div>@@ -8831,8 +8831,8 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div> -<div> TCGv_i32 tcg_op2 = tcg_temp_new_i32();</div> -<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);</div> -<div>- read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_UL);</div> -<div>+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_UL);</div> -<div> </div> -<div> switch (fpopcode) {</div> -<div> case 0x39: /* FMLS */</div> -<div>@@ -8840,7 +8840,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div> -<div> gen_helper_vfp_negs(tcg_op1, tcg_op1);</div> -<div> /* fall through */</div> -<div> case 0x19: /* FMLA */</div> -<div>- read_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div> -<div> gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,</div> -<div> tcg_res, fpst);</div> -<div> break;</div> -<div>@@ -8908,7 +8908,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div> -<div> write_vec_element(s, tcg_tmp, rd, pass, MO_64);</div> -<div> tcg_temp_free_i64(tcg_tmp);</div> -<div> } else {</div> -<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div> -<div> }</div> -<div> </div> -<div> tcg_temp_free_i32(tcg_res);</div> -<div>@@ -9557,7 +9557,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < maxpasses; pass++) {</div> -<div>- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op, rn, pass, MO_UL);</div> -<div> </div> -<div> switch (opcode) {</div> -<div> case 0x3c: /* URECPE */</div> -<div>@@ -9579,7 +9579,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div> -<div> if (is_scalar) {</div> -<div> write_fp_sreg(s, rd, tcg_res);</div> -<div> } else {</div> -<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div> -<div> }</div> -<div> }</div> -<div> tcg_temp_free_i32(tcg_res);</div> -<div>@@ -9693,7 +9693,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_UL);</div> -<div> tcg_temp_free_i32(tcg_res[pass]);</div> -<div> }</div> -<div> clear_vec_high(s, is_q, rd);</div> -<div>@@ -9740,8 +9740,8 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div> -<div> read_vec_element_i32(s, tcg_rn, rn, pass, size);</div> -<div> read_vec_element_i32(s, tcg_rd, rd, pass, size);</div> -<div> } else {</div> -<div>- read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);</div> -<div>- read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_rn, rn, pass, MO_UL);</div> -<div>+ read_vec_element_i32(s, tcg_rd, rd, pass, MO_UL);</div> -<div> }</div> -<div> </div> -<div> if (is_u) { /* USQADD */</div> -<div>@@ -9779,7 +9779,7 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div> -<div> write_vec_element(s, tcg_zero, rd, 0, MO_64);</div> -<div> tcg_temp_free_i64(tcg_zero);</div> -<div> }</div> -<div>- write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_rd, rd, pass, MO_UL);</div> -<div> }</div> -<div> tcg_temp_free_i32(tcg_rd);</div> -<div> tcg_temp_free_i32(tcg_rn);</div> -<div>@@ -10347,7 +10347,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div> -<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_passres;</div> -<div>- TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);</div> -<div>+ TCGMemOp memop = is_u ? MO_UL : MO_SL;</div> -<div> </div> -<div> int elt = pass + is_q * 2;</div> -<div> </div> -<div>@@ -10426,8 +10426,8 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div> -<div> TCGv_i64 tcg_passres;</div> -<div> int elt = pass + is_q * 2;</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);</div> -<div>- read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op1, rn, elt, MO_UL);</div> -<div>+ read_vec_element_i32(s, tcg_op2, rm, elt, MO_UL);</div> -<div> </div> -<div> if (accop == 0) {</div> -<div> tcg_passres = tcg_res[pass];</div> -<div>@@ -10547,7 +10547,7 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,</div> -<div> NeonGenWidenFn *widenfn = widenfns[size][is_u];</div> -<div> </div> -<div> read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>- read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_UL);</div> -<div> widenfn(tcg_op2_wide, tcg_op2);</div> -<div> tcg_temp_free_i32(tcg_op2);</div> -<div> tcg_res[pass] = tcg_temp_new_i64();</div> -<div>@@ -10603,7 +10603,7 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_UL);</div> -<div> tcg_temp_free_i32(tcg_res[pass]);</div> -<div> }</div> -<div> clear_vec_high(s, is_q, rd);</div> -<div>@@ -10860,8 +10860,8 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div> -<div> int passreg = pass < (maxpass / 2) ? rn : rm;</div> -<div> int passelt = (is_q && (pass & 1)) ? 2 : 0;</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32);</div> -<div>- read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_UL);</div> -<div>+ read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_UL);</div> -<div> tcg_res[pass] = tcg_temp_new_i32();</div> -<div> </div> -<div> switch (opcode) {</div> -<div>@@ -10925,7 +10925,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < maxpass; pass++) {</div> -<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_UL);</div> -<div> tcg_temp_free_i32(tcg_res[pass]);</div> -<div> }</div> -<div> clear_vec_high(s, is_q, rd);</div> -<div>@@ -10971,7 +10971,7 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> }</div> -<div>- handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32,</div> -<div>+ handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_UL,</div> -<div> rn, rm, rd);</div> -<div> return;</div> -<div> case 0x1b: /* FMULX */</div> -<div>@@ -11174,8 +11174,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)</div> -<div> NeonGenTwoOpFn *genfn = NULL;</div> -<div> NeonGenTwoOpEnvFn *genenvfn = NULL;</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);</div> -<div>- read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_UL);</div> -<div>+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_UL);</div> -<div> </div> -<div> switch (opcode) {</div> -<div> case 0x0: /* SHADD, UHADD */</div> -<div>@@ -11292,11 +11292,11 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)</div> -<div> tcg_gen_add_i32,</div> -<div> };</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op1, rd, pass, MO_UL);</div> -<div> fns[size](tcg_res, tcg_op1, tcg_res);</div> -<div> }</div> -<div> </div> -<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div> -<div> </div> -<div> tcg_temp_free_i32(tcg_res);</div> -<div> tcg_temp_free_i32(tcg_op1);</div> -<div>@@ -11578,7 +11578,7 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)</div> -<div> break;</div> -<div> case 0x02: /* SDOT (vector) */</div> -<div> case 0x12: /* UDOT (vector) */</div> -<div>- if (size != MO_32) {</div> -<div>+ if (size != MO_UL) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> }</div> -<div>@@ -11709,7 +11709,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div> -<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div> -<div> tcg_res[pass] = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_UL);</div> -<div> gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env);</div> -<div> tcg_temp_free_i32(tcg_op);</div> -<div> }</div> -<div>@@ -11732,7 +11732,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div> -<div> fpst, ahp);</div> -<div> }</div> -<div> for (pass = 0; pass < 4; pass++) {</div> -<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_UL);</div> -<div> tcg_temp_free_i32(tcg_res[pass]);</div> -<div> }</div> -<div> </div> -<div>@@ -11771,7 +11771,7 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div> -<div> case MO_UW:</div> -<div> tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -11900,7 +11900,7 @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)</div> -<div> NeonGenWidenFn *widenfn = widenfns[size];</div> -<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op, rn, part + pass, MO_UL);</div> -<div> tcg_res[pass] = tcg_temp_new_i64();</div> -<div> widenfn(tcg_res[pass], tcg_op);</div> -<div> tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);</div> -<div>@@ -12251,7 +12251,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div> -<div> TCGCond cond;</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op, rn, pass, MO_UL);</div> -<div> </div> -<div> if (size == 2) {</div> -<div> /* Special cases for 32 bit elements */</div> -<div>@@ -12418,7 +12418,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div> -<div> </div> -<div> tcg_temp_free_i32(tcg_res);</div> -<div> tcg_temp_free_i32(tcg_op);</div> -<div>@@ -12816,7 +12816,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> break;</div> -<div> case 0x0e: /* SDOT */</div> -<div> case 0x1e: /* UDOT */</div> -<div>- if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) {</div> -<div>+ if (is_scalar || size != MO_UL || !dc_isar_feature(aa64_dp, s)) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> }</div> -<div>@@ -12835,7 +12835,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> case 0x04: /* FMLSL */</div> -<div> case 0x18: /* FMLAL2 */</div> -<div> case 0x1c: /* FMLSL2 */</div> -<div>- if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {</div> -<div>+ if (is_scalar || size != MO_UL || !dc_isar_feature(aa64_fhm, s)) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> }</div> -<div>@@ -12855,7 +12855,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> size = MO_UW;</div> -<div> is_fp16 = true;</div> -<div> break;</div> -<div>- case MO_32: /* single precision */</div> -<div>+ case MO_UL: /* single precision */</div> -<div> case MO_64: /* double precision */</div> -<div> break;</div> -<div> default:</div> -<div>@@ -12868,7 +12868,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> /* Each indexable element is a complex pair. */</div> -<div> size += 1;</div> -<div> switch (size) {</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (h && !is_q) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div>@@ -12902,7 +12902,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> case MO_UW:</div> -<div> index = h << 2 | l << 1 | m;</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> index = h << 1 | l;</div> -<div> rm |= m << 4;</div> -<div> break;</div> -<div>@@ -13038,7 +13038,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div> -<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_UL);</div> -<div> </div> -<div> switch (16 * u + opcode) {</div> -<div> case 0x08: /* MUL */</div> -<div>@@ -13060,7 +13060,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> if (opcode == 0x8) {</div> -<div> break;</div> -<div> }</div> -<div>- read_vec_element_i32(s, tcg_op, rd, pass, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op, rd, pass, MO_UL);</div> -<div> genfn = fns[size - 1][is_sub];</div> -<div> genfn(tcg_res, tcg_op, tcg_res);</div> -<div> break;</div> -<div>@@ -13068,7 +13068,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> case 0x05: /* FMLS */</div> -<div> case 0x01: /* FMLA */</div> -<div> read_vec_element_i32(s, tcg_res, rd, pass,</div> -<div>- is_scalar ? size : MO_32);</div> -<div>+ is_scalar ? size : MO_UL);</div> -<div> switch (size) {</div> -<div> case 1:</div> -<div> if (opcode == 0x5) {</div> -<div>@@ -13153,7 +13153,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> break;</div> -<div> case 0x1d: /* SQRDMLAH */</div> -<div> read_vec_element_i32(s, tcg_res, rd, pass,</div> -<div>- is_scalar ? size : MO_32);</div> -<div>+ is_scalar ? size : MO_UL);</div> -<div> if (size == 1) {</div> -<div> gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,</div> -<div> tcg_op, tcg_idx, tcg_res);</div> -<div>@@ -13164,7 +13164,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> break;</div> -<div> case 0x1f: /* SQRDMLSH */</div> -<div> read_vec_element_i32(s, tcg_res, rd, pass,</div> -<div>- is_scalar ? size : MO_32);</div> -<div>+ is_scalar ? size : MO_UL);</div> -<div> if (size == 1) {</div> -<div> gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,</div> -<div> tcg_op, tcg_idx, tcg_res);</div> -<div>@@ -13180,7 +13180,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> if (is_scalar) {</div> -<div> write_fp_sreg(s, rd, tcg_res);</div> -<div> } else {</div> -<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div> -<div> }</div> -<div> </div> -<div> tcg_temp_free_i32(tcg_op);</div> -<div>@@ -13194,7 +13194,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i64 tcg_res[2];</div> -<div> int pass;</div> -<div> bool satop = extract32(opcode, 0, 1);</div> -<div>- TCGMemOp memop = MO_32;</div> -<div>+ TCGMemOp memop = MO_UL;</div> -<div> </div> -<div> if (satop || !u) {</div> -<div> memop |= MO_SIGN;</div> -<div>@@ -13288,7 +13288,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> read_vec_element_i32(s, tcg_op, rn, pass, size);</div> -<div> } else {</div> -<div> read_vec_element_i32(s, tcg_op, rn,</div> -<div>- pass + (is_q * 2), MO_32);</div> -<div>+ pass + (is_q * 2), MO_UL);</div> -<div> }</div> -<div> </div> -<div> tcg_res[pass] = tcg_temp_new_i64();</div> -<div>@@ -13780,19 +13780,19 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)</div> -<div> tcg_res = tcg_temp_new_i32();</div> -<div> tcg_zero = tcg_const_i32(0);</div> -<div> </div> -<div>- read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);</div> -<div>- read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);</div> -<div>- read_vec_element_i32(s, tcg_op3, ra, 3, MO_32);</div> -<div>+ read_vec_element_i32(s, tcg_op1, rn, 3, MO_UL);</div> -<div>+ read_vec_element_i32(s, tcg_op2, rm, 3, MO_UL);</div> -<div>+ read_vec_element_i32(s, tcg_op3, ra, 3, MO_UL);</div> -<div> </div> -<div> tcg_gen_rotri_i32(tcg_res, tcg_op1, 20);</div> -<div> tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2);</div> -<div> tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3);</div> -<div> tcg_gen_rotri_i32(tcg_res, tcg_res, 25);</div> -<div> </div> -<div>- write_vec_element_i32(s, tcg_zero, rd, 0, MO_32);</div> -<div>- write_vec_element_i32(s, tcg_zero, rd, 1, MO_32);</div> -<div>- write_vec_element_i32(s, tcg_zero, rd, 2, MO_32);</div> -<div>- write_vec_element_i32(s, tcg_res, rd, 3, MO_32);</div> -<div>+ write_vec_element_i32(s, tcg_zero, rd, 0, MO_UL);</div> -<div>+ write_vec_element_i32(s, tcg_zero, rd, 1, MO_UL);</div> -<div>+ write_vec_element_i32(s, tcg_zero, rd, 2, MO_UL);</div> -<div>+ write_vec_element_i32(s, tcg_res, rd, 3, MO_UL);</div> -<div> </div> -<div> tcg_temp_free_i32(tcg_op1);</div> -<div> tcg_temp_free_i32(tcg_op2);</div> -<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div> -<div>index 2bc1bd1..f7c891d 100644</div> -<div>--- a/target/arm/translate-sve.c</div> -<div>+++ b/target/arm/translate-sve.c</div> -<div>@@ -1693,7 +1693,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div> -<div> tcg_temp_free_i32(t32);</div> -<div> break;</div> -<div> </div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> t64 = tcg_temp_new_i64();</div> -<div> if (d) {</div> -<div> tcg_gen_neg_i64(t64, val);</div> -<div>@@ -3320,7 +3320,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_sve_subri_s,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32,</div> -<div>+ .vece = MO_UL,</div> -<div> .scalar_first = true },</div> -<div> { .fni8 = tcg_gen_sub_i64,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div>@@ -5258,7 +5258,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)</div> -<div> }</div> -<div> </div> -<div> switch (a->esz) {</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> fn = gather_load_fn32[be][a->ff][a->xs][a->u][a->msz];</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -5286,7 +5286,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)</div> -<div> }</div> -<div> </div> -<div> switch (a->esz) {</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> fn = gather_load_fn32[be][a->ff][0][a->u][a->msz];</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -5364,7 +5364,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)</div> -<div> return true;</div> -<div> }</div> -<div> switch (a->esz) {</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> fn = scatter_store_fn32[be][a->xs][a->msz];</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -5392,7 +5392,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)</div> -<div> }</div> -<div> </div> -<div> switch (a->esz) {</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> fn = scatter_store_fn32[be][0][a->msz];</div> -<div> break;</div> -<div> case MO_64:</div> -<div>diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c</div> -<div>index 549874c..5e0cd63 100644</div> -<div>--- a/target/arm/translate-vfp.inc.c</div> -<div>+++ b/target/arm/translate-vfp.inc.c</div> -<div>@@ -46,7 +46,7 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8)</div> -<div> extract32(imm8, 0, 6);</div> -<div> imm <<= 48;</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |</div> -<div> (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |</div> -<div> (extract32(imm8, 0, 6) << 3);</div> -<div>@@ -1901,7 +1901,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>- fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));</div> -<div>+ fd = tcg_const_i32(vfp_expand_imm(MO_UL, a->imm));</div> -<div> </div> -<div> for (;;) {</div> -<div> neon_store_reg32(fd, vd);</div> -<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div> -<div>index 8d10922..5510ecd 100644</div> -<div>--- a/target/arm/translate.c</div> -<div>+++ b/target/arm/translate.c</div> -<div>@@ -1085,7 +1085,7 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)</div> -<div> tcg_gen_extu_i32_tl(addr, a32);</div> -<div> </div> -<div> /* Not needed for user-mode BE32, where we use MO_BE instead. */</div> -<div>- if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {</div> -<div>+ if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_UL) {</div> -<div> tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));</div> -<div> }</div> -<div> return addr;</div> -<div>@@ -1480,7 +1480,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div> -<div> case MO_UW:</div> -<div> tcg_gen_st16_i32(var, cpu_env, offset);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_st_i32(var, cpu_env, offset);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -1499,7 +1499,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div> -<div> case MO_UW:</div> -<div> tcg_gen_st16_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_st32_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -4272,7 +4272,7 @@ const GVecGen2i ssra_op[4] = {</div> -<div> .fniv = gen_ssra_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_ssra,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = gen_ssra64_i64,</div> -<div> .fniv = gen_ssra_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>@@ -4330,7 +4330,7 @@ const GVecGen2i usra_op[4] = {</div> -<div> .fniv = gen_usra_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_usra,</div> -<div>- .vece = MO_32, },</div> -<div>+ .vece = MO_UL, },</div> -<div> { .fni8 = gen_usra64_i64,</div> -<div> .fniv = gen_usra_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>@@ -4410,7 +4410,7 @@ const GVecGen2i sri_op[4] = {</div> -<div> .fniv = gen_shr_ins_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sri,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = gen_shr64_ins_i64,</div> -<div> .fniv = gen_shr_ins_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>@@ -4488,7 +4488,7 @@ const GVecGen2i sli_op[4] = {</div> -<div> .fniv = gen_shl_ins_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sli,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = gen_shl64_ins_i64,</div> -<div> .fniv = gen_shl_ins_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>@@ -4584,7 +4584,7 @@ const GVecGen3 mla_op[4] = {</div> -<div> .fniv = gen_mla_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mla,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = gen_mla64_i64,</div> -<div> .fniv = gen_mla_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>@@ -4608,7 +4608,7 @@ const GVecGen3 mls_op[4] = {</div> -<div> .fniv = gen_mls_vec,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mls,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = gen_mls64_i64,</div> -<div> .fniv = gen_mls_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>@@ -4653,7 +4653,7 @@ const GVecGen3 cmtst_op[4] = {</div> -<div> { .fni4 = gen_cmtst_i32,</div> -<div> .fniv = gen_cmtst_vec,</div> -<div> .opt_opc = vecop_list_cmtst,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = gen_cmtst_i64,</div> -<div> .fniv = gen_cmtst_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>@@ -4691,7 +4691,7 @@ const GVecGen4 uqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqadd_s,</div> -<div> .write_aofs = true,</div> -<div> .opt_opc = vecop_list_uqadd,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fniv = gen_uqadd_vec,</div> -<div> .fno = gen_helper_gvec_uqadd_d,</div> -<div> .write_aofs = true,</div> -<div>@@ -4729,7 +4729,7 @@ const GVecGen4 sqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqadd_s,</div> -<div> .opt_opc = vecop_list_sqadd,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fniv = gen_sqadd_vec,</div> -<div> .fno = gen_helper_gvec_sqadd_d,</div> -<div> .opt_opc = vecop_list_sqadd,</div> -<div>@@ -4767,7 +4767,7 @@ const GVecGen4 uqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqsub_s,</div> -<div> .opt_opc = vecop_list_uqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fniv = gen_uqsub_vec,</div> -<div> .fno = gen_helper_gvec_uqsub_d,</div> -<div> .opt_opc = vecop_list_uqsub,</div> -<div>@@ -4805,7 +4805,7 @@ const GVecGen4 sqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqsub_s,</div> -<div> .opt_opc = vecop_list_sqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fniv = gen_sqsub_vec,</div> -<div> .fno = gen_helper_gvec_sqsub_d,</div> -<div> .opt_opc = vecop_list_sqsub,</div> -<div>@@ -5798,10 +5798,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div> -<div> /* The immediate value has already been inverted,</div> -<div> * so BIC becomes AND.</div> -<div> */</div> -<div>- tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,</div> -<div>+ tcg_gen_gvec_andi(MO_UL, reg_ofs, reg_ofs, imm,</div> -<div> vec_size, vec_size);</div> -<div> } else {</div> -<div>- tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,</div> -<div>+ tcg_gen_gvec_ori(MO_UL, reg_ofs, reg_ofs, imm,</div> -<div> vec_size, vec_size);</div> -<div> }</div> -<div> } else {</div> -<div>@@ -6879,7 +6879,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div> -<div> size = MO_UW;</div> -<div> element = (insn >> 18) & 3;</div> -<div> } else {</div> -<div>- size = MO_32;</div> -<div>+ size = MO_UL;</div> -<div> element = (insn >> 19) & 1;</div> -<div> }</div> -<div> tcg_gen_gvec_dup_mem(size, neon_reg_offset(rd, 0),</div> -<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div> -<div>index 0535bae..0e863d4 100644</div> -<div>--- a/target/i386/translate.c</div> -<div>+++ b/target/i386/translate.c</div> -<div>@@ -332,16 +332,16 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div> -<div> /* Select the size of the stack pointer. */</div> -<div> static inline TCGMemOp mo_stacksize(DisasContext *s)</div> -<div> {</div> -<div>- return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div> -<div>+ return CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div> -<div> }</div> -<div> </div> -<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div> -<div> static inline TCGMemOp mo_64_32(TCGMemOp ot)</div> -<div> {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- return ot == MO_64 ? MO_64 : MO_32;</div> -<div>+ return ot == MO_64 ? MO_64 : MO_UL;</div> -<div> #else</div> -<div>- return MO_32;</div> -<div>+ return MO_UL;</div> -<div> #endif</div> -<div> }</div> -<div> </div> -<div>@@ -356,7 +356,7 @@ static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div> -<div> Used for decoding operand size of port opcodes. */</div> -<div> static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div> -<div> {</div> -<div>- return b & 1 ? (ot == MO_UW ? MO_UW : MO_32) : MO_UB;</div> -<div>+ return b & 1 ? (ot == MO_UW ? MO_UW : MO_UL) : MO_UB;</div> -<div> }</div> -<div> </div> -<div> static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div>@@ -372,7 +372,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div> case MO_UW:</div> -<div> tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> /* For x86_64, this sets the higher half of register to zero.</div> -<div> For i386, this is equivalent to a mov. */</div> -<div> tcg_gen_ext32u_tl(cpu_regs[reg], t0);</div> -<div>@@ -463,7 +463,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div> -<div> }</div> -<div> break;</div> -<div> #endif</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> /* 32 bit address */</div> -<div> if (ovr_seg < 0 && s->addseg) {</div> -<div> ovr_seg = def_seg;</div> -<div>@@ -538,7 +538,7 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div> -<div> }</div> -<div> return dst;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (sign) {</div> -<div> tcg_gen_ext32s_tl(dst, src);</div> -<div> } else {</div> -<div>@@ -586,7 +586,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div> -<div> case MO_UW:</div> -<div> gen_helper_inw(v, cpu_env, n);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_helper_inl(v, cpu_env, n);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -603,7 +603,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div> -<div> case MO_UW:</div> -<div> gen_helper_outw(cpu_env, v, n);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_helper_outl(cpu_env, v, n);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -625,7 +625,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div> -<div> case MO_UW:</div> -<div> gen_helper_check_iow(cpu_env, s->tmp2_i32);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_helper_check_iol(cpu_env, s->tmp2_i32);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -1077,7 +1077,7 @@ static TCGLabel *gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)</div> -<div> </div> -<div> static inline void gen_stos(DisasContext *s, TCGMemOp ot)</div> -<div> {</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div> -<div> gen_string_movl_A0_EDI(s);</div> -<div> gen_op_st_v(s, ot, s->T0, s->A0);</div> -<div> gen_op_movl_T0_Dshift(s, ot);</div> -<div>@@ -1568,7 +1568,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div> -<div> goto do_long;</div> -<div> do_long:</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);</div> -<div> if (is_right) {</div> -<div>@@ -1644,7 +1644,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> if (op2 != 0) {</div> -<div> switch (ot) {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> if (is_right) {</div> -<div> tcg_gen_rotri_i32(s->tmp2_i32, s->tmp2_i32, op2);</div> -<div>@@ -1725,7 +1725,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> case MO_UW:</div> -<div> gen_helper_rcrw(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_helper_rcrl(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>@@ -1744,7 +1744,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> case MO_UW:</div> -<div> gen_helper_rclw(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_helper_rcll(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>@@ -1791,7 +1791,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> }</div> -<div> /* FALLTHRU */</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> /* Concatenate the two 32-bit values and use a 64-bit shift. */</div> -<div> tcg_gen_subi_tl(s->tmp0, count, 1);</div> -<div> if (is_right) {</div> -<div>@@ -1984,7 +1984,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,</div> -<div> </div> -<div> switch (s->aflag) {</div> -<div> case MO_64:</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> havesib = 0;</div> -<div> if (rm == 4) {</div> -<div> int code = x86_ldub_code(env, s);</div> -<div>@@ -2190,7 +2190,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div> -<div> case MO_UW:</div> -<div> ret = x86_lduw_code(env, s);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> #ifdef TARGET_X86_64</div> -<div> case MO_64:</div> -<div> #endif</div> -<div>@@ -2204,7 +2204,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div> -<div> </div> -<div> static inline int insn_const_size(TCGMemOp ot)</div> -<div> {</div> -<div>- if (ot <= MO_32) {</div> -<div>+ if (ot <= MO_UL) {</div> -<div> return 1 << ot;</div> -<div> } else {</div> -<div> return 4;</div> -<div>@@ -2400,12 +2400,12 @@ static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)</div> -<div> </div> -<div> static inline void gen_stack_A0(DisasContext *s)</div> -<div> {</div> -<div>- gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_UW, cpu_regs[R_ESP], R_SS, -1);</div> -<div>+ gen_lea_v_seg(s, s->ss32 ? MO_UL : MO_UW, cpu_regs[R_ESP], R_SS, -1);</div> -<div> }</div> -<div> </div> -<div> static void gen_pusha(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div> -<div>+ TCGMemOp s_ot = s->ss32 ? MO_UL : MO_UW;</div> -<div> TCGMemOp d_ot = s->dflag;</div> -<div> int size = 1 << d_ot;</div> -<div> int i;</div> -<div>@@ -2421,7 +2421,7 @@ static void gen_pusha(DisasContext *s)</div> -<div> </div> -<div> static void gen_popa(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div> -<div>+ TCGMemOp s_ot = s->ss32 ? MO_UL : MO_UW;</div> -<div> TCGMemOp d_ot = s->dflag;</div> -<div> int size = 1 << d_ot;</div> -<div> int i;</div> -<div>@@ -2443,7 +2443,7 @@ static void gen_popa(DisasContext *s)</div> -<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div> -<div> {</div> -<div> TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div> -<div>+ TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div> -<div> int size = 1 << d_ot;</div> -<div> </div> -<div> /* Push BP; compute FrameTemp into T1. */</div> -<div>@@ -3145,7 +3145,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> } else {</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State,</div> -<div> xmm_regs[reg].ZMM_L(0)));</div> -<div>- gen_op_st_v(s, MO_32, s->T0, s->A0);</div> -<div>+ gen_op_st_v(s, MO_UL, s->T0, s->A0);</div> -<div> }</div> -<div> break;</div> -<div> case 0x6e: /* movd mm, ea */</div> -<div>@@ -3157,7 +3157,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> } else</div> -<div> #endif</div> -<div> {</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 0);</div> -<div> tcg_gen_addi_ptr(s->ptr0, cpu_env,</div> -<div> offsetof(CPUX86State,fpregs[reg].mmx));</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div>@@ -3174,7 +3174,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> } else</div> -<div> #endif</div> -<div> {</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 0);</div> -<div> tcg_gen_addi_ptr(s->ptr0, cpu_env,</div> -<div> offsetof(CPUX86State,xmm_regs[reg]));</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div>@@ -3211,7 +3211,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> case 0x210: /* movss xmm, ea */</div> -<div> if (mod != 3) {</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div>- gen_op_ld_v(s, MO_32, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UL, s->T0, s->A0);</div> -<div> tcg_gen_st32_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State, xmm_regs[reg].ZMM_L(0)));</div> -<div> tcg_gen_movi_tl(s->T0, 0);</div> -<div>@@ -3346,7 +3346,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> {</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 1);</div> -<div> }</div> -<div> break;</div> -<div> case 0x17e: /* movd ea, xmm */</div> -<div>@@ -3360,7 +3360,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> {</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 1);</div> -<div> }</div> -<div> break;</div> -<div> case 0x27e: /* movq xmm, ea */</div> -<div>@@ -3405,7 +3405,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State, xmm_regs[reg].ZMM_L(0)));</div> -<div>- gen_op_st_v(s, MO_32, s->T0, s->A0);</div> -<div>+ gen_op_st_v(s, MO_UL, s->T0, s->A0);</div> -<div> } else {</div> -<div> rm = (modrm & 7) | REX_B(s);</div> -<div> gen_op_movl(s, offsetof(CPUX86State, xmm_regs[rm].ZMM_L(0)),</div> -<div>@@ -3530,7 +3530,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div> -<div> op1_offset = offsetof(CPUX86State,xmm_regs[reg]);</div> -<div> tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);</div> -<div>- if (ot == MO_32) {</div> -<div>+ if (ot == MO_UL) {</div> -<div> SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> sse_fn_epi(cpu_env, s->ptr0, s->tmp2_i32);</div> -<div>@@ -3584,7 +3584,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> if ((b >> 8) & 1) {</div> -<div> gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_Q(0)));</div> -<div> } else {</div> -<div>- gen_op_ld_v(s, MO_32, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UL, s->T0, s->A0);</div> -<div> tcg_gen_st32_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State, xmm_t0.ZMM_L(0)));</div> -<div> }</div> -<div>@@ -3594,7 +3594,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> op2_offset = offsetof(CPUX86State,xmm_regs[rm]);</div> -<div> }</div> -<div> tcg_gen_addi_ptr(s->ptr0, cpu_env, op2_offset);</div> -<div>- if (ot == MO_32) {</div> -<div>+ if (ot == MO_UL) {</div> -<div> SSEFunc_i_ep sse_fn_i_ep =</div> -<div> sse_op_table3bi[((b >> 7) & 2) | (b & 1)];</div> -<div> sse_fn_i_ep(s->tmp2_i32, cpu_env, s->ptr0);</div> -<div>@@ -3786,7 +3786,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> if ((b & 0xff) == 0xf0) {</div> -<div> ot = MO_UB;</div> -<div> } else if (s->dflag != MO_64) {</div> -<div>- ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div> -<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div> -<div> } else {</div> -<div> ot = MO_64;</div> -<div> }</div> -<div>@@ -3815,7 +3815,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> if (s->dflag != MO_64) {</div> -<div>- ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div> -<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div> -<div> } else {</div> -<div> ot = MO_64;</div> -<div> }</div> -<div>@@ -4026,7 +4026,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> </div> -<div> switch (ot) {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> /* If we know TL is 64-bit, and we want a 32-bit</div> -<div> result, just do everything in 64-bit arithmetic. */</div> -<div> tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]);</div> -<div>@@ -4172,7 +4172,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> }</div> -<div> break;</div> -<div> case 0x16:</div> -<div>- if (ot == MO_32) { /* pextrd */</div> -<div>+ if (ot == MO_UL) { /* pextrd */</div> -<div> tcg_gen_ld_i32(s->tmp2_i32, cpu_env,</div> -<div> offsetof(CPUX86State,</div> -<div> xmm_regs[reg].ZMM_L(val & 3)));</div> -<div>@@ -4210,7 +4210,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> break;</div> -<div> case 0x20: /* pinsrb */</div> -<div> if (mod == 3) {</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T0, rm);</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, rm);</div> -<div> } else {</div> -<div> tcg_gen_qemu_ld_tl(s->T0, s->A0,</div> -<div> s->mem_index, MO_UB);</div> -<div>@@ -4248,7 +4248,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> xmm_regs[reg].ZMM_L(3)));</div> -<div> break;</div> -<div> case 0x22:</div> -<div>- if (ot == MO_32) { /* pinsrd */</div> -<div>+ if (ot == MO_UL) { /* pinsrd */</div> -<div> if (mod == 3) {</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[rm]);</div> -<div> } else {</div> -<div>@@ -4393,7 +4393,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> switch (sz) {</div> -<div> case 2:</div> -<div> /* 32 bit access */</div> -<div>- gen_op_ld_v(s, MO_32, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_UL, s->T0, s->A0);</div> -<div> tcg_gen_st32_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State,xmm_t0.ZMM_L(0)));</div> -<div> break;</div> -<div>@@ -4630,19 +4630,19 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* In 64-bit mode, the default data size is 32-bit. Select 64-bit</div> -<div> data with rex_w, and 16-bit data with 0x66; rex_w takes precedence</div> -<div> over 0x66 if both are present. */</div> -<div>- dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_32);</div> -<div>+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_UL);</div> -<div> /* In 64-bit mode, 0x67 selects 32-bit addressing. */</div> -<div>- aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);</div> -<div>+ aflag = (prefixes & PREFIX_ADR ? MO_UL : MO_64);</div> -<div> } else {</div> -<div> /* In 16/32-bit mode, 0x66 selects the opposite data size. */</div> -<div> if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {</div> -<div>- dflag = MO_32;</div> -<div>+ dflag = MO_UL;</div> -<div> } else {</div> -<div> dflag = MO_UW;</div> -<div> }</div> -<div> /* In 16/32-bit mode, 0x67 selects the opposite addressing. */</div> -<div> if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {</div> -<div>- aflag = MO_32;</div> -<div>+ aflag = MO_UL;</div> -<div> } else {</div> -<div> aflag = MO_UW;</div> -<div> }</div> -<div>@@ -4891,7 +4891,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> set_cc_op(s, CC_OP_MULW);</div> -<div> break;</div> -<div> default:</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);</div> -<div> tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32,</div> -<div>@@ -4942,7 +4942,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> set_cc_op(s, CC_OP_MULW);</div> -<div> break;</div> -<div> default:</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);</div> -<div> tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,</div> -<div>@@ -4976,7 +4976,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_helper_divw_AX(cpu_env, s->T0);</div> -<div> break;</div> -<div> default:</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_helper_divl_EAX(cpu_env, s->T0);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>@@ -4995,7 +4995,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_helper_idivw_AX(cpu_env, s->T0);</div> -<div> break;</div> -<div> default:</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_helper_idivl_EAX(cpu_env, s->T0);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>@@ -5026,7 +5026,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* operand size for jumps is 64 bit */</div> -<div> ot = MO_64;</div> -<div> } else if (op == 3 || op == 5) {</div> -<div>- ot = dflag != MO_UW ? MO_32 + (rex_w == 1) : MO_UW;</div> -<div>+ ot = dflag != MO_UW ? MO_UL + (rex_w == 1) : MO_UW;</div> -<div> } else if (op == 6) {</div> -<div> /* default push size is 64 bit */</div> -<div> ot = mo_pushpop(s, dflag);</div> -<div>@@ -5146,15 +5146,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> switch (dflag) {</div> -<div> #ifdef TARGET_X86_64</div> -<div> case MO_64:</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div> -<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div> -<div> gen_op_mov_reg_v(s, MO_64, R_EAX, s->T0);</div> -<div> break;</div> -<div> #endif</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div> -<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div> -<div>- gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UL, R_EAX, s->T0);</div> -<div> break;</div> -<div> case MO_UW:</div> -<div> gen_op_mov_v_reg(s, MO_UB, s->T0, R_EAX);</div> -<div>@@ -5174,11 +5174,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_op_mov_reg_v(s, MO_64, R_EDX, s->T0);</div> -<div> break;</div> -<div> #endif</div> -<div>- case MO_32:</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div> -<div>+ case MO_UL:</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div> -<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div> -<div> tcg_gen_sari_tl(s->T0, s->T0, 31);</div> -<div>- gen_op_mov_reg_v(s, MO_32, R_EDX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UL, R_EDX, s->T0);</div> -<div> break;</div> -<div> case MO_UW:</div> -<div> gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div> -<div>@@ -5219,7 +5219,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, s->T1);</div> -<div> break;</div> -<div> #endif</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);</div> -<div> tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,</div> -<div>@@ -5394,7 +5394,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /**************************/</div> -<div> /* push/pop */</div> -<div> case 0x50 ... 0x57: /* push */</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T0, (b & 7) | REX_B(s));</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, (b & 7) | REX_B(s));</div> -<div> gen_push_v(s, s->T0);</div> -<div> break;</div> -<div> case 0x58 ... 0x5f: /* pop */</div> -<div>@@ -5734,7 +5734,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x1b5: /* lgs Gv */</div> -<div> op = R_GS;</div> -<div> do_lxx:</div> -<div>- ot = dflag != MO_UW ? MO_32 : MO_UW;</div> -<div>+ ot = dflag != MO_UW ? MO_UL : MO_UW;</div> -<div> modrm = x86_ldub_code(env, s);</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div> mod = (modrm >> 6) & 3;</div> -<div>@@ -6576,7 +6576,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0xe8: /* call im */</div> -<div> {</div> -<div> if (dflag != MO_UW) {</div> -<div>- tval = (int32_t)insn_get(env, s, MO_32);</div> -<div>+ tval = (int32_t)insn_get(env, s, MO_UL);</div> -<div> } else {</div> -<div> tval = (int16_t)insn_get(env, s, MO_UW);</div> -<div> }</div> -<div>@@ -6609,7 +6609,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> goto do_lcall;</div> -<div> case 0xe9: /* jmp im */</div> -<div> if (dflag != MO_UW) {</div> -<div>- tval = (int32_t)insn_get(env, s, MO_32);</div> -<div>+ tval = (int32_t)insn_get(env, s, MO_UL);</div> -<div> } else {</div> -<div> tval = (int16_t)insn_get(env, s, MO_UW);</div> -<div> }</div> -<div>@@ -6649,7 +6649,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> goto do_jcc;</div> -<div> case 0x180 ... 0x18f: /* jcc Jv */</div> -<div> if (dflag != MO_UW) {</div> -<div>- tval = (int32_t)insn_get(env, s, MO_32);</div> -<div>+ tval = (int32_t)insn_get(env, s, MO_UL);</div> -<div> } else {</div> -<div> tval = (int16_t)insn_get(env, s, MO_UW);</div> -<div> }</div> -<div>@@ -6827,7 +6827,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div> mod = (modrm >> 6) & 3;</div> -<div> rm = (modrm & 7) | REX_B(s);</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T1, reg);</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T1, reg);</div> -<div> if (mod != 3) {</div> -<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div> -<div> /* specific case: we need to add a displacement */</div> -<div>@@ -7126,10 +7126,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> } else</div> -<div> #endif</div> -<div> {</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T0, reg);</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, reg);</div> -<div> tcg_gen_ext32u_tl(s->T0, s->T0);</div> -<div> tcg_gen_bswap32_tl(s->T0, s->T0);</div> -<div>- gen_op_mov_reg_v(s, MO_32, reg, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UL, reg, s->T0);</div> -<div> }</div> -<div> break;</div> -<div> case 0xd6: /* salc */</div> -<div>@@ -7359,7 +7359,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div>- gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>+ gen_op_st_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div> -<div> break;</div> -<div> </div> -<div> case 0xc8: /* monitor */</div> -<div>@@ -7414,7 +7414,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div>- gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>+ gen_op_st_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div> -<div> break;</div> -<div> </div> -<div> case 0xd0: /* xgetbv */</div> -<div>@@ -7560,7 +7560,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div> gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div> -<div> gen_add_A0_im(s, 2);</div> -<div>- gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div> -<div> if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div>@@ -7577,7 +7577,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div> gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div> -<div> gen_add_A0_im(s, 2);</div> -<div>- gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div> -<div> if (dflag == MO_UW) {</div> -<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div> -<div> }</div> -<div>@@ -7698,7 +7698,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> rm = (modrm & 7) | REX_B(s);</div> -<div> </div> -<div> if (mod == 3) {</div> -<div>- gen_op_mov_v_reg(s, MO_32, s->T0, rm);</div> -<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, rm);</div> -<div> /* sign extend */</div> -<div> if (d_ot == MO_64) {</div> -<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div> -<div>@@ -7706,7 +7706,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_op_mov_reg_v(s, d_ot, reg, s->T0);</div> -<div> } else {</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div>- gen_op_ld_v(s, MO_32 | MO_SIGN, s->T0, s->A0);</div> -<div>+ gen_op_ld_v(s, MO_SL, s->T0, s->A0);</div> -<div> gen_op_mov_reg_v(s, d_ot, reg, s->T0);</div> -<div> }</div> -<div> } else</div> -<div>@@ -7765,7 +7765,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> TCGv t0;</div> -<div> if (!s->pe || s->vm86)</div> -<div> goto illegal_op;</div> -<div>- ot = dflag != MO_UW ? MO_32 : MO_UW;</div> -<div>+ ot = dflag != MO_UW ? MO_UL : MO_UW;</div> -<div> modrm = x86_ldub_code(env, s);</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div> gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div> -<div>@@ -8016,7 +8016,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (CODE64(s))</div> -<div> ot = MO_64;</div> -<div> else</div> -<div>- ot = MO_32;</div> -<div>+ ot = MO_UL;</div> -<div> if ((prefixes & PREFIX_LOCK) && (reg == 0) &&</div> -<div> (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {</div> -<div> reg = 8;</div> -<div>@@ -8073,7 +8073,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (CODE64(s))</div> -<div> ot = MO_64;</div> -<div> else</div> -<div>- ot = MO_32;</div> -<div>+ ot = MO_UL;</div> -<div> if (reg >= 8) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div>@@ -8168,7 +8168,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> }</div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div> tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr));</div> -<div>- gen_op_st_v(s, MO_32, s->T0, s->A0);</div> -<div>+ gen_op_st_v(s, MO_UL, s->T0, s->A0);</div> -<div> break;</div> -<div> </div> -<div> CASE_MODRM_MEM_OP(4): /* xsave */</div> -<div>@@ -8268,7 +8268,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> dst = treg, src = base;</div> -<div> }</div> -<div> </div> -<div>- if (s->dflag == MO_32) {</div> -<div>+ if (s->dflag == MO_UL) {</div> -<div> tcg_gen_ext32u_tl(dst, src);</div> -<div> } else {</div> -<div> tcg_gen_mov_tl(dst, src);</div> -<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div> -<div>index 71efef4..8aa767e 100644</div> -<div>--- a/target/ppc/translate/vmx-impl.inc.c</div> -<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div> -<div>@@ -409,27 +409,27 @@ GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \</div> -<div> GEN_VXFORM_V(vadduhm, MO_UW, tcg_gen_gvec_add, 0, 1);</div> -<div> GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div> -<div>-GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);</div> -<div>+GEN_VXFORM_V(vadduwm, MO_UL, tcg_gen_gvec_add, 0, 2);</div> -<div> GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div> -<div> GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div> -<div> GEN_VXFORM_V(vsubuhm, MO_UW, tcg_gen_gvec_sub, 0, 17);</div> -<div>-GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);</div> -<div>+GEN_VXFORM_V(vsubuwm, MO_UL, tcg_gen_gvec_sub, 0, 18);</div> -<div> GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div> -<div> GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div> -<div> GEN_VXFORM_V(vmaxuh, MO_UW, tcg_gen_gvec_umax, 1, 1);</div> -<div>-GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);</div> -<div>+GEN_VXFORM_V(vmaxuw, MO_UL, tcg_gen_gvec_umax, 1, 2);</div> -<div> GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div> -<div> GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div> -<div> GEN_VXFORM_V(vmaxsh, MO_UW, tcg_gen_gvec_smax, 1, 5);</div> -<div>-GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);</div> -<div>+GEN_VXFORM_V(vmaxsw, MO_UL, tcg_gen_gvec_smax, 1, 6);</div> -<div> GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div> -<div> GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div> -<div> GEN_VXFORM_V(vminuh, MO_UW, tcg_gen_gvec_umin, 1, 9);</div> -<div>-GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);</div> -<div>+GEN_VXFORM_V(vminuw, MO_UL, tcg_gen_gvec_umin, 1, 10);</div> -<div> GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div> -<div> GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div> -<div> GEN_VXFORM_V(vminsh, MO_UW, tcg_gen_gvec_smin, 1, 13);</div> -<div>-GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);</div> -<div>+GEN_VXFORM_V(vminsw, MO_UL, tcg_gen_gvec_smin, 1, 14);</div> -<div> GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div> -<div> GEN_VXFORM(vavgub, 1, 16);</div> -<div> GEN_VXFORM(vabsdub, 1, 16);</div> -<div>@@ -532,18 +532,18 @@ GEN_VXFORM(vmulesh, 4, 13);</div> -<div> GEN_VXFORM(vmulesw, 4, 14);</div> -<div> GEN_VXFORM_V(vslb, MO_UB, tcg_gen_gvec_shlv, 2, 4);</div> -<div> GEN_VXFORM_V(vslh, MO_UW, tcg_gen_gvec_shlv, 2, 5);</div> -<div>-GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);</div> -<div>+GEN_VXFORM_V(vslw, MO_UL, tcg_gen_gvec_shlv, 2, 6);</div> -<div> GEN_VXFORM(vrlwnm, 2, 6);</div> -<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div> -<div> GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div> -<div> GEN_VXFORM_V(vsrh, MO_UW, tcg_gen_gvec_shrv, 2, 9);</div> -<div>-GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);</div> -<div>+GEN_VXFORM_V(vsrw, MO_UL, tcg_gen_gvec_shrv, 2, 10);</div> -<div> GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div> -<div> GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div> -<div> GEN_VXFORM_V(vsrah, MO_UW, tcg_gen_gvec_sarv, 2, 13);</div> -<div>-GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);</div> -<div>+GEN_VXFORM_V(vsraw, MO_UL, tcg_gen_gvec_sarv, 2, 14);</div> -<div> GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div> -<div> GEN_VXFORM(vsrv, 2, 28);</div> -<div> GEN_VXFORM(vslv, 2, 29);</div> -<div>@@ -595,16 +595,16 @@ GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \</div> -<div> GEN_VXFORM_SAT(vadduhs, MO_UW, add, usadd, 0, 9);</div> -<div> GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vmul10euq, PPC_NONE, PPC2_ISA300)</div> -<div>-GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);</div> -<div>+GEN_VXFORM_SAT(vadduws, MO_UL, add, usadd, 0, 10);</div> -<div> GEN_VXFORM_SAT(vaddsbs, MO_UB, add, ssadd, 0, 12);</div> -<div> GEN_VXFORM_SAT(vaddshs, MO_UW, add, ssadd, 0, 13);</div> -<div>-GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);</div> -<div>+GEN_VXFORM_SAT(vaddsws, MO_UL, add, ssadd, 0, 14);</div> -<div> GEN_VXFORM_SAT(vsububs, MO_UB, sub, ussub, 0, 24);</div> -<div> GEN_VXFORM_SAT(vsubuhs, MO_UW, sub, ussub, 0, 25);</div> -<div>-GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);</div> -<div>+GEN_VXFORM_SAT(vsubuws, MO_UL, sub, ussub, 0, 26);</div> -<div> GEN_VXFORM_SAT(vsubsbs, MO_UB, sub, sssub, 0, 28);</div> -<div> GEN_VXFORM_SAT(vsubshs, MO_UW, sub, sssub, 0, 29);</div> -<div>-GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);</div> -<div>+GEN_VXFORM_SAT(vsubsws, MO_UL, sub, sssub, 0, 30);</div> -<div> GEN_VXFORM(vadduqm, 0, 4);</div> -<div> GEN_VXFORM(vaddcuq, 0, 5);</div> -<div> GEN_VXFORM3(vaddeuqm, 30, 0);</div> -<div>@@ -914,7 +914,7 @@ static void glue(gen_, name)(DisasContext *ctx) \</div> -<div> </div> -<div> GEN_VXFORM_VSPLT(vspltb, MO_UB, 6, 8);</div> -<div> GEN_VXFORM_VSPLT(vsplth, MO_UW, 6, 9);</div> -<div>-GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);</div> -<div>+GEN_VXFORM_VSPLT(vspltw, MO_UL, 6, 10);</div> -<div> GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);</div> -<div> GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);</div> -<div> GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);</div> -<div>diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c</div> -<div>index 3922686..212817e 100644</div> -<div>--- a/target/ppc/translate/vsx-impl.inc.c</div> -<div>+++ b/target/ppc/translate/vsx-impl.inc.c</div> -<div>@@ -1553,12 +1553,12 @@ static void gen_xxspltw(DisasContext *ctx)</div> -<div> </div> -<div> tofs = vsr_full_offset(rt);</div> -<div> bofs = vsr_full_offset(rb);</div> -<div>- bofs += uim << MO_32;</div> -<div>+ bofs += uim << MO_UL;</div> -<div> #ifndef HOST_WORDS_BIG_ENDIAN</div> -<div> bofs ^= 8 | 4;</div> -<div> #endif</div> -<div> </div> -<div>- tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);</div> -<div>+ tcg_gen_gvec_dup_mem(MO_UL, tofs, bofs, 16, 16);</div> -<div> }</div> -<div> </div> -<div> #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))</div> -<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div> -<div>index 415747f..9e646f1 100644</div> -<div>--- a/target/s390x/translate.c</div> -<div>+++ b/target/s390x/translate.c</div> -<div>@@ -196,7 +196,7 @@ static inline int freg64_offset(uint8_t reg)</div> -<div> static inline int freg32_offset(uint8_t reg)</div> -<div> {</div> -<div> g_assert(reg < 16);</div> -<div>- return vec_reg_offset(reg, 0, MO_32);</div> -<div>+ return vec_reg_offset(reg, 0, MO_UL);</div> -<div> }</div> -<div> </div> -<div> static TCGv_i64 load_reg(int reg)</div> -<div>@@ -2283,7 +2283,7 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o)</div> -<div> </div> -<div> /* Write back the output now, so that it happens before the</div> -<div> following branch, so that we don't need local temps. */</div> -<div>- if ((mop & MO_SIZE) == MO_32) {</div> -<div>+ if ((mop & MO_SIZE) == MO_UL) {</div> -<div> tcg_gen_deposit_i64(o->out, o->out, old, 0, 32);</div> -<div> } else {</div> -<div> tcg_gen_mov_i64(o->out, old);</div> -<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div> -<div>index 65da6b3..75d788c 100644</div> -<div>--- a/target/s390x/translate_vx.inc.c</div> -<div>+++ b/target/s390x/translate_vx.inc.c</div> -<div>@@ -48,7 +48,7 @@</div> -<div> </div> -<div> #define ES_8 MO_UB</div> -<div> #define ES_16 MO_UW</div> -<div>-#define ES_32 MO_32</div> -<div>+#define ES_32 MO_UL</div> -<div> #define ES_64 MO_64</div> -<div> #define ES_128 4</div> -<div> </div> -<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div> -<div>index 28e1b1d..f67392c 100644</div> -<div>--- a/target/s390x/vec.h</div> -<div>+++ b/target/s390x/vec.h</div> -<div>@@ -80,7 +80,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div> -<div> return s390_vec_read_element8(v, enr);</div> -<div> case MO_UW:</div> -<div> return s390_vec_read_element16(v, enr);</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> return s390_vec_read_element32(v, enr);</div> -<div> case MO_64:</div> -<div> return s390_vec_read_element64(v, enr);</div> -<div>@@ -127,7 +127,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div> -<div> case MO_UW:</div> -<div> s390_vec_write_element16(v, enr, data);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> s390_vec_write_element32(v, enr, data);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div> -<div>index 3d90c4b..dc4fd21 100644</div> -<div>--- a/tcg/aarch64/tcg-target.inc.c</div> -<div>+++ b/tcg/aarch64/tcg-target.inc.c</div> -<div>@@ -431,12 +431,12 @@ typedef enum {</div> -<div> that emits them can transform to 3.3.10 or 3.3.13. */</div> -<div> I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div> -<div> I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_UW << 30,</div> -<div>- I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,</div> -<div>+ I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_UL << 30,</div> -<div> I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div> -<div> </div> -<div> I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div> -<div> I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_UW << 30,</div> -<div>- I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,</div> -<div>+ I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_UL << 30,</div> -<div> I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div> -<div> </div> -<div> I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div> -<div>@@ -444,10 +444,10 @@ typedef enum {</div> -<div> </div> -<div> I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_UB << 30,</div> -<div> I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_UW << 30,</div> -<div>- I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,</div> -<div>+ I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_UL << 30,</div> -<div> </div> -<div>- I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,</div> -<div>- I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,</div> -<div>+ I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_UL << 30,</div> -<div>+ I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_UL << 30,</div> -<div> </div> -<div> I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,</div> -<div> I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,</div> -<div>@@ -870,7 +870,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div> -<div> </div> -<div> /*</div> -<div> * Test all bytes 0x00 or 0xff second. This can match cases that</div> -<div>- * might otherwise take 2 or 3 insns for MO_UW or MO_32 below.</div> -<div>+ * might otherwise take 2 or 3 insns for MO_UW or MO_UL below.</div> -<div> */</div> -<div> for (i = imm8 = 0; i < 8; i++) {</div> -<div> uint8_t byte = v64 >> (i * 8);</div> -<div>@@ -908,7 +908,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div> -<div> tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);</div> -<div> tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);</div> -<div> return;</div> -<div>- } else if (v64 == dup_const(MO_32, v64)) {</div> -<div>+ } else if (v64 == dup_const(MO_UL, v64)) {</div> -<div> uint32_t v32 = v64;</div> -<div> uint32_t n32 = ~v32;</div> -<div> </div> -<div>@@ -1749,7 +1749,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div> -<div> if (bswap) {</div> -<div> tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);</div> -<div> tcg_out_rev32(s, data_r, data_r);</div> -<div>- tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);</div> -<div>+ tcg_out_sxt(s, TCG_TYPE_I64, MO_UL, data_r, data_r);</div> -<div> } else {</div> -<div> tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);</div> -<div> }</div> -<div>@@ -1782,7 +1782,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div> -<div> }</div> -<div> tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (bswap && data_r != TCG_REG_XZR) {</div> -<div> tcg_out_rev32(s, TCG_REG_TMP, data_r);</div> -<div> data_r = TCG_REG_TMP;</div> -<div>@@ -2194,7 +2194,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div> -<div> break;</div> -<div> case INDEX_op_ext_i32_i64:</div> -<div> case INDEX_op_ext32s_i64:</div> -<div>- tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1);</div> -<div>+ tcg_out_sxt(s, TCG_TYPE_I64, MO_UL, a0, a1);</div> -<div> break;</div> -<div> case INDEX_op_ext8u_i64:</div> -<div> case INDEX_op_ext8u_i32:</div> -<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div> -<div>index 0bd400e..05560a2 100644</div> -<div>--- a/tcg/arm/tcg-target.inc.c</div> -<div>+++ b/tcg/arm/tcg-target.inc.c</div> -<div>@@ -1435,7 +1435,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> case MO_UW:</div> -<div> argreg = tcg_out_arg_reg16(s, argreg, datalo);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> default:</div> -<div> argreg = tcg_out_arg_reg32(s, argreg, datalo);</div> -<div> break;</div> -<div>@@ -1632,7 +1632,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div> -<div> tcg_out_st16_r(s, cond, datalo, addrlo, addend);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> default:</div> -<div> if (bswap) {</div> -<div> tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);</div> -<div>@@ -1677,7 +1677,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div> -<div> tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> default:</div> -<div> if (bswap) {</div> -<div> tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);</div> -<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div> -<div>index 31c3664..93e4c63 100644</div> -<div>--- a/tcg/i386/tcg-target.inc.c</div> -<div>+++ b/tcg/i386/tcg-target.inc.c</div> -<div>@@ -897,7 +897,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a);</div> -<div> a = r;</div> -<div> /* FALLTHRU */</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a);</div> -<div> /* imm8 operand: all output lanes selected from input lane 0. */</div> -<div> tcg_out8(s, 0);</div> -<div>@@ -924,7 +924,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> case MO_64:</div> -<div> tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset);</div> -<div> break;</div> -<div> case MO_UW:</div> -<div>@@ -2173,7 +2173,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div> -<div> tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo,</div> -<div> base, index, 0, ofs);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (bswap) {</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);</div> -<div> tcg_out_bswap32(s, scratch);</div> -<div>@@ -2927,7 +2927,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div> -<div> case INDEX_op_x86_blend_vec:</div> -<div> if (vece == MO_UW) {</div> -<div> insn = OPC_PBLENDW;</div> -<div>- } else if (vece == MO_32) {</div> -<div>+ } else if (vece == MO_UL) {</div> -<div> insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);</div> -<div> } else {</div> -<div> g_assert_not_reached();</div> -<div>@@ -3292,13 +3292,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> case INDEX_op_shrs_vec:</div> -<div> return vece >= MO_UW;</div> -<div> case INDEX_op_sars_vec:</div> -<div>- return vece >= MO_UW && vece <= MO_32;</div> -<div>+ return vece >= MO_UW && vece <= MO_UL;</div> -<div> </div> -<div> case INDEX_op_shlv_vec:</div> -<div> case INDEX_op_shrv_vec:</div> -<div>- return have_avx2 && vece >= MO_32;</div> -<div>+ return have_avx2 && vece >= MO_UL;</div> -<div> case INDEX_op_sarv_vec:</div> -<div>- return have_avx2 && vece == MO_32;</div> -<div>+ return have_avx2 && vece == MO_UL;</div> -<div> </div> -<div> case INDEX_op_mul_vec:</div> -<div> if (vece == MO_UB) {</div> -<div>@@ -3320,7 +3320,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> case INDEX_op_umin_vec:</div> -<div> case INDEX_op_umax_vec:</div> -<div> case INDEX_op_abs_vec:</div> -<div>- return vece <= MO_32;</div> -<div>+ return vece <= MO_UL;</div> -<div> </div> -<div> default:</div> -<div> return 0;</div> -<div>@@ -3396,9 +3396,9 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div> -<div> * shift (note that the ISA says shift of 32 is valid).</div> -<div> */</div> -<div> t1 = tcg_temp_new_vec(type);</div> -<div>- tcg_gen_sari_vec(MO_32, t1, v1, imm);</div> -<div>+ tcg_gen_sari_vec(MO_UL, t1, v1, imm);</div> -<div> tcg_gen_shri_vec(MO_64, v0, v1, imm);</div> -<div>- vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,</div> -<div>+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_UL,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(v0),</div> -<div> tcgv_vec_arg(t1), 0xaa);</div> -<div> tcg_temp_free_vec(t1);</div> -<div>@@ -3515,28 +3515,28 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,</div> -<div> fixup = NEED_SWAP | NEED_INV;</div> -<div> break;</div> -<div> case TCG_COND_LEU:</div> -<div>- if (vece <= MO_32) {</div> -<div>+ if (vece <= MO_UL) {</div> -<div> fixup = NEED_UMIN;</div> -<div> } else {</div> -<div> fixup = NEED_BIAS | NEED_INV;</div> -<div> }</div> -<div> break;</div> -<div> case TCG_COND_GTU:</div> -<div>- if (vece <= MO_32) {</div> -<div>+ if (vece <= MO_UL) {</div> -<div> fixup = NEED_UMIN | NEED_INV;</div> -<div> } else {</div> -<div> fixup = NEED_BIAS;</div> -<div> }</div> -<div> break;</div> -<div> case TCG_COND_GEU:</div> -<div>- if (vece <= MO_32) {</div> -<div>+ if (vece <= MO_UL) {</div> -<div> fixup = NEED_UMAX;</div> -<div> } else {</div> -<div> fixup = NEED_BIAS | NEED_SWAP | NEED_INV;</div> -<div> }</div> -<div> break;</div> -<div> case TCG_COND_LTU:</div> -<div>- if (vece <= MO_32) {</div> -<div>+ if (vece <= MO_UL) {</div> -<div> fixup = NEED_UMAX | NEED_INV;</div> -<div> } else {</div> -<div> fixup = NEED_BIAS | NEED_SWAP;</div> -<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div> -<div>index 1780cb1..a78fe87 100644</div> -<div>--- a/tcg/mips/tcg-target.inc.c</div> -<div>+++ b/tcg/mips/tcg-target.inc.c</div> -<div>@@ -1386,7 +1386,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> case MO_UW:</div> -<div> i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -1579,11 +1579,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> tcg_out_opc_imm(s, OPC_SH, lo, base, 0);</div> -<div> break;</div> -<div> </div> -<div>- case MO_32 | MO_BSWAP:</div> -<div>+ case MO_UL | MO_BSWAP:</div> -<div> tcg_out_bswap32(s, TCG_TMP3, lo);</div> -<div> lo = TCG_TMP3;</div> -<div> /* FALLTHRU */</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_out_opc_imm(s, OPC_SW, lo, base, 0);</div> -<div> break;</div> -<div> </div> -<div>diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c</div> -<div>index 852b894..835336a 100644</div> -<div>--- a/tcg/ppc/tcg-target.inc.c</div> -<div>+++ b/tcg/ppc/tcg-target.inc.c</div> -<div>@@ -1714,7 +1714,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> #endif</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);</div> -<div> /* FALLTHRU */</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);</div> -<div> break;</div> -<div> default:</div> -<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div> -<div>index 20bc19d..1905986 100644</div> -<div>--- a/tcg/riscv/tcg-target.inc.c</div> -<div>+++ b/tcg/riscv/tcg-target.inc.c</div> -<div>@@ -1222,7 +1222,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> case MO_UW:</div> -<div> tcg_out_opc_store(s, OPC_SH, base, lo, 0);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_out_opc_store(s, OPC_SW, base, lo, 0);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div> -<div>index 85550b5..ac0d3a3 100644</div> -<div>--- a/tcg/sparc/tcg-target.inc.c</div> -<div>+++ b/tcg/sparc/tcg-target.inc.c</div> -<div>@@ -889,7 +889,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div> -<div> tcg_out_arithi(s, r, r, 16, SHIFT_SLL);</div> -<div> tcg_out_arithi(s, r, r, 16, SHIFT_SRL);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (SPARC64) {</div> -<div> tcg_out_arith(s, r, r, 0, SHIFT_SRL);</div> -<div> }</div> -<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div> -<div>index da409f5..e63622c 100644</div> -<div>--- a/tcg/tcg-op-gvec.c</div> -<div>+++ b/tcg/tcg-op-gvec.c</div> -<div>@@ -310,7 +310,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div> -<div> return 0x0101010101010101ull * (uint8_t)c;</div> -<div> case MO_UW:</div> -<div> return 0x0001000100010001ull * (uint16_t)c;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> return 0x0000000100000001ull * (uint32_t)c;</div> -<div> case MO_64:</div> -<div> return c;</div> -<div>@@ -330,7 +330,7 @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div> -<div> case MO_UW:</div> -<div> tcg_gen_deposit_i32(out, in, in, 16, 16);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_mov_i32(out, in);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -349,7 +349,7 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div> -<div> tcg_gen_ext16u_i64(out, in);</div> -<div> tcg_gen_muli_i64(out, out, 0x0001000100010001ull);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_deposit_i64(out, in, in, 32, 32);</div> -<div> break;</div> -<div> case MO_64:</div> -<div>@@ -443,7 +443,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> TCGv_ptr t_ptr;</div> -<div> uint32_t i;</div> -<div> </div> -<div>- assert(vece <= (in_32 ? MO_32 : MO_64));</div> -<div>+ assert(vece <= (in_32 ? MO_UL : MO_64));</div> -<div> assert(in_32 == NULL || in_64 == NULL);</div> -<div> </div> -<div> /* If we're storing 0, expand oprsz to maxsz. */</div> -<div>@@ -485,7 +485,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> use a 64-bit operation unless the 32-bit operation would</div> -<div> be simple enough. */</div> -<div> if (TCG_TARGET_REG_BITS == 64</div> -<div>- && (vece != MO_32 || !check_size_impl(oprsz, 4))) {</div> -<div>+ && (vece != MO_UL || !check_size_impl(oprsz, 4))) {</div> -<div> t_64 = tcg_temp_new_i64();</div> -<div> tcg_gen_extu_i32_i64(t_64, in_32);</div> -<div> gen_dup_i64(vece, t_64, t_64);</div> -<div>@@ -1430,7 +1430,7 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> uint32_t maxsz, TCGv_i32 in)</div> -<div> {</div> -<div> check_size_align(oprsz, maxsz, dofs);</div> -<div>- tcg_debug_assert(vece <= MO_32);</div> -<div>+ tcg_debug_assert(vece <= MO_UL);</div> -<div> do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);</div> -<div> }</div> -<div> </div> -<div>@@ -1453,7 +1453,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs);</div> -<div> do_dup_store(type, dofs, oprsz, maxsz, t_vec);</div> -<div> tcg_temp_free_vec(t_vec);</div> -<div>- } else if (vece <= MO_32) {</div> -<div>+ } else if (vece <= MO_UL) {</div> -<div> TCGv_i32 in = tcg_temp_new_i32();</div> -<div> switch (vece) {</div> -<div> case MO_UB:</div> -<div>@@ -1519,7 +1519,7 @@ void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,</div> -<div> uint32_t maxsz, uint32_t x)</div> -<div> {</div> -<div> check_size_align(oprsz, maxsz, dofs);</div> -<div>- do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div>+ do_dup(MO_UL, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,</div> -<div>@@ -1618,7 +1618,7 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_add32,</div> -<div> .opt_opc = vecop_list_add,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_add_i64,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_add64,</div> -<div>@@ -1649,7 +1649,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_adds32,</div> -<div> .opt_opc = vecop_list_add,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_add_i64,</div> -<div> .fniv = tcg_gen_add_vec,</div> -<div> .fno = gen_helper_gvec_adds64,</div> -<div>@@ -1690,7 +1690,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_subs32,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_sub_i64,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_subs64,</div> -<div>@@ -1769,7 +1769,7 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_sub32,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_sub_i64,</div> -<div> .fniv = tcg_gen_sub_vec,</div> -<div> .fno = gen_helper_gvec_sub64,</div> -<div>@@ -1800,7 +1800,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_mul32,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_mul_i64,</div> -<div> .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_mul64,</div> -<div>@@ -1829,7 +1829,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_muls32,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_mul_i64,</div> -<div> .fniv = tcg_gen_mul_vec,</div> -<div> .fno = gen_helper_gvec_muls64,</div> -<div>@@ -1866,7 +1866,7 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_ssadd_vec,</div> -<div> .fno = gen_helper_gvec_ssadd32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fniv = tcg_gen_ssadd_vec,</div> -<div> .fno = gen_helper_gvec_ssadd64,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1892,7 +1892,7 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_sssub_vec,</div> -<div> .fno = gen_helper_gvec_sssub32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fniv = tcg_gen_sssub_vec,</div> -<div> .fno = gen_helper_gvec_sssub64,</div> -<div> .opt_opc = vecop_list,</div> -<div>@@ -1935,7 +1935,7 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_usadd_vec,</div> -<div> .fno = gen_helper_gvec_usadd32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_usadd_i64,</div> -<div> .fniv = tcg_gen_usadd_vec,</div> -<div> .fno = gen_helper_gvec_usadd64,</div> -<div>@@ -1979,7 +1979,7 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_ussub_vec,</div> -<div> .fno = gen_helper_gvec_ussub32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_ussub_i64,</div> -<div> .fniv = tcg_gen_ussub_vec,</div> -<div> .fno = gen_helper_gvec_ussub64,</div> -<div>@@ -2007,7 +2007,7 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_smin_vec,</div> -<div> .fno = gen_helper_gvec_smin32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_smin_i64,</div> -<div> .fniv = tcg_gen_smin_vec,</div> -<div> .fno = gen_helper_gvec_smin64,</div> -<div>@@ -2035,7 +2035,7 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_umin_vec,</div> -<div> .fno = gen_helper_gvec_umin32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_umin_i64,</div> -<div> .fniv = tcg_gen_umin_vec,</div> -<div> .fno = gen_helper_gvec_umin64,</div> -<div>@@ -2063,7 +2063,7 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_smax_vec,</div> -<div> .fno = gen_helper_gvec_smax32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_smax_i64,</div> -<div> .fniv = tcg_gen_smax_vec,</div> -<div> .fno = gen_helper_gvec_smax64,</div> -<div>@@ -2091,7 +2091,7 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_umax_vec,</div> -<div> .fno = gen_helper_gvec_umax32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_umax_i64,</div> -<div> .fniv = tcg_gen_umax_vec,</div> -<div> .fno = gen_helper_gvec_umax64,</div> -<div>@@ -2165,7 +2165,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_neg_vec,</div> -<div> .fno = gen_helper_gvec_neg32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_neg_i64,</div> -<div> .fniv = tcg_gen_neg_vec,</div> -<div> .fno = gen_helper_gvec_neg64,</div> -<div>@@ -2228,7 +2228,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_abs_vec,</div> -<div> .fno = gen_helper_gvec_abs32,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_abs_i64,</div> -<div> .fniv = tcg_gen_abs_vec,</div> -<div> .fno = gen_helper_gvec_abs64,</div> -<div>@@ -2485,7 +2485,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shli_vec,</div> -<div> .fno = gen_helper_gvec_shl32i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_shli_i64,</div> -<div> .fniv = tcg_gen_shli_vec,</div> -<div> .fno = gen_helper_gvec_shl64i,</div> -<div>@@ -2536,7 +2536,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shri_vec,</div> -<div> .fno = gen_helper_gvec_shr32i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_shri_i64,</div> -<div> .fniv = tcg_gen_shri_vec,</div> -<div> .fno = gen_helper_gvec_shr64i,</div> -<div>@@ -2601,7 +2601,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sari_vec,</div> -<div> .fno = gen_helper_gvec_sar32i,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_sari_i64,</div> -<div> .fniv = tcg_gen_sari_vec,</div> -<div> .fno = gen_helper_gvec_sar64i,</div> -<div>@@ -2736,7 +2736,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div> -<div> }</div> -<div> </div> -<div> /* Otherwise fall back to integral... */</div> -<div>- if (vece == MO_32 && check_size_impl(oprsz, 4)) {</div> -<div>+ if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div> -<div> expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4);</div> -<div> } else if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div> -<div> TCGv_i64 sh64 = tcg_temp_new_i64();</div> -<div>@@ -2889,7 +2889,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shlv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shl32v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_shl_mod_i64,</div> -<div> .fniv = tcg_gen_shlv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shl64v,</div> -<div>@@ -2952,7 +2952,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_shrv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shr32v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_shr_mod_i64,</div> -<div> .fniv = tcg_gen_shrv_mod_vec,</div> -<div> .fno = gen_helper_gvec_shr64v,</div> -<div>@@ -3015,7 +3015,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_sarv_mod_vec,</div> -<div> .fno = gen_helper_gvec_sar32v,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_32 },</div> -<div>+ .vece = MO_UL },</div> -<div> { .fni8 = tcg_gen_sar_mod_i64,</div> -<div> .fniv = tcg_gen_sarv_mod_vec,</div> -<div> .fno = gen_helper_gvec_sar64v,</div> -<div>@@ -3168,7 +3168,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div> -<div> case 0:</div> -<div> if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div> -<div> expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);</div> -<div>- } else if (vece == MO_32 && check_size_impl(oprsz, 4)) {</div> -<div>+ } else if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div> -<div> expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);</div> -<div> } else {</div> -<div> gen_helper_gvec_3 * const *fn = fns[cond];</div> -<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div> -<div>index b0a4d98..ff723ab 100644</div> -<div>--- a/tcg/tcg-op-vec.c</div> -<div>+++ b/tcg/tcg-op-vec.c</div> -<div>@@ -216,7 +216,7 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)</div> -<div>+#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_UL)</div> -<div> </div> -<div> static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)</div> -<div> {</div> -<div>@@ -253,7 +253,7 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)</div> -<div> void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)</div> -<div> {</div> -<div> if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {</div> -<div>- do_dupi_vec(r, MO_32, a);</div> -<div>+ do_dupi_vec(r, MO_UL, a);</div> -<div> } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {</div> -<div> do_dupi_vec(r, MO_64, a);</div> -<div> } else {</div> -<div>@@ -265,7 +265,7 @@ void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)</div> -<div> </div> -<div> void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)</div> -<div> {</div> -<div>- do_dupi_vec(r, MO_REG, dup_const(MO_32, a));</div> -<div>+ do_dupi_vec(r, MO_REG, dup_const(MO_UL, a));</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)</div> -<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div> -<div>index 21d448c..447683d 100644</div> -<div>--- a/tcg/tcg-op.c</div> -<div>+++ b/tcg/tcg-op.c</div> -<div>@@ -2725,7 +2725,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div> -<div> break;</div> -<div> case MO_UW:</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> if (!is64) {</div> -<div> op &= ~MO_SIGN;</div> -<div> }</div> -<div>@@ -2816,7 +2816,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> tcg_gen_ext16s_i32(val, val);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_bswap32_i32(val, val);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -2841,7 +2841,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> tcg_gen_ext16u_i32(swap, val);</div> -<div> tcg_gen_bswap16_i32(swap, swap);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_bswap32_i32(swap, val);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -2896,7 +2896,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> tcg_gen_ext16s_i64(val, val);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_bswap32_i64(val, val);</div> -<div> if (orig_memop & MO_SIGN) {</div> -<div> tcg_gen_ext32s_i64(val, val);</div> -<div>@@ -2932,7 +2932,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> tcg_gen_ext16u_i64(swap, val);</div> -<div> tcg_gen_bswap16_i64(swap, swap);</div> -<div> break;</div> -<div>- case MO_32:</div> -<div>+ case MO_UL:</div> -<div> tcg_gen_ext32u_i64(swap, val);</div> -<div> tcg_gen_bswap32_i64(swap, swap);</div> -<div> break;</div> -<div>@@ -3027,8 +3027,8 @@ static void * const table_cmpxchg[16] = {</div> -<div> [MO_UB] = gen_helper_atomic_cmpxchgb,</div> -<div> [MO_UW | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div> -<div> [MO_UW | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div> -<div>- [MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div> -<div>- [MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div> -<div>+ [MO_UL | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div> -<div>+ [MO_UL | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div> -<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div> -<div> WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be)</div> -<div> };</div> -<div>@@ -3251,8 +3251,8 @@ static void * const table_##NAME[16] = { \</div> -<div> [MO_UB] = gen_helper_atomic_##NAME##b, \</div> -<div> [MO_UW | MO_LE] = gen_helper_atomic_##NAME##w_le, \</div> -<div> [MO_UW | MO_BE] = gen_helper_atomic_##NAME##w_be, \</div> -<div>- [MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \</div> -<div>- [MO_32 | MO_BE] = gen_helper_atomic_##NAME##l_be, \</div> -<div>+ [MO_UL | MO_LE] = gen_helper_atomic_##NAME##l_le, \</div> -<div>+ [MO_UL | MO_BE] = gen_helper_atomic_##NAME##l_be, \</div> -<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \</div> -<div> WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \</div> -<div> }; \</div> -<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div> -<div>index a378887..4b6ee89 100644</div> -<div>--- a/tcg/tcg.h</div> -<div>+++ b/tcg/tcg.h</div> -<div>@@ -1304,7 +1304,7 @@ uint64_t dup_const(unsigned vece, uint64_t c);</div> -<div> (__builtin_constant_p(VECE) \</div> -<div> ? ((VECE) == MO_UB ? 0x0101010101010101ull * (uint8_t)(C) \</div> -<div> : (VECE) == MO_UW ? 0x0001000100010001ull * (uint16_t)(C) \</div> -<div>- : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \</div> -<div>+ : (VECE) == MO_UL ? 0x0000000100000001ull * (uint32_t)(C) \</div> -<div> : dup_const(VECE, C)) \</div> -<div> : dup_const(VECE, C))</div> -<div> </div> -<div>-- </div> -<div>1.8.3.1</div> -<div><br> -<br> -</div> -<p><br> -</p> -</body> -</html> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index e54d0ae..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/html; charset="iso-8859-1" -Content-Transfer-Encoding: quoted-printable diff --git a/a/content_digest b/N1/content_digest index c76ace7..0766281 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,34 +1,34 @@ "ref\0e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net\0" "From\0<tony.nguyen@bt.com>\0" - "Subject\0[Qemu-riscv] [Qemu-devel] [PATCH v2 03/20] tcg: Replace MO_32 with MO_UL alias\0" + "Subject\0[Qemu-devel] [PATCH v2 03/20] tcg: Replace MO_32 with MO_UL alias\0" "Date\0Mon, 22 Jul 2019 15:41:47 +0000\0" "To\0<qemu-devel@nongnu.org>\0" - "Cc\0<peter.maydell@linaro.org>" - <walling@linux.ibm.com> - <david@redhat.com> - <palmer@sifive.com> - <mark.cave-ayland@ilande.co.uk> - <Alistair.Francis@wdc.com> - <arikalo@wavecomp.com> - <mst@redhat.com> - <pasic@linux.ibm.com> - <borntraeger@de.ibm.com> - <rth@twiddle.net> - <atar4qemu@gmail.com> - <ehabkost@redhat.com> - <sw@weilnetz.de> - <alex.williamson@redhat.com> - <qemu-arm@nongnu.org> - <david@gibson.dropbear.id.au> - <qemu-riscv@nongnu.org> - <cohuck@redhat.com> - <claudio.fontana@huawei.com> - <qemu-s390x@nongnu.org> - <qemu-ppc@nongnu.org> - <amarkovic@wavecomp.com> - <pbonzini@redhat.com> - " <aurelien@aurel32.net>\0" - "\01:1\0" + "Cc\0peter.maydell@linaro.org" + walling@linux.ibm.com + mst@redhat.com + palmer@sifive.com + mark.cave-ayland@ilande.co.uk + Alistair.Francis@wdc.com + arikalo@wavecomp.com + david@redhat.com + pasic@linux.ibm.com + borntraeger@de.ibm.com + rth@twiddle.net + atar4qemu@gmail.com + ehabkost@redhat.com + sw@weilnetz.de + qemu-s390x@nongnu.org + qemu-arm@nongnu.org + david@gibson.dropbear.id.au + qemu-riscv@nongnu.org + cohuck@redhat.com + claudio.fontana@huawei.com + alex.williamson@redhat.com + qemu-ppc@nongnu.org + amarkovic@wavecomp.com + pbonzini@redhat.com + " aurelien@aurel32.net\0" + "\00:1\0" "b\0" "Preparation for splitting MO_32 out from TCGMemOp into new accelerator\n" "independent MemOp.\n" @@ -2399,2394 +2399,5 @@ "\n" "--\n" 1.8.3.1 - "\01:2\0" - "b\0" - "<html>\r\n" - "<head>\r\n" - "<meta http-equiv=\"Content-Type\" content=\"text/html; charset=iso-8859-1\">\r\n" - "<style type=\"text/css\" style=\"display:none\"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style>\r\n" - "</head>\r\n" - "<body dir=\"ltr\" style=\"font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;\">\r\n" - "<p></p>\r\n" - "<div><span style=\"font-size: 12pt;\">Preparation for splitting MO_32 out from TCGMemOp into new accelerator</span><br>\r\n" - "</div>\r\n" - "<div>independent MemOp.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>As MO_32 will be a value of MemOp, existing TCGMemOp comparisons and</div>\r\n" - "<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div>\r\n" - "<div>---</div>\r\n" - "<div> target/arm/sve_helper.c | 6 +-</div>\r\n" - "<div> target/arm/translate-a64.c | 148 +++++++++++++++++------------------</div>\r\n" - "<div> target/arm/translate-sve.c | 12 +--</div>\r\n" - "<div> target/arm/translate-vfp.inc.c | 4 +-</div>\r\n" - "<div> target/arm/translate.c | 34 ++++----</div>\r\n" - "<div> target/i386/translate.c | 150 ++++++++++++++++++------------------</div>\r\n" - "<div> target/ppc/translate/vmx-impl.inc.c | 28 +++----</div>\r\n" - "<div> target/ppc/translate/vsx-impl.inc.c | 4 +-</div>\r\n" - "<div> target/s390x/translate.c | 4 +-</div>\r\n" - "<div> target/s390x/translate_vx.inc.c | 2 +-</div>\r\n" - "<div> target/s390x/vec.h | 4 +-</div>\r\n" - "<div> tcg/aarch64/tcg-target.inc.c | 20 ++---</div>\r\n" - "<div> tcg/arm/tcg-target.inc.c | 6 +-</div>\r\n" - "<div> tcg/i386/tcg-target.inc.c | 28 +++----</div>\r\n" - "<div> tcg/mips/tcg-target.inc.c | 6 +-</div>\r\n" - "<div> tcg/ppc/tcg-target.inc.c | 2 +-</div>\r\n" - "<div> tcg/riscv/tcg-target.inc.c | 2 +-</div>\r\n" - "<div> tcg/sparc/tcg-target.inc.c | 2 +-</div>\r\n" - "<div> tcg/tcg-op-gvec.c | 64 +++++++--------</div>\r\n" - "<div> tcg/tcg-op-vec.c | 6 +-</div>\r\n" - "<div> tcg/tcg-op.c | 18 ++---</div>\r\n" - "<div> tcg/tcg.h | 2 +-</div>\r\n" - "<div> 22 files changed, 276 insertions(+), 276 deletions(-)</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div>\r\n" - "<div>index f6bef3d..fa705c4 100644</div>\r\n" - "<div>--- a/target/arm/sve_helper.c</div>\r\n" - "<div>+++ b/target/arm/sve_helper.c</div>\r\n" - "<div>@@ -1561,7 +1561,7 @@ void HELPER(sve_cpy_m_s)(void *vd, void *vn, void *vg,</div>\r\n" - "<div> uint64_t *d = vd, *n = vn;</div>\r\n" - "<div> uint8_t *pg = vg;</div>\r\n" - "<div> </div>\r\n" - "<div>- mm = dup_const(MO_32, mm);</div>\r\n" - "<div>+ mm = dup_const(MO_UL, mm);</div>\r\n" - "<div> for (i = 0; i < opr_sz; i += 1) {</div>\r\n" - "<div> uint64_t nn = n[i];</div>\r\n" - "<div> uint64_t pp = expand_pred_s(pg[H1(i)]);</div>\r\n" - "<div>@@ -1612,7 +1612,7 @@ void HELPER(sve_cpy_z_s)(void *vd, void *vg, uint64_t val, uint32_t desc)</div>\r\n" - "<div> uint64_t *d = vd;</div>\r\n" - "<div> uint8_t *pg = vg;</div>\r\n" - "<div> </div>\r\n" - "<div>- val = dup_const(MO_32, val);</div>\r\n" - "<div>+ val = dup_const(MO_UL, val);</div>\r\n" - "<div> for (i = 0; i < opr_sz; i += 1) {</div>\r\n" - "<div> d[i] = val & expand_pred_s(pg[H1(i)]);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -5123,7 +5123,7 @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,</div>\r\n" - "<div> target_ulong addr;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Skip to the first true predicate. */</div>\r\n" - "<div>- reg_off = find_next_active(vg, 0, reg_max, MO_32);</div>\r\n" - "<div>+ reg_off = find_next_active(vg, 0, reg_max, MO_UL);</div>\r\n" - "<div> if (likely(reg_off < reg_max)) {</div>\r\n" - "<div> /* Perform one normal read, which will fault or not. */</div>\r\n" - "<div> set_helper_retaddr(ra);</div>\r\n" - "<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div>\r\n" - "<div>index 3acfccb..0b92e6d 100644</div>\r\n" - "<div>--- a/target/arm/translate-a64.c</div>\r\n" - "<div>+++ b/target/arm/translate-a64.c</div>\r\n" - "<div>@@ -484,7 +484,7 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 v = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32));</div>\r\n" - "<div>+ tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_UL));</div>\r\n" - "<div> return v;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -999,7 +999,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_SB:</div>\r\n" - "<div>@@ -1008,7 +1008,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_SW:</div>\r\n" - "<div> tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32|MO_SIGN:</div>\r\n" - "<div>+ case MO_SL:</div>\r\n" - "<div> tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -1037,8 +1037,8 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_SW:</div>\r\n" - "<div> tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>- case MO_32|MO_SIGN:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div>+ case MO_SL:</div>\r\n" - "<div> tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -1058,7 +1058,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -1080,7 +1080,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_st_i32(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -5299,7 +5299,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (signal_all_nans) {</div>\r\n" - "<div> gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -5354,7 +5354,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> switch (type) {</div>\r\n" - "<div> case 0:</div>\r\n" - "<div>- size = MO_32;</div>\r\n" - "<div>+ size = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div> size = MO_64;</div>\r\n" - "<div>@@ -5405,7 +5405,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> switch (type) {</div>\r\n" - "<div> case 0:</div>\r\n" - "<div>- size = MO_32;</div>\r\n" - "<div>+ size = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div> size = MO_64;</div>\r\n" - "<div>@@ -5471,7 +5471,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> switch (type) {</div>\r\n" - "<div> case 0:</div>\r\n" - "<div>- sz = MO_32;</div>\r\n" - "<div>+ sz = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div> sz = MO_64;</div>\r\n" - "<div>@@ -6276,7 +6276,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> switch (type) {</div>\r\n" - "<div> case 0:</div>\r\n" - "<div>- sz = MO_32;</div>\r\n" - "<div>+ sz = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div> sz = MO_64;</div>\r\n" - "<div>@@ -6581,7 +6581,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)</div>\r\n" - "<div> switch (type) {</div>\r\n" - "<div> case 0:</div>\r\n" - "<div> /* 32 bit */</div>\r\n" - "<div>- tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32));</div>\r\n" - "<div>+ tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_UL));</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div> /* 64 bit */</div>\r\n" - "<div>@@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,</div>\r\n" - "<div> {</div>\r\n" - "<div> if (esize == size) {</div>\r\n" - "<div> int element;</div>\r\n" - "<div>- TCGMemOp msize = esize == 16 ? MO_UW : MO_32;</div>\r\n" - "<div>+ TCGMemOp msize = esize == 16 ? MO_UW : MO_UL;</div>\r\n" - "<div> TCGv_i32 tcg_elem;</div>\r\n" - "<div> </div>\r\n" - "<div> /* We should have one register left here */</div>\r\n" - "<div>@@ -7702,7 +7702,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- size = extract32(size, 0, 1) ? MO_64 : MO_32;</div>\r\n" - "<div>+ size = extract32(size, 0, 1) ? MO_64 : MO_UL;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> if (!fp_access_check(s)) {</div>\r\n" - "<div>@@ -8181,7 +8181,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div>\r\n" - "<div> }</div>\r\n" - "<div> };</div>\r\n" - "<div> NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];</div>\r\n" - "<div>- TCGMemOp memop = scalar ? size : MO_32;</div>\r\n" - "<div>+ TCGMemOp memop = scalar ? size : MO_UL;</div>\r\n" - "<div> int maxpass = scalar ? 1 : is_q ? 4 : 2;</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < maxpass; pass++) {</div>\r\n" - "<div>@@ -8204,7 +8204,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div>\r\n" - "<div> }</div>\r\n" - "<div> write_fp_sreg(s, rd, tcg_op);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_op, rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_op, rd, pass, MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i32(tcg_op);</div>\r\n" - "<div>@@ -8264,7 +8264,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div>\r\n" - "<div> read_vec_element_i32(s, tcg_int32, rn, pass, mop);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (fracbits) {</div>\r\n" - "<div> if (is_signed) {</div>\r\n" - "<div> gen_helper_vfp_sltos(tcg_float, tcg_int32,</div>\r\n" - "<div>@@ -8337,7 +8337,7 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> } else if (immh & 4) {</div>\r\n" - "<div>- size = MO_32;</div>\r\n" - "<div>+ size = MO_UL;</div>\r\n" - "<div> } else if (immh & 2) {</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div> if (!dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div>@@ -8382,7 +8382,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> } else if (immh & 0x4) {</div>\r\n" - "<div>- size = MO_32;</div>\r\n" - "<div>+ size = MO_UL;</div>\r\n" - "<div> } else if (immh & 0x2) {</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div> if (!dc_isar_feature(aa64_fp16, s)) {</div>\r\n" - "<div>@@ -8436,7 +8436,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> fn = gen_helper_vfp_toshh;</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (is_u) {</div>\r\n" - "<div> fn = gen_helper_vfp_touls;</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -8588,8 +8588,8 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, 0, MO_SL);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, 0, MO_SL);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);</div>\r\n" - "<div> gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);</div>\r\n" - "<div>@@ -8631,7 +8631,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> case 0x9: /* SQDMLAL, SQDMLAL2 */</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 tcg_op3 = tcg_temp_new_i64();</div>\r\n" - "<div>- read_vec_element(s, tcg_op3, rd, 0, MO_32);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op3, rd, 0, MO_UL);</div>\r\n" - "<div> gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,</div>\r\n" - "<div> tcg_res, tcg_op3);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op3);</div>\r\n" - "<div>@@ -8831,8 +8831,8 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div>\r\n" - "<div> TCGv_i32 tcg_op2 = tcg_temp_new_i32();</div>\r\n" - "<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_UL);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (fpopcode) {</div>\r\n" - "<div> case 0x39: /* FMLS */</div>\r\n" - "<div>@@ -8840,7 +8840,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div>\r\n" - "<div> gen_helper_vfp_negs(tcg_op1, tcg_op1);</div>\r\n" - "<div> /* fall through */</div>\r\n" - "<div> case 0x19: /* FMLA */</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div>\r\n" - "<div> gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,</div>\r\n" - "<div> tcg_res, fpst);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -8908,7 +8908,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div>\r\n" - "<div> write_vec_element(s, tcg_tmp, rd, pass, MO_64);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_tmp);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i32(tcg_res);</div>\r\n" - "<div>@@ -9557,7 +9557,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < maxpasses; pass++) {</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op, rn, pass, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0x3c: /* URECPE */</div>\r\n" - "<div>@@ -9579,7 +9579,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div>\r\n" - "<div> if (is_scalar) {</div>\r\n" - "<div> write_fp_sreg(s, rd, tcg_res);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_temp_free_i32(tcg_res);</div>\r\n" - "<div>@@ -9693,7 +9693,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_UL);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> clear_vec_high(s, is_q, rd);</div>\r\n" - "<div>@@ -9740,8 +9740,8 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div>\r\n" - "<div> read_vec_element_i32(s, tcg_rn, rn, pass, size);</div>\r\n" - "<div> read_vec_element_i32(s, tcg_rd, rd, pass, size);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_rn, rn, pass, MO_UL);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_rd, rd, pass, MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> if (is_u) { /* USQADD */</div>\r\n" - "<div>@@ -9779,7 +9779,7 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div>\r\n" - "<div> write_vec_element(s, tcg_zero, rd, 0, MO_64);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_zero);</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_rd, rd, pass, MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_temp_free_i32(tcg_rd);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_rn);</div>\r\n" - "<div>@@ -10347,7 +10347,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_passres;</div>\r\n" - "<div>- TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);</div>\r\n" - "<div>+ TCGMemOp memop = is_u ? MO_UL : MO_SL;</div>\r\n" - "<div> </div>\r\n" - "<div> int elt = pass + is_q * 2;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -10426,8 +10426,8 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> TCGv_i64 tcg_passres;</div>\r\n" - "<div> int elt = pass + is_q * 2;</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, rn, elt, MO_UL);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, rm, elt, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> if (accop == 0) {</div>\r\n" - "<div> tcg_passres = tcg_res[pass];</div>\r\n" - "<div>@@ -10547,7 +10547,7 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> NeonGenWidenFn *widenfn = widenfns[size][is_u];</div>\r\n" - "<div> </div>\r\n" - "<div> read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_UL);</div>\r\n" - "<div> widenfn(tcg_op2_wide, tcg_op2);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op2);</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i64();</div>\r\n" - "<div>@@ -10603,7 +10603,7 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_UL);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> clear_vec_high(s, is_q, rd);</div>\r\n" - "<div>@@ -10860,8 +10860,8 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div>\r\n" - "<div> int passreg = pass < (maxpass / 2) ? rn : rm;</div>\r\n" - "<div> int passelt = (is_q && (pass & 1)) ? 2 : 0;</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_UL);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_UL);</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div>@@ -10925,7 +10925,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < maxpass; pass++) {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_UL);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> clear_vec_high(s, is_q, rd);</div>\r\n" - "<div>@@ -10971,7 +10971,7 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>- handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32,</div>\r\n" - "<div>+ handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_UL,</div>\r\n" - "<div> rn, rm, rd);</div>\r\n" - "<div> return;</div>\r\n" - "<div> case 0x1b: /* FMULX */</div>\r\n" - "<div>@@ -11174,8 +11174,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> NeonGenTwoOpFn *genfn = NULL;</div>\r\n" - "<div> NeonGenTwoOpEnvFn *genenvfn = NULL;</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_UL);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0x0: /* SHADD, UHADD */</div>\r\n" - "<div>@@ -11292,11 +11292,11 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_gen_add_i32,</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, rd, pass, MO_UL);</div>\r\n" - "<div> fns[size](tcg_res, tcg_op1, tcg_res);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i32(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op1);</div>\r\n" - "<div>@@ -11578,7 +11578,7 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x02: /* SDOT (vector) */</div>\r\n" - "<div> case 0x12: /* UDOT (vector) */</div>\r\n" - "<div>- if (size != MO_32) {</div>\r\n" - "<div>+ if (size != MO_UL) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -11709,7 +11709,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div>\r\n" - "<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_UL);</div>\r\n" - "<div> gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -11732,7 +11732,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div>\r\n" - "<div> fpst, ahp);</div>\r\n" - "<div> }</div>\r\n" - "<div> for (pass = 0; pass < 4; pass++) {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_UL);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -11771,7 +11771,7 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -11900,7 +11900,7 @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)</div>\r\n" - "<div> NeonGenWidenFn *widenfn = widenfns[size];</div>\r\n" - "<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op, rn, part + pass, MO_UL);</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i64();</div>\r\n" - "<div> widenfn(tcg_res[pass], tcg_op);</div>\r\n" - "<div> tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);</div>\r\n" - "<div>@@ -12251,7 +12251,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div>\r\n" - "<div> TCGCond cond;</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op, rn, pass, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> if (size == 2) {</div>\r\n" - "<div> /* Special cases for 32 bit elements */</div>\r\n" - "<div>@@ -12418,7 +12418,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i32(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op);</div>\r\n" - "<div>@@ -12816,7 +12816,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x0e: /* SDOT */</div>\r\n" - "<div> case 0x1e: /* UDOT */</div>\r\n" - "<div>- if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) {</div>\r\n" - "<div>+ if (is_scalar || size != MO_UL || !dc_isar_feature(aa64_dp, s)) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -12835,7 +12835,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> case 0x04: /* FMLSL */</div>\r\n" - "<div> case 0x18: /* FMLAL2 */</div>\r\n" - "<div> case 0x1c: /* FMLSL2 */</div>\r\n" - "<div>- if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {</div>\r\n" - "<div>+ if (is_scalar || size != MO_UL || !dc_isar_feature(aa64_fhm, s)) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -12855,7 +12855,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div> is_fp16 = true;</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32: /* single precision */</div>\r\n" - "<div>+ case MO_UL: /* single precision */</div>\r\n" - "<div> case MO_64: /* double precision */</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -12868,7 +12868,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> /* Each indexable element is a complex pair. */</div>\r\n" - "<div> size += 1;</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (h && !is_q) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -12902,7 +12902,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> index = h << 2 | l << 1 | m;</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> index = h << 1 | l;</div>\r\n" - "<div> rm |= m << 4;</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -13038,7 +13038,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i32 tcg_op = tcg_temp_new_i32();</div>\r\n" - "<div> TCGv_i32 tcg_res = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (16 * u + opcode) {</div>\r\n" - "<div> case 0x08: /* MUL */</div>\r\n" - "<div>@@ -13060,7 +13060,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> if (opcode == 0x8) {</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op, rd, pass, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op, rd, pass, MO_UL);</div>\r\n" - "<div> genfn = fns[size - 1][is_sub];</div>\r\n" - "<div> genfn(tcg_res, tcg_op, tcg_res);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -13068,7 +13068,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> case 0x05: /* FMLS */</div>\r\n" - "<div> case 0x01: /* FMLA */</div>\r\n" - "<div> read_vec_element_i32(s, tcg_res, rd, pass,</div>\r\n" - "<div>- is_scalar ? size : MO_32);</div>\r\n" - "<div>+ is_scalar ? size : MO_UL);</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div> case 1:</div>\r\n" - "<div> if (opcode == 0x5) {</div>\r\n" - "<div>@@ -13153,7 +13153,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x1d: /* SQRDMLAH */</div>\r\n" - "<div> read_vec_element_i32(s, tcg_res, rd, pass,</div>\r\n" - "<div>- is_scalar ? size : MO_32);</div>\r\n" - "<div>+ is_scalar ? size : MO_UL);</div>\r\n" - "<div> if (size == 1) {</div>\r\n" - "<div> gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,</div>\r\n" - "<div> tcg_op, tcg_idx, tcg_res);</div>\r\n" - "<div>@@ -13164,7 +13164,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x1f: /* SQRDMLSH */</div>\r\n" - "<div> read_vec_element_i32(s, tcg_res, rd, pass,</div>\r\n" - "<div>- is_scalar ? size : MO_32);</div>\r\n" - "<div>+ is_scalar ? size : MO_UL);</div>\r\n" - "<div> if (size == 1) {</div>\r\n" - "<div> gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,</div>\r\n" - "<div> tcg_op, tcg_idx, tcg_res);</div>\r\n" - "<div>@@ -13180,7 +13180,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> if (is_scalar) {</div>\r\n" - "<div> write_fp_sreg(s, rd, tcg_res);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i32(tcg_op);</div>\r\n" - "<div>@@ -13194,7 +13194,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i64 tcg_res[2];</div>\r\n" - "<div> int pass;</div>\r\n" - "<div> bool satop = extract32(opcode, 0, 1);</div>\r\n" - "<div>- TCGMemOp memop = MO_32;</div>\r\n" - "<div>+ TCGMemOp memop = MO_UL;</div>\r\n" - "<div> </div>\r\n" - "<div> if (satop || !u) {</div>\r\n" - "<div> memop |= MO_SIGN;</div>\r\n" - "<div>@@ -13288,7 +13288,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> read_vec_element_i32(s, tcg_op, rn, pass, size);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> read_vec_element_i32(s, tcg_op, rn,</div>\r\n" - "<div>- pass + (is_q * 2), MO_32);</div>\r\n" - "<div>+ pass + (is_q * 2), MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i64();</div>\r\n" - "<div>@@ -13780,19 +13780,19 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_res = tcg_temp_new_i32();</div>\r\n" - "<div> tcg_zero = tcg_const_i32(0);</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);</div>\r\n" - "<div>- read_vec_element_i32(s, tcg_op3, ra, 3, MO_32);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op1, rn, 3, MO_UL);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op2, rm, 3, MO_UL);</div>\r\n" - "<div>+ read_vec_element_i32(s, tcg_op3, ra, 3, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_rotri_i32(tcg_res, tcg_op1, 20);</div>\r\n" - "<div> tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2);</div>\r\n" - "<div> tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3);</div>\r\n" - "<div> tcg_gen_rotri_i32(tcg_res, tcg_res, 25);</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element_i32(s, tcg_zero, rd, 0, MO_32);</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_zero, rd, 1, MO_32);</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_zero, rd, 2, MO_32);</div>\r\n" - "<div>- write_vec_element_i32(s, tcg_res, rd, 3, MO_32);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_zero, rd, 0, MO_UL);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_zero, rd, 1, MO_UL);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_zero, rd, 2, MO_UL);</div>\r\n" - "<div>+ write_vec_element_i32(s, tcg_res, rd, 3, MO_UL);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i32(tcg_op1);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op2);</div>\r\n" - "<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div>\r\n" - "<div>index 2bc1bd1..f7c891d 100644</div>\r\n" - "<div>--- a/target/arm/translate-sve.c</div>\r\n" - "<div>+++ b/target/arm/translate-sve.c</div>\r\n" - "<div>@@ -1693,7 +1693,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div>\r\n" - "<div> tcg_temp_free_i32(t32);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> t64 = tcg_temp_new_i64();</div>\r\n" - "<div> if (d) {</div>\r\n" - "<div> tcg_gen_neg_i64(t64, val);</div>\r\n" - "<div>@@ -3320,7 +3320,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_sve_subri_s,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32,</div>\r\n" - "<div>+ .vece = MO_UL,</div>\r\n" - "<div> .scalar_first = true },</div>\r\n" - "<div> { .fni8 = tcg_gen_sub_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div>@@ -5258,7 +5258,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> switch (a->esz) {</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> fn = gather_load_fn32[be][a->ff][a->xs][a->u][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -5286,7 +5286,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> switch (a->esz) {</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> fn = gather_load_fn32[be][a->ff][0][a->u][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -5364,7 +5364,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)</div>\r\n" - "<div> return true;</div>\r\n" - "<div> }</div>\r\n" - "<div> switch (a->esz) {</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> fn = scatter_store_fn32[be][a->xs][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -5392,7 +5392,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> switch (a->esz) {</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> fn = scatter_store_fn32[be][0][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>index 549874c..5e0cd63 100644</div>\r\n" - "<div>--- a/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>+++ b/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>@@ -46,7 +46,7 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8)</div>\r\n" - "<div> extract32(imm8, 0, 6);</div>\r\n" - "<div> imm <<= 48;</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |</div>\r\n" - "<div> (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |</div>\r\n" - "<div> (extract32(imm8, 0, 6) << 3);</div>\r\n" - "<div>@@ -1901,7 +1901,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));</div>\r\n" - "<div>+ fd = tcg_const_i32(vfp_expand_imm(MO_UL, a->imm));</div>\r\n" - "<div> </div>\r\n" - "<div> for (;;) {</div>\r\n" - "<div> neon_store_reg32(fd, vd);</div>\r\n" - "<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div>\r\n" - "<div>index 8d10922..5510ecd 100644</div>\r\n" - "<div>--- a/target/arm/translate.c</div>\r\n" - "<div>+++ b/target/arm/translate.c</div>\r\n" - "<div>@@ -1085,7 +1085,7 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)</div>\r\n" - "<div> tcg_gen_extu_i32_tl(addr, a32);</div>\r\n" - "<div> </div>\r\n" - "<div> /* Not needed for user-mode BE32, where we use MO_BE instead. */</div>\r\n" - "<div>- if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {</div>\r\n" - "<div>+ if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_UL) {</div>\r\n" - "<div> tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));</div>\r\n" - "<div> }</div>\r\n" - "<div> return addr;</div>\r\n" - "<div>@@ -1480,7 +1480,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i32(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_st_i32(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -1499,7 +1499,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_st16_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_st32_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -4272,7 +4272,7 @@ const GVecGen2i ssra_op[4] = {</div>\r\n" - "<div> .fniv = gen_ssra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_ssra,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = gen_ssra64_i64,</div>\r\n" - "<div> .fniv = gen_ssra_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>@@ -4330,7 +4330,7 @@ const GVecGen2i usra_op[4] = {</div>\r\n" - "<div> .fniv = gen_usra_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_usra,</div>\r\n" - "<div>- .vece = MO_32, },</div>\r\n" - "<div>+ .vece = MO_UL, },</div>\r\n" - "<div> { .fni8 = gen_usra64_i64,</div>\r\n" - "<div> .fniv = gen_usra_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>@@ -4410,7 +4410,7 @@ const GVecGen2i sri_op[4] = {</div>\r\n" - "<div> .fniv = gen_shr_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sri,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = gen_shr64_ins_i64,</div>\r\n" - "<div> .fniv = gen_shr_ins_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>@@ -4488,7 +4488,7 @@ const GVecGen2i sli_op[4] = {</div>\r\n" - "<div> .fniv = gen_shl_ins_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sli,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = gen_shl64_ins_i64,</div>\r\n" - "<div> .fniv = gen_shl_ins_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>@@ -4584,7 +4584,7 @@ const GVecGen3 mla_op[4] = {</div>\r\n" - "<div> .fniv = gen_mla_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mla,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = gen_mla64_i64,</div>\r\n" - "<div> .fniv = gen_mla_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>@@ -4608,7 +4608,7 @@ const GVecGen3 mls_op[4] = {</div>\r\n" - "<div> .fniv = gen_mls_vec,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mls,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = gen_mls64_i64,</div>\r\n" - "<div> .fniv = gen_mls_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>@@ -4653,7 +4653,7 @@ const GVecGen3 cmtst_op[4] = {</div>\r\n" - "<div> { .fni4 = gen_cmtst_i32,</div>\r\n" - "<div> .fniv = gen_cmtst_vec,</div>\r\n" - "<div> .opt_opc = vecop_list_cmtst,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = gen_cmtst_i64,</div>\r\n" - "<div> .fniv = gen_cmtst_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>@@ -4691,7 +4691,7 @@ const GVecGen4 uqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqadd_s,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div> .opt_opc = vecop_list_uqadd,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fniv = gen_uqadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_uqadd_d,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>@@ -4729,7 +4729,7 @@ const GVecGen4 sqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqadd_s,</div>\r\n" - "<div> .opt_opc = vecop_list_sqadd,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fniv = gen_sqadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sqadd_d,</div>\r\n" - "<div> .opt_opc = vecop_list_sqadd,</div>\r\n" - "<div>@@ -4767,7 +4767,7 @@ const GVecGen4 uqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqsub_s,</div>\r\n" - "<div> .opt_opc = vecop_list_uqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fniv = gen_uqsub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_uqsub_d,</div>\r\n" - "<div> .opt_opc = vecop_list_uqsub,</div>\r\n" - "<div>@@ -4805,7 +4805,7 @@ const GVecGen4 sqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqsub_s,</div>\r\n" - "<div> .opt_opc = vecop_list_sqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fniv = gen_sqsub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sqsub_d,</div>\r\n" - "<div> .opt_opc = vecop_list_sqsub,</div>\r\n" - "<div>@@ -5798,10 +5798,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> /* The immediate value has already been inverted,</div>\r\n" - "<div> * so BIC becomes AND.</div>\r\n" - "<div> */</div>\r\n" - "<div>- tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,</div>\r\n" - "<div>+ tcg_gen_gvec_andi(MO_UL, reg_ofs, reg_ofs, imm,</div>\r\n" - "<div> vec_size, vec_size);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,</div>\r\n" - "<div>+ tcg_gen_gvec_ori(MO_UL, reg_ofs, reg_ofs, imm,</div>\r\n" - "<div> vec_size, vec_size);</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -6879,7 +6879,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div> element = (insn >> 18) & 3;</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- size = MO_32;</div>\r\n" - "<div>+ size = MO_UL;</div>\r\n" - "<div> element = (insn >> 19) & 1;</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_gvec_dup_mem(size, neon_reg_offset(rd, 0),</div>\r\n" - "<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div>\r\n" - "<div>index 0535bae..0e863d4 100644</div>\r\n" - "<div>--- a/target/i386/translate.c</div>\r\n" - "<div>+++ b/target/i386/translate.c</div>\r\n" - "<div>@@ -332,16 +332,16 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> /* Select the size of the stack pointer. */</div>\r\n" - "<div> static inline TCGMemOp mo_stacksize(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div>+ return CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div>\r\n" - "<div> static inline TCGMemOp mo_64_32(TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- return ot == MO_64 ? MO_64 : MO_32;</div>\r\n" - "<div>+ return ot == MO_64 ? MO_64 : MO_UL;</div>\r\n" - "<div> #else</div>\r\n" - "<div>- return MO_32;</div>\r\n" - "<div>+ return MO_UL;</div>\r\n" - "<div> #endif</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -356,7 +356,7 @@ static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div>\r\n" - "<div> Used for decoding operand size of port opcodes. */</div>\r\n" - "<div> static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return b & 1 ? (ot == MO_UW ? MO_UW : MO_32) : MO_UB;</div>\r\n" - "<div>+ return b & 1 ? (ot == MO_UW ? MO_UW : MO_UL) : MO_UB;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div>@@ -372,7 +372,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> /* For x86_64, this sets the higher half of register to zero.</div>\r\n" - "<div> For i386, this is equivalent to a mov. */</div>\r\n" - "<div> tcg_gen_ext32u_tl(cpu_regs[reg], t0);</div>\r\n" - "<div>@@ -463,7 +463,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> /* 32 bit address */</div>\r\n" - "<div> if (ovr_seg < 0 && s->addseg) {</div>\r\n" - "<div> ovr_seg = def_seg;</div>\r\n" - "<div>@@ -538,7 +538,7 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div>\r\n" - "<div> }</div>\r\n" - "<div> return dst;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (sign) {</div>\r\n" - "<div> tcg_gen_ext32s_tl(dst, src);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -586,7 +586,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> gen_helper_inw(v, cpu_env, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_helper_inl(v, cpu_env, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -603,7 +603,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> gen_helper_outw(cpu_env, v, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_helper_outl(cpu_env, v, n);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -625,7 +625,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> gen_helper_check_iow(cpu_env, s->tmp2_i32);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_helper_check_iol(cpu_env, s->tmp2_i32);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -1077,7 +1077,7 @@ static TCGLabel *gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void gen_stos(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div>\r\n" - "<div> gen_string_movl_A0_EDI(s);</div>\r\n" - "<div> gen_op_st_v(s, ot, s->T0, s->A0);</div>\r\n" - "<div> gen_op_movl_T0_Dshift(s, ot);</div>\r\n" - "<div>@@ -1568,7 +1568,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div>\r\n" - "<div> goto do_long;</div>\r\n" - "<div> do_long:</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);</div>\r\n" - "<div> if (is_right) {</div>\r\n" - "<div>@@ -1644,7 +1644,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> if (op2 != 0) {</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> if (is_right) {</div>\r\n" - "<div> tcg_gen_rotri_i32(s->tmp2_i32, s->tmp2_i32, op2);</div>\r\n" - "<div>@@ -1725,7 +1725,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> gen_helper_rcrw(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_helper_rcrl(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>@@ -1744,7 +1744,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> gen_helper_rclw(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_helper_rcll(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>@@ -1791,7 +1791,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> }</div>\r\n" - "<div> /* FALLTHRU */</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> /* Concatenate the two 32-bit values and use a 64-bit shift. */</div>\r\n" - "<div> tcg_gen_subi_tl(s->tmp0, count, 1);</div>\r\n" - "<div> if (is_right) {</div>\r\n" - "<div>@@ -1984,7 +1984,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,</div>\r\n" - "<div> </div>\r\n" - "<div> switch (s->aflag) {</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> havesib = 0;</div>\r\n" - "<div> if (rm == 4) {</div>\r\n" - "<div> int code = x86_ldub_code(env, s);</div>\r\n" - "<div>@@ -2190,7 +2190,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> ret = x86_lduw_code(env, s);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -2204,7 +2204,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> </div>\r\n" - "<div> static inline int insn_const_size(TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div>- if (ot <= MO_32) {</div>\r\n" - "<div>+ if (ot <= MO_UL) {</div>\r\n" - "<div> return 1 << ot;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> return 4;</div>\r\n" - "<div>@@ -2400,12 +2400,12 @@ static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void gen_stack_A0(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_UW, cpu_regs[R_ESP], R_SS, -1);</div>\r\n" - "<div>+ gen_lea_v_seg(s, s->ss32 ? MO_UL : MO_UW, cpu_regs[R_ESP], R_SS, -1);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_pusha(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div>+ TCGMemOp s_ot = s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div> TCGMemOp d_ot = s->dflag;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> int i;</div>\r\n" - "<div>@@ -2421,7 +2421,7 @@ static void gen_pusha(DisasContext *s)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_popa(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div>+ TCGMemOp s_ot = s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div> TCGMemOp d_ot = s->dflag;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> int i;</div>\r\n" - "<div>@@ -2443,7 +2443,7 @@ static void gen_popa(DisasContext *s)</div>\r\n" - "<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_UW;</div>\r\n" - "<div>+ TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Push BP; compute FrameTemp into T1. */</div>\r\n" - "<div>@@ -3145,7 +3145,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State,</div>\r\n" - "<div> xmm_regs[reg].ZMM_L(0)));</div>\r\n" - "<div>- gen_op_st_v(s, MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_st_v(s, MO_UL, s->T0, s->A0);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x6e: /* movd mm, ea */</div>\r\n" - "<div>@@ -3157,7 +3157,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> } else</div>\r\n" - "<div> #endif</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 0);</div>\r\n" - "<div> tcg_gen_addi_ptr(s->ptr0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,fpregs[reg].mmx));</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div>@@ -3174,7 +3174,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> } else</div>\r\n" - "<div> #endif</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 0);</div>\r\n" - "<div> tcg_gen_addi_ptr(s->ptr0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,xmm_regs[reg]));</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div>@@ -3211,7 +3211,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> case 0x210: /* movss xmm, ea */</div>\r\n" - "<div> if (mod != 3) {</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div>- gen_op_ld_v(s, MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UL, s->T0, s->A0);</div>\r\n" - "<div> tcg_gen_st32_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State, xmm_regs[reg].ZMM_L(0)));</div>\r\n" - "<div> tcg_gen_movi_tl(s->T0, 0);</div>\r\n" - "<div>@@ -3346,7 +3346,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 1);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x17e: /* movd ea, xmm */</div>\r\n" - "<div>@@ -3360,7 +3360,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UL, OR_TMP0, 1);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x27e: /* movq xmm, ea */</div>\r\n" - "<div>@@ -3405,7 +3405,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State, xmm_regs[reg].ZMM_L(0)));</div>\r\n" - "<div>- gen_op_st_v(s, MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_st_v(s, MO_UL, s->T0, s->A0);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> rm = (modrm & 7) | REX_B(s);</div>\r\n" - "<div> gen_op_movl(s, offsetof(CPUX86State, xmm_regs[rm].ZMM_L(0)),</div>\r\n" - "<div>@@ -3530,7 +3530,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div>\r\n" - "<div> op1_offset = offsetof(CPUX86State,xmm_regs[reg]);</div>\r\n" - "<div> tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);</div>\r\n" - "<div>- if (ot == MO_32) {</div>\r\n" - "<div>+ if (ot == MO_UL) {</div>\r\n" - "<div> SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> sse_fn_epi(cpu_env, s->ptr0, s->tmp2_i32);</div>\r\n" - "<div>@@ -3584,7 +3584,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> if ((b >> 8) & 1) {</div>\r\n" - "<div> gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_Q(0)));</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- gen_op_ld_v(s, MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UL, s->T0, s->A0);</div>\r\n" - "<div> tcg_gen_st32_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State, xmm_t0.ZMM_L(0)));</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -3594,7 +3594,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> op2_offset = offsetof(CPUX86State,xmm_regs[rm]);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_addi_ptr(s->ptr0, cpu_env, op2_offset);</div>\r\n" - "<div>- if (ot == MO_32) {</div>\r\n" - "<div>+ if (ot == MO_UL) {</div>\r\n" - "<div> SSEFunc_i_ep sse_fn_i_ep =</div>\r\n" - "<div> sse_op_table3bi[((b >> 7) & 2) | (b & 1)];</div>\r\n" - "<div> sse_fn_i_ep(s->tmp2_i32, cpu_env, s->ptr0);</div>\r\n" - "<div>@@ -3786,7 +3786,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> if ((b & 0xff) == 0xf0) {</div>\r\n" - "<div> ot = MO_UB;</div>\r\n" - "<div> } else if (s->dflag != MO_64) {</div>\r\n" - "<div>- ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div>\r\n" - "<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -3815,7 +3815,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> if (s->dflag != MO_64) {</div>\r\n" - "<div>- ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_32);</div>\r\n" - "<div>+ ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -4026,7 +4026,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> </div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> /* If we know TL is 64-bit, and we want a 32-bit</div>\r\n" - "<div> result, just do everything in 64-bit arithmetic. */</div>\r\n" - "<div> tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]);</div>\r\n" - "<div>@@ -4172,7 +4172,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x16:</div>\r\n" - "<div>- if (ot == MO_32) { /* pextrd */</div>\r\n" - "<div>+ if (ot == MO_UL) { /* pextrd */</div>\r\n" - "<div> tcg_gen_ld_i32(s->tmp2_i32, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,</div>\r\n" - "<div> xmm_regs[reg].ZMM_L(val & 3)));</div>\r\n" - "<div>@@ -4210,7 +4210,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x20: /* pinsrb */</div>\r\n" - "<div> if (mod == 3) {</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T0, rm);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, rm);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_qemu_ld_tl(s->T0, s->A0,</div>\r\n" - "<div> s->mem_index, MO_UB);</div>\r\n" - "<div>@@ -4248,7 +4248,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> xmm_regs[reg].ZMM_L(3)));</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x22:</div>\r\n" - "<div>- if (ot == MO_32) { /* pinsrd */</div>\r\n" - "<div>+ if (ot == MO_UL) { /* pinsrd */</div>\r\n" - "<div> if (mod == 3) {</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[rm]);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -4393,7 +4393,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> switch (sz) {</div>\r\n" - "<div> case 2:</div>\r\n" - "<div> /* 32 bit access */</div>\r\n" - "<div>- gen_op_ld_v(s, MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_UL, s->T0, s->A0);</div>\r\n" - "<div> tcg_gen_st32_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,xmm_t0.ZMM_L(0)));</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -4630,19 +4630,19 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* In 64-bit mode, the default data size is 32-bit. Select 64-bit</div>\r\n" - "<div> data with rex_w, and 16-bit data with 0x66; rex_w takes precedence</div>\r\n" - "<div> over 0x66 if both are present. */</div>\r\n" - "<div>- dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_32);</div>\r\n" - "<div>+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_UL);</div>\r\n" - "<div> /* In 64-bit mode, 0x67 selects 32-bit addressing. */</div>\r\n" - "<div>- aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);</div>\r\n" - "<div>+ aflag = (prefixes & PREFIX_ADR ? MO_UL : MO_64);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> /* In 16/32-bit mode, 0x66 selects the opposite data size. */</div>\r\n" - "<div> if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {</div>\r\n" - "<div>- dflag = MO_32;</div>\r\n" - "<div>+ dflag = MO_UL;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> dflag = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> /* In 16/32-bit mode, 0x67 selects the opposite addressing. */</div>\r\n" - "<div> if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {</div>\r\n" - "<div>- aflag = MO_32;</div>\r\n" - "<div>+ aflag = MO_UL;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> aflag = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -4891,7 +4891,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULW);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);</div>\r\n" - "<div> tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32,</div>\r\n" - "<div>@@ -4942,7 +4942,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULW);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);</div>\r\n" - "<div> tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,</div>\r\n" - "<div>@@ -4976,7 +4976,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_helper_divw_AX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_helper_divl_EAX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>@@ -4995,7 +4995,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_helper_idivw_AX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_helper_idivl_EAX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>@@ -5026,7 +5026,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* operand size for jumps is 64 bit */</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> } else if (op == 3 || op == 5) {</div>\r\n" - "<div>- ot = dflag != MO_UW ? MO_32 + (rex_w == 1) : MO_UW;</div>\r\n" - "<div>+ ot = dflag != MO_UW ? MO_UL + (rex_w == 1) : MO_UW;</div>\r\n" - "<div> } else if (op == 6) {</div>\r\n" - "<div> /* default push size is 64 bit */</div>\r\n" - "<div> ot = mo_pushpop(s, dflag);</div>\r\n" - "<div>@@ -5146,15 +5146,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> switch (dflag) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div>\r\n" - "<div> gen_op_mov_reg_v(s, MO_64, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext16s_tl(s->T0, s->T0);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UL, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> gen_op_mov_v_reg(s, MO_UB, s->T0, R_EAX);</div>\r\n" - "<div>@@ -5174,11 +5174,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_op_mov_reg_v(s, MO_64, R_EDX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_sari_tl(s->T0, s->T0, 31);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_32, R_EDX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UL, R_EDX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> gen_op_mov_v_reg(s, MO_UW, s->T0, R_EAX);</div>\r\n" - "<div>@@ -5219,7 +5219,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);</div>\r\n" - "<div> tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,</div>\r\n" - "<div>@@ -5394,7 +5394,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /**************************/</div>\r\n" - "<div> /* push/pop */</div>\r\n" - "<div> case 0x50 ... 0x57: /* push */</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T0, (b & 7) | REX_B(s));</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, (b & 7) | REX_B(s));</div>\r\n" - "<div> gen_push_v(s, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x58 ... 0x5f: /* pop */</div>\r\n" - "<div>@@ -5734,7 +5734,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x1b5: /* lgs Gv */</div>\r\n" - "<div> op = R_GS;</div>\r\n" - "<div> do_lxx:</div>\r\n" - "<div>- ot = dflag != MO_UW ? MO_32 : MO_UW;</div>\r\n" - "<div>+ ot = dflag != MO_UW ? MO_UL : MO_UW;</div>\r\n" - "<div> modrm = x86_ldub_code(env, s);</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div> mod = (modrm >> 6) & 3;</div>\r\n" - "<div>@@ -6576,7 +6576,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0xe8: /* call im */</div>\r\n" - "<div> {</div>\r\n" - "<div> if (dflag != MO_UW) {</div>\r\n" - "<div>- tval = (int32_t)insn_get(env, s, MO_32);</div>\r\n" - "<div>+ tval = (int32_t)insn_get(env, s, MO_UL);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tval = (int16_t)insn_get(env, s, MO_UW);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6609,7 +6609,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> goto do_lcall;</div>\r\n" - "<div> case 0xe9: /* jmp im */</div>\r\n" - "<div> if (dflag != MO_UW) {</div>\r\n" - "<div>- tval = (int32_t)insn_get(env, s, MO_32);</div>\r\n" - "<div>+ tval = (int32_t)insn_get(env, s, MO_UL);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tval = (int16_t)insn_get(env, s, MO_UW);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6649,7 +6649,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> goto do_jcc;</div>\r\n" - "<div> case 0x180 ... 0x18f: /* jcc Jv */</div>\r\n" - "<div> if (dflag != MO_UW) {</div>\r\n" - "<div>- tval = (int32_t)insn_get(env, s, MO_32);</div>\r\n" - "<div>+ tval = (int32_t)insn_get(env, s, MO_UL);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tval = (int16_t)insn_get(env, s, MO_UW);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6827,7 +6827,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div> mod = (modrm >> 6) & 3;</div>\r\n" - "<div> rm = (modrm & 7) | REX_B(s);</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T1, reg);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T1, reg);</div>\r\n" - "<div> if (mod != 3) {</div>\r\n" - "<div> AddressParts a = gen_lea_modrm_0(env, s, modrm);</div>\r\n" - "<div> /* specific case: we need to add a displacement */</div>\r\n" - "<div>@@ -7126,10 +7126,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> } else</div>\r\n" - "<div> #endif</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T0, reg);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, reg);</div>\r\n" - "<div> tcg_gen_ext32u_tl(s->T0, s->T0);</div>\r\n" - "<div> tcg_gen_bswap32_tl(s->T0, s->T0);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_32, reg, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UL, reg, s->T0);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0xd6: /* salc */</div>\r\n" - "<div>@@ -7359,7 +7359,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div>- gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_st_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div> case 0xc8: /* monitor */</div>\r\n" - "<div>@@ -7414,7 +7414,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div>- gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_st_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div> case 0xd0: /* xgetbv */</div>\r\n" - "<div>@@ -7560,7 +7560,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div> gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 2);</div>\r\n" - "<div>- gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div>\r\n" - "<div> if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -7577,7 +7577,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div> gen_op_ld_v(s, MO_UW, s->T1, s->A0);</div>\r\n" - "<div> gen_add_A0_im(s, 2);</div>\r\n" - "<div>- gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, CODE64(s) + MO_UL, s->T0, s->A0);</div>\r\n" - "<div> if (dflag == MO_UW) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -7698,7 +7698,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> rm = (modrm & 7) | REX_B(s);</div>\r\n" - "<div> </div>\r\n" - "<div> if (mod == 3) {</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_32, s->T0, rm);</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UL, s->T0, rm);</div>\r\n" - "<div> /* sign extend */</div>\r\n" - "<div> if (d_ot == MO_64) {</div>\r\n" - "<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div>\r\n" - "<div>@@ -7706,7 +7706,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_op_mov_reg_v(s, d_ot, reg, s->T0);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div>- gen_op_ld_v(s, MO_32 | MO_SIGN, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_ld_v(s, MO_SL, s->T0, s->A0);</div>\r\n" - "<div> gen_op_mov_reg_v(s, d_ot, reg, s->T0);</div>\r\n" - "<div> }</div>\r\n" - "<div> } else</div>\r\n" - "<div>@@ -7765,7 +7765,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> TCGv t0;</div>\r\n" - "<div> if (!s->pe || s->vm86)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div>- ot = dflag != MO_UW ? MO_32 : MO_UW;</div>\r\n" - "<div>+ ot = dflag != MO_UW ? MO_UL : MO_UW;</div>\r\n" - "<div> modrm = x86_ldub_code(env, s);</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, MO_UW, OR_TMP0, 0);</div>\r\n" - "<div>@@ -8016,7 +8016,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (CODE64(s))</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> else</div>\r\n" - "<div>- ot = MO_32;</div>\r\n" - "<div>+ ot = MO_UL;</div>\r\n" - "<div> if ((prefixes & PREFIX_LOCK) && (reg == 0) &&</div>\r\n" - "<div> (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {</div>\r\n" - "<div> reg = 8;</div>\r\n" - "<div>@@ -8073,7 +8073,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (CODE64(s))</div>\r\n" - "<div> ot = MO_64;</div>\r\n" - "<div> else</div>\r\n" - "<div>- ot = MO_32;</div>\r\n" - "<div>+ ot = MO_UL;</div>\r\n" - "<div> if (reg >= 8) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -8168,7 +8168,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div> tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr));</div>\r\n" - "<div>- gen_op_st_v(s, MO_32, s->T0, s->A0);</div>\r\n" - "<div>+ gen_op_st_v(s, MO_UL, s->T0, s->A0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div> CASE_MODRM_MEM_OP(4): /* xsave */</div>\r\n" - "<div>@@ -8268,7 +8268,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> dst = treg, src = base;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- if (s->dflag == MO_32) {</div>\r\n" - "<div>+ if (s->dflag == MO_UL) {</div>\r\n" - "<div> tcg_gen_ext32u_tl(dst, src);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_mov_tl(dst, src);</div>\r\n" - "<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>index 71efef4..8aa767e 100644</div>\r\n" - "<div>--- a/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>@@ -409,27 +409,27 @@ GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \\</div>\r\n" - "<div> GEN_VXFORM_V(vadduhm, MO_UW, tcg_gen_gvec_add, 0, 1);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div>-GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);</div>\r\n" - "<div>+GEN_VXFORM_V(vadduwm, MO_UL, tcg_gen_gvec_add, 0, 2);</div>\r\n" - "<div> GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div>\r\n" - "<div> GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div>\r\n" - "<div> GEN_VXFORM_V(vsubuhm, MO_UW, tcg_gen_gvec_sub, 0, 17);</div>\r\n" - "<div>-GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);</div>\r\n" - "<div>+GEN_VXFORM_V(vsubuwm, MO_UL, tcg_gen_gvec_sub, 0, 18);</div>\r\n" - "<div> GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxuh, MO_UW, tcg_gen_gvec_umax, 1, 1);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxuw, MO_UL, tcg_gen_gvec_umax, 1, 2);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsh, MO_UW, tcg_gen_gvec_smax, 1, 5);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxsw, MO_UL, tcg_gen_gvec_smax, 1, 6);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div>\r\n" - "<div> GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div>\r\n" - "<div> GEN_VXFORM_V(vminuh, MO_UW, tcg_gen_gvec_umin, 1, 9);</div>\r\n" - "<div>-GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);</div>\r\n" - "<div>+GEN_VXFORM_V(vminuw, MO_UL, tcg_gen_gvec_umin, 1, 10);</div>\r\n" - "<div> GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div>\r\n" - "<div> GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div>\r\n" - "<div> GEN_VXFORM_V(vminsh, MO_UW, tcg_gen_gvec_smin, 1, 13);</div>\r\n" - "<div>-GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);</div>\r\n" - "<div>+GEN_VXFORM_V(vminsw, MO_UL, tcg_gen_gvec_smin, 1, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div>\r\n" - "<div> GEN_VXFORM(vavgub, 1, 16);</div>\r\n" - "<div> GEN_VXFORM(vabsdub, 1, 16);</div>\r\n" - "<div>@@ -532,18 +532,18 @@ GEN_VXFORM(vmulesh, 4, 13);</div>\r\n" - "<div> GEN_VXFORM(vmulesw, 4, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vslb, MO_UB, tcg_gen_gvec_shlv, 2, 4);</div>\r\n" - "<div> GEN_VXFORM_V(vslh, MO_UW, tcg_gen_gvec_shlv, 2, 5);</div>\r\n" - "<div>-GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);</div>\r\n" - "<div>+GEN_VXFORM_V(vslw, MO_UL, tcg_gen_gvec_shlv, 2, 6);</div>\r\n" - "<div> GEN_VXFORM(vrlwnm, 2, 6);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div>\r\n" - "<div> GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div>\r\n" - "<div> GEN_VXFORM_V(vsrh, MO_UW, tcg_gen_gvec_shrv, 2, 9);</div>\r\n" - "<div>-GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);</div>\r\n" - "<div>+GEN_VXFORM_V(vsrw, MO_UL, tcg_gen_gvec_shrv, 2, 10);</div>\r\n" - "<div> GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div>\r\n" - "<div> GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div>\r\n" - "<div> GEN_VXFORM_V(vsrah, MO_UW, tcg_gen_gvec_sarv, 2, 13);</div>\r\n" - "<div>-GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);</div>\r\n" - "<div>+GEN_VXFORM_V(vsraw, MO_UL, tcg_gen_gvec_sarv, 2, 14);</div>\r\n" - "<div> GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div>\r\n" - "<div> GEN_VXFORM(vsrv, 2, 28);</div>\r\n" - "<div> GEN_VXFORM(vslv, 2, 29);</div>\r\n" - "<div>@@ -595,16 +595,16 @@ GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \\</div>\r\n" - "<div> GEN_VXFORM_SAT(vadduhs, MO_UW, add, usadd, 0, 9);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vmul10euq, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div>-GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vadduws, MO_UL, add, usadd, 0, 10);</div>\r\n" - "<div> GEN_VXFORM_SAT(vaddsbs, MO_UB, add, ssadd, 0, 12);</div>\r\n" - "<div> GEN_VXFORM_SAT(vaddshs, MO_UW, add, ssadd, 0, 13);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vaddsws, MO_UL, add, ssadd, 0, 14);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsububs, MO_UB, sub, ussub, 0, 24);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubuhs, MO_UW, sub, ussub, 0, 25);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vsubuws, MO_UL, sub, ussub, 0, 26);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubsbs, MO_UB, sub, sssub, 0, 28);</div>\r\n" - "<div> GEN_VXFORM_SAT(vsubshs, MO_UW, sub, sssub, 0, 29);</div>\r\n" - "<div>-GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);</div>\r\n" - "<div>+GEN_VXFORM_SAT(vsubsws, MO_UL, sub, sssub, 0, 30);</div>\r\n" - "<div> GEN_VXFORM(vadduqm, 0, 4);</div>\r\n" - "<div> GEN_VXFORM(vaddcuq, 0, 5);</div>\r\n" - "<div> GEN_VXFORM3(vaddeuqm, 30, 0);</div>\r\n" - "<div>@@ -914,7 +914,7 @@ static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div> </div>\r\n" - "<div> GEN_VXFORM_VSPLT(vspltb, MO_UB, 6, 8);</div>\r\n" - "<div> GEN_VXFORM_VSPLT(vsplth, MO_UW, 6, 9);</div>\r\n" - "<div>-GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);</div>\r\n" - "<div>+GEN_VXFORM_VSPLT(vspltw, MO_UL, 6, 10);</div>\r\n" - "<div> GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);</div>\r\n" - "<div> GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);</div>\r\n" - "<div> GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);</div>\r\n" - "<div>diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c</div>\r\n" - "<div>index 3922686..212817e 100644</div>\r\n" - "<div>--- a/target/ppc/translate/vsx-impl.inc.c</div>\r\n" - "<div>+++ b/target/ppc/translate/vsx-impl.inc.c</div>\r\n" - "<div>@@ -1553,12 +1553,12 @@ static void gen_xxspltw(DisasContext *ctx)</div>\r\n" - "<div> </div>\r\n" - "<div> tofs = vsr_full_offset(rt);</div>\r\n" - "<div> bofs = vsr_full_offset(rb);</div>\r\n" - "<div>- bofs += uim << MO_32;</div>\r\n" - "<div>+ bofs += uim << MO_UL;</div>\r\n" - "<div> #ifndef HOST_WORDS_BIG_ENDIAN</div>\r\n" - "<div> bofs ^= 8 | 4;</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);</div>\r\n" - "<div>+ tcg_gen_gvec_dup_mem(MO_UL, tofs, bofs, 16, 16);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))</div>\r\n" - "<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div>\r\n" - "<div>index 415747f..9e646f1 100644</div>\r\n" - "<div>--- a/target/s390x/translate.c</div>\r\n" - "<div>+++ b/target/s390x/translate.c</div>\r\n" - "<div>@@ -196,7 +196,7 @@ static inline int freg64_offset(uint8_t reg)</div>\r\n" - "<div> static inline int freg32_offset(uint8_t reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> g_assert(reg < 16);</div>\r\n" - "<div>- return vec_reg_offset(reg, 0, MO_32);</div>\r\n" - "<div>+ return vec_reg_offset(reg, 0, MO_UL);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static TCGv_i64 load_reg(int reg)</div>\r\n" - "<div>@@ -2283,7 +2283,7 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o)</div>\r\n" - "<div> </div>\r\n" - "<div> /* Write back the output now, so that it happens before the</div>\r\n" - "<div> following branch, so that we don't need local temps. */</div>\r\n" - "<div>- if ((mop & MO_SIZE) == MO_32) {</div>\r\n" - "<div>+ if ((mop & MO_SIZE) == MO_UL) {</div>\r\n" - "<div> tcg_gen_deposit_i64(o->out, o->out, old, 0, 32);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_mov_i64(o->out, old);</div>\r\n" - "<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>index 65da6b3..75d788c 100644</div>\r\n" - "<div>--- a/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>+++ b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>@@ -48,7 +48,7 @@</div>\r\n" - "<div> </div>\r\n" - "<div> #define ES_8 MO_UB</div>\r\n" - "<div> #define ES_16 MO_UW</div>\r\n" - "<div>-#define ES_32 MO_32</div>\r\n" - "<div>+#define ES_32 MO_UL</div>\r\n" - "<div> #define ES_64 MO_64</div>\r\n" - "<div> #define ES_128 4</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div>\r\n" - "<div>index 28e1b1d..f67392c 100644</div>\r\n" - "<div>--- a/target/s390x/vec.h</div>\r\n" - "<div>+++ b/target/s390x/vec.h</div>\r\n" - "<div>@@ -80,7 +80,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div>\r\n" - "<div> return s390_vec_read_element8(v, enr);</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> return s390_vec_read_element16(v, enr);</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> return s390_vec_read_element32(v, enr);</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div> return s390_vec_read_element64(v, enr);</div>\r\n" - "<div>@@ -127,7 +127,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> s390_vec_write_element16(v, enr, data);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> s390_vec_write_element32(v, enr, data);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>index 3d90c4b..dc4fd21 100644</div>\r\n" - "<div>--- a/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>@@ -431,12 +431,12 @@ typedef enum {</div>\r\n" - "<div> that emits them can transform to 3.3.10 or 3.3.13. */</div>\r\n" - "<div> I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_UW << 30,</div>\r\n" - "<div>- I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,</div>\r\n" - "<div>+ I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_UL << 30,</div>\r\n" - "<div> I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_UW << 30,</div>\r\n" - "<div>- I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,</div>\r\n" - "<div>+ I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_UL << 30,</div>\r\n" - "<div> I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div>\r\n" - "<div>@@ -444,10 +444,10 @@ typedef enum {</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_UW << 30,</div>\r\n" - "<div>- I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,</div>\r\n" - "<div>+ I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_UL << 30,</div>\r\n" - "<div> </div>\r\n" - "<div>- I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,</div>\r\n" - "<div>- I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,</div>\r\n" - "<div>+ I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_UL << 30,</div>\r\n" - "<div>+ I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_UL << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,</div>\r\n" - "<div> I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,</div>\r\n" - "<div>@@ -870,7 +870,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div>\r\n" - "<div> </div>\r\n" - "<div> /*</div>\r\n" - "<div> * Test all bytes 0x00 or 0xff second. This can match cases that</div>\r\n" - "<div>- * might otherwise take 2 or 3 insns for MO_UW or MO_32 below.</div>\r\n" - "<div>+ * might otherwise take 2 or 3 insns for MO_UW or MO_UL below.</div>\r\n" - "<div> */</div>\r\n" - "<div> for (i = imm8 = 0; i < 8; i++) {</div>\r\n" - "<div> uint8_t byte = v64 >> (i * 8);</div>\r\n" - "<div>@@ -908,7 +908,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,</div>\r\n" - "<div> tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);</div>\r\n" - "<div> tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);</div>\r\n" - "<div> return;</div>\r\n" - "<div>- } else if (v64 == dup_const(MO_32, v64)) {</div>\r\n" - "<div>+ } else if (v64 == dup_const(MO_UL, v64)) {</div>\r\n" - "<div> uint32_t v32 = v64;</div>\r\n" - "<div> uint32_t n32 = ~v32;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1749,7 +1749,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> tcg_out_rev32(s, data_r, data_r);</div>\r\n" - "<div>- tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);</div>\r\n" - "<div>+ tcg_out_sxt(s, TCG_TYPE_I64, MO_UL, data_r, data_r);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -1782,7 +1782,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (bswap && data_r != TCG_REG_XZR) {</div>\r\n" - "<div> tcg_out_rev32(s, TCG_REG_TMP, data_r);</div>\r\n" - "<div> data_r = TCG_REG_TMP;</div>\r\n" - "<div>@@ -2194,7 +2194,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext_i32_i64:</div>\r\n" - "<div> case INDEX_op_ext32s_i64:</div>\r\n" - "<div>- tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1);</div>\r\n" - "<div>+ tcg_out_sxt(s, TCG_TYPE_I64, MO_UL, a0, a1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case INDEX_op_ext8u_i64:</div>\r\n" - "<div> case INDEX_op_ext8u_i32:</div>\r\n" - "<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>index 0bd400e..05560a2 100644</div>\r\n" - "<div>--- a/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>@@ -1435,7 +1435,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> argreg = tcg_out_arg_reg16(s, argreg, datalo);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> default:</div>\r\n" - "<div> argreg = tcg_out_arg_reg32(s, argreg, datalo);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -1632,7 +1632,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div>\r\n" - "<div> tcg_out_st16_r(s, cond, datalo, addrlo, addend);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> default:</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);</div>\r\n" - "<div>@@ -1677,7 +1677,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div> tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> default:</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);</div>\r\n" - "<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>index 31c3664..93e4c63 100644</div>\r\n" - "<div>--- a/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>@@ -897,7 +897,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a);</div>\r\n" - "<div> a = r;</div>\r\n" - "<div> /* FALLTHRU */</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a);</div>\r\n" - "<div> /* imm8 operand: all output lanes selected from input lane 0. */</div>\r\n" - "<div> tcg_out8(s, 0);</div>\r\n" - "<div>@@ -924,7 +924,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div> tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div>@@ -2173,7 +2173,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo,</div>\r\n" - "<div> base, index, 0, ofs);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);</div>\r\n" - "<div> tcg_out_bswap32(s, scratch);</div>\r\n" - "<div>@@ -2927,7 +2927,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> case INDEX_op_x86_blend_vec:</div>\r\n" - "<div> if (vece == MO_UW) {</div>\r\n" - "<div> insn = OPC_PBLENDW;</div>\r\n" - "<div>- } else if (vece == MO_32) {</div>\r\n" - "<div>+ } else if (vece == MO_UL) {</div>\r\n" - "<div> insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div>@@ -3292,13 +3292,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> case INDEX_op_shrs_vec:</div>\r\n" - "<div> return vece >= MO_UW;</div>\r\n" - "<div> case INDEX_op_sars_vec:</div>\r\n" - "<div>- return vece >= MO_UW && vece <= MO_32;</div>\r\n" - "<div>+ return vece >= MO_UW && vece <= MO_UL;</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_shlv_vec:</div>\r\n" - "<div> case INDEX_op_shrv_vec:</div>\r\n" - "<div>- return have_avx2 && vece >= MO_32;</div>\r\n" - "<div>+ return have_avx2 && vece >= MO_UL;</div>\r\n" - "<div> case INDEX_op_sarv_vec:</div>\r\n" - "<div>- return have_avx2 && vece == MO_32;</div>\r\n" - "<div>+ return have_avx2 && vece == MO_UL;</div>\r\n" - "<div> </div>\r\n" - "<div> case INDEX_op_mul_vec:</div>\r\n" - "<div> if (vece == MO_UB) {</div>\r\n" - "<div>@@ -3320,7 +3320,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> case INDEX_op_umin_vec:</div>\r\n" - "<div> case INDEX_op_umax_vec:</div>\r\n" - "<div> case INDEX_op_abs_vec:</div>\r\n" - "<div>- return vece <= MO_32;</div>\r\n" - "<div>+ return vece <= MO_UL;</div>\r\n" - "<div> </div>\r\n" - "<div> default:</div>\r\n" - "<div> return 0;</div>\r\n" - "<div>@@ -3396,9 +3396,9 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div>\r\n" - "<div> * shift (note that the ISA says shift of 32 is valid).</div>\r\n" - "<div> */</div>\r\n" - "<div> t1 = tcg_temp_new_vec(type);</div>\r\n" - "<div>- tcg_gen_sari_vec(MO_32, t1, v1, imm);</div>\r\n" - "<div>+ tcg_gen_sari_vec(MO_UL, t1, v1, imm);</div>\r\n" - "<div> tcg_gen_shri_vec(MO_64, v0, v1, imm);</div>\r\n" - "<div>- vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,</div>\r\n" - "<div>+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_UL,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(v0),</div>\r\n" - "<div> tcgv_vec_arg(t1), 0xaa);</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div>@@ -3515,28 +3515,28 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,</div>\r\n" - "<div> fixup = NEED_SWAP | NEED_INV;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case TCG_COND_LEU:</div>\r\n" - "<div>- if (vece <= MO_32) {</div>\r\n" - "<div>+ if (vece <= MO_UL) {</div>\r\n" - "<div> fixup = NEED_UMIN;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> fixup = NEED_BIAS | NEED_INV;</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case TCG_COND_GTU:</div>\r\n" - "<div>- if (vece <= MO_32) {</div>\r\n" - "<div>+ if (vece <= MO_UL) {</div>\r\n" - "<div> fixup = NEED_UMIN | NEED_INV;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> fixup = NEED_BIAS;</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case TCG_COND_GEU:</div>\r\n" - "<div>- if (vece <= MO_32) {</div>\r\n" - "<div>+ if (vece <= MO_UL) {</div>\r\n" - "<div> fixup = NEED_UMAX;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> fixup = NEED_BIAS | NEED_SWAP | NEED_INV;</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> case TCG_COND_LTU:</div>\r\n" - "<div>- if (vece <= MO_32) {</div>\r\n" - "<div>+ if (vece <= MO_UL) {</div>\r\n" - "<div> fixup = NEED_UMAX | NEED_INV;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> fixup = NEED_BIAS | NEED_SWAP;</div>\r\n" - "<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>index 1780cb1..a78fe87 100644</div>\r\n" - "<div>--- a/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>@@ -1386,7 +1386,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -1579,11 +1579,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SH, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_32 | MO_BSWAP:</div>\r\n" - "<div>+ case MO_UL | MO_BSWAP:</div>\r\n" - "<div> tcg_out_bswap32(s, TCG_TMP3, lo);</div>\r\n" - "<div> lo = TCG_TMP3;</div>\r\n" - "<div> /* FALLTHRU */</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SW, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>index 852b894..835336a 100644</div>\r\n" - "<div>--- a/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>@@ -1714,7 +1714,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> #endif</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);</div>\r\n" - "<div> /* FALLTHRU */</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>index 20bc19d..1905986 100644</div>\r\n" - "<div>--- a/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>@@ -1222,7 +1222,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_out_opc_store(s, OPC_SH, base, lo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_out_opc_store(s, OPC_SW, base, lo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>index 85550b5..ac0d3a3 100644</div>\r\n" - "<div>--- a/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>@@ -889,7 +889,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div>\r\n" - "<div> tcg_out_arithi(s, r, r, 16, SHIFT_SLL);</div>\r\n" - "<div> tcg_out_arithi(s, r, r, 16, SHIFT_SRL);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (SPARC64) {</div>\r\n" - "<div> tcg_out_arith(s, r, r, 0, SHIFT_SRL);</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>index da409f5..e63622c 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-gvec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>@@ -310,7 +310,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div>\r\n" - "<div> return 0x0101010101010101ull * (uint8_t)c;</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> return 0x0001000100010001ull * (uint16_t)c;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> return 0x0000000100000001ull * (uint32_t)c;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div> return c;</div>\r\n" - "<div>@@ -330,7 +330,7 @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> tcg_gen_deposit_i32(out, in, in, 16, 16);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_mov_i32(out, in);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -349,7 +349,7 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div>\r\n" - "<div> tcg_gen_ext16u_i64(out, in);</div>\r\n" - "<div> tcg_gen_muli_i64(out, out, 0x0001000100010001ull);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_deposit_i64(out, in, in, 32, 32);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_64:</div>\r\n" - "<div>@@ -443,7 +443,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> TCGv_ptr t_ptr;</div>\r\n" - "<div> uint32_t i;</div>\r\n" - "<div> </div>\r\n" - "<div>- assert(vece <= (in_32 ? MO_32 : MO_64));</div>\r\n" - "<div>+ assert(vece <= (in_32 ? MO_UL : MO_64));</div>\r\n" - "<div> assert(in_32 == NULL || in_64 == NULL);</div>\r\n" - "<div> </div>\r\n" - "<div> /* If we're storing 0, expand oprsz to maxsz. */</div>\r\n" - "<div>@@ -485,7 +485,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> use a 64-bit operation unless the 32-bit operation would</div>\r\n" - "<div> be simple enough. */</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64</div>\r\n" - "<div>- && (vece != MO_32 || !check_size_impl(oprsz, 4))) {</div>\r\n" - "<div>+ && (vece != MO_UL || !check_size_impl(oprsz, 4))) {</div>\r\n" - "<div> t_64 = tcg_temp_new_i64();</div>\r\n" - "<div> tcg_gen_extu_i32_i64(t_64, in_32);</div>\r\n" - "<div> gen_dup_i64(vece, t_64, t_64);</div>\r\n" - "<div>@@ -1430,7 +1430,7 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> uint32_t maxsz, TCGv_i32 in)</div>\r\n" - "<div> {</div>\r\n" - "<div> check_size_align(oprsz, maxsz, dofs);</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_32);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UL);</div>\r\n" - "<div> do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1453,7 +1453,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs);</div>\r\n" - "<div> do_dup_store(type, dofs, oprsz, maxsz, t_vec);</div>\r\n" - "<div> tcg_temp_free_vec(t_vec);</div>\r\n" - "<div>- } else if (vece <= MO_32) {</div>\r\n" - "<div>+ } else if (vece <= MO_UL) {</div>\r\n" - "<div> TCGv_i32 in = tcg_temp_new_i32();</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div>@@ -1519,7 +1519,7 @@ void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> uint32_t maxsz, uint32_t x)</div>\r\n" - "<div> {</div>\r\n" - "<div> check_size_align(oprsz, maxsz, dofs);</div>\r\n" - "<div>- do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div>+ do_dup(MO_UL, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div>@@ -1618,7 +1618,7 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_add32,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_add_i64,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_add64,</div>\r\n" - "<div>@@ -1649,7 +1649,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_adds32,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_add_i64,</div>\r\n" - "<div> .fniv = tcg_gen_add_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_adds64,</div>\r\n" - "<div>@@ -1690,7 +1690,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_subs32,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_sub_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_subs64,</div>\r\n" - "<div>@@ -1769,7 +1769,7 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sub32,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_sub_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sub64,</div>\r\n" - "<div>@@ -1800,7 +1800,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_mul32,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_mul_i64,</div>\r\n" - "<div> .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_mul64,</div>\r\n" - "<div>@@ -1829,7 +1829,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_muls32,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_mul_i64,</div>\r\n" - "<div> .fniv = tcg_gen_mul_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_muls64,</div>\r\n" - "<div>@@ -1866,7 +1866,7 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_ssadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ssadd32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fniv = tcg_gen_ssadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ssadd64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1892,7 +1892,7 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_sssub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sssub32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fniv = tcg_gen_sssub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sssub64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>@@ -1935,7 +1935,7 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_usadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_usadd32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_usadd_i64,</div>\r\n" - "<div> .fniv = tcg_gen_usadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_usadd64,</div>\r\n" - "<div>@@ -1979,7 +1979,7 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_ussub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ussub32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_ussub_i64,</div>\r\n" - "<div> .fniv = tcg_gen_ussub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ussub64,</div>\r\n" - "<div>@@ -2007,7 +2007,7 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_smin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smin32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_smin_i64,</div>\r\n" - "<div> .fniv = tcg_gen_smin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smin64,</div>\r\n" - "<div>@@ -2035,7 +2035,7 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_umin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umin32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_umin_i64,</div>\r\n" - "<div> .fniv = tcg_gen_umin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umin64,</div>\r\n" - "<div>@@ -2063,7 +2063,7 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_smax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smax32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_smax_i64,</div>\r\n" - "<div> .fniv = tcg_gen_smax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smax64,</div>\r\n" - "<div>@@ -2091,7 +2091,7 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_umax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umax32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_umax_i64,</div>\r\n" - "<div> .fniv = tcg_gen_umax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umax64,</div>\r\n" - "<div>@@ -2165,7 +2165,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_neg_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_neg32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_neg_i64,</div>\r\n" - "<div> .fniv = tcg_gen_neg_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_neg64,</div>\r\n" - "<div>@@ -2228,7 +2228,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_abs_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_abs32,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_abs_i64,</div>\r\n" - "<div> .fniv = tcg_gen_abs_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_abs64,</div>\r\n" - "<div>@@ -2485,7 +2485,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shli_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl32i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_shli_i64,</div>\r\n" - "<div> .fniv = tcg_gen_shli_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl64i,</div>\r\n" - "<div>@@ -2536,7 +2536,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shri_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr32i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_shri_i64,</div>\r\n" - "<div> .fniv = tcg_gen_shri_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr64i,</div>\r\n" - "<div>@@ -2601,7 +2601,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sari_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar32i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_sari_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sari_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar64i,</div>\r\n" - "<div>@@ -2736,7 +2736,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Otherwise fall back to integral... */</div>\r\n" - "<div>- if (vece == MO_32 && check_size_impl(oprsz, 4)) {</div>\r\n" - "<div>+ if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div>\r\n" - "<div> expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4);</div>\r\n" - "<div> } else if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div>\r\n" - "<div> TCGv_i64 sh64 = tcg_temp_new_i64();</div>\r\n" - "<div>@@ -2889,7 +2889,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shlv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl32v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_shl_mod_i64,</div>\r\n" - "<div> .fniv = tcg_gen_shlv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl64v,</div>\r\n" - "<div>@@ -2952,7 +2952,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_shrv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr32v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_shr_mod_i64,</div>\r\n" - "<div> .fniv = tcg_gen_shrv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr64v,</div>\r\n" - "<div>@@ -3015,7 +3015,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_sarv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar32v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_32 },</div>\r\n" - "<div>+ .vece = MO_UL },</div>\r\n" - "<div> { .fni8 = tcg_gen_sar_mod_i64,</div>\r\n" - "<div> .fniv = tcg_gen_sarv_mod_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar64v,</div>\r\n" - "<div>@@ -3168,7 +3168,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div>\r\n" - "<div> case 0:</div>\r\n" - "<div> if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div>\r\n" - "<div> expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);</div>\r\n" - "<div>- } else if (vece == MO_32 && check_size_impl(oprsz, 4)) {</div>\r\n" - "<div>+ } else if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div>\r\n" - "<div> expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> gen_helper_gvec_3 * const *fn = fns[cond];</div>\r\n" - "<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div>\r\n" - "<div>index b0a4d98..ff723ab 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-vec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-vec.c</div>\r\n" - "<div>@@ -216,7 +216,7 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)</div>\r\n" - "<div>+#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_UL)</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -253,7 +253,7 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)</div>\r\n" - "<div> void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {</div>\r\n" - "<div>- do_dupi_vec(r, MO_32, a);</div>\r\n" - "<div>+ do_dupi_vec(r, MO_UL, a);</div>\r\n" - "<div> } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {</div>\r\n" - "<div> do_dupi_vec(r, MO_64, a);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -265,7 +265,7 @@ void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)</div>\r\n" - "<div> {</div>\r\n" - "<div>- do_dupi_vec(r, MO_REG, dup_const(MO_32, a));</div>\r\n" - "<div>+ do_dupi_vec(r, MO_REG, dup_const(MO_UL, a));</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)</div>\r\n" - "<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div>\r\n" - "<div>index 21d448c..447683d 100644</div>\r\n" - "<div>--- a/tcg/tcg-op.c</div>\r\n" - "<div>+++ b/tcg/tcg-op.c</div>\r\n" - "<div>@@ -2725,7 +2725,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_UW:</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> if (!is64) {</div>\r\n" - "<div> op &= ~MO_SIGN;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2816,7 +2816,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> tcg_gen_ext16s_i32(val, val);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_bswap32_i32(val, val);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -2841,7 +2841,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> tcg_gen_ext16u_i32(swap, val);</div>\r\n" - "<div> tcg_gen_bswap16_i32(swap, swap);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_bswap32_i32(swap, val);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -2896,7 +2896,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> tcg_gen_ext16s_i64(val, val);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_bswap32_i64(val, val);</div>\r\n" - "<div> if (orig_memop & MO_SIGN) {</div>\r\n" - "<div> tcg_gen_ext32s_i64(val, val);</div>\r\n" - "<div>@@ -2932,7 +2932,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> tcg_gen_ext16u_i64(swap, val);</div>\r\n" - "<div> tcg_gen_bswap16_i64(swap, swap);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_32:</div>\r\n" - "<div>+ case MO_UL:</div>\r\n" - "<div> tcg_gen_ext32u_i64(swap, val);</div>\r\n" - "<div> tcg_gen_bswap32_i64(swap, swap);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -3027,8 +3027,8 @@ static void * const table_cmpxchg[16] = {</div>\r\n" - "<div> [MO_UB] = gen_helper_atomic_cmpxchgb,</div>\r\n" - "<div> [MO_UW | MO_LE] = gen_helper_atomic_cmpxchgw_le,</div>\r\n" - "<div> [MO_UW | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div>\r\n" - "<div>- [MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div>\r\n" - "<div>- [MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div>\r\n" - "<div>+ [MO_UL | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div>\r\n" - "<div>+ [MO_UL | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div>\r\n" - "<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div>\r\n" - "<div> WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be)</div>\r\n" - "<div> };</div>\r\n" - "<div>@@ -3251,8 +3251,8 @@ static void * const table_##NAME[16] = { \\</div>\r\n" - "<div> [MO_UB] = gen_helper_atomic_##NAME##b, \\</div>\r\n" - "<div> [MO_UW | MO_LE] = gen_helper_atomic_##NAME##w_le, \\</div>\r\n" - "<div> [MO_UW | MO_BE] = gen_helper_atomic_##NAME##w_be, \\</div>\r\n" - "<div>- [MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \\</div>\r\n" - "<div>- [MO_32 | MO_BE] = gen_helper_atomic_##NAME##l_be, \\</div>\r\n" - "<div>+ [MO_UL | MO_LE] = gen_helper_atomic_##NAME##l_le, \\</div>\r\n" - "<div>+ [MO_UL | MO_BE] = gen_helper_atomic_##NAME##l_be, \\</div>\r\n" - "<div> WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \\</div>\r\n" - "<div> WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \\</div>\r\n" - "<div> }; \\</div>\r\n" - "<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div>\r\n" - "<div>index a378887..4b6ee89 100644</div>\r\n" - "<div>--- a/tcg/tcg.h</div>\r\n" - "<div>+++ b/tcg/tcg.h</div>\r\n" - "<div>@@ -1304,7 +1304,7 @@ uint64_t dup_const(unsigned vece, uint64_t c);</div>\r\n" - "<div> (__builtin_constant_p(VECE) \\</div>\r\n" - "<div> ? ((VECE) == MO_UB ? 0x0101010101010101ull * (uint8_t)(C) \\</div>\r\n" - "<div> : (VECE) == MO_UW ? 0x0001000100010001ull * (uint16_t)(C) \\</div>\r\n" - "<div>- : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \\</div>\r\n" - "<div>+ : (VECE) == MO_UL ? 0x0000000100000001ull * (uint32_t)(C) \\</div>\r\n" - "<div> : dup_const(VECE, C)) \\</div>\r\n" - "<div> : dup_const(VECE, C))</div>\r\n" - "<div> </div>\r\n" - "<div>-- </div>\r\n" - "<div>1.8.3.1</div>\r\n" - "<div><br>\r\n" - "<br>\r\n" - "</div>\r\n" - "<p><br>\r\n" - "</p>\r\n" - "</body>\r\n" - "</html>\r\n" -aaa117d11d2661ebb47bb83a86b669e2f12ee050f4397e3d02b7871d52011846 +b1a5121a78bedd2a69cb42057ca00061606d2c86559e9b6b133a02c566a0b98a
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