diff for duplicates of <1563810162081.40323@bt.com> diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index f079080..0000000 --- a/a/2.bin +++ /dev/null @@ -1,3300 +0,0 @@ -<html> -<head> -<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> -<style type="text/css" style="display:none"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style> -</head> -<body dir="ltr" style="font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;"> -<p></p> -<div><span style="font-size: 12pt;">Preparation for splitting MO_64 out from TCGMemOp into new accelerator</span><br> -</div> -<div>independent MemOp.</div> -<div><br> -</div> -<div>As MO_64 will be a value of MemOp, existing TCGMemOp comparisons and</div> -<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div> -<div><br> -</div> -<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div> -<div>---</div> -<div> target/arm/sve_helper.c | 2 +-</div> -<div> target/arm/translate-a64.c | 270 ++++++++++++++++++------------------</div> -<div> target/arm/translate-sve.c | 18 +--</div> -<div> target/arm/translate-vfp.inc.c | 4 +-</div> -<div> target/arm/translate.c | 30 ++--</div> -<div> target/i386/translate.c | 122 ++++++++--------</div> -<div> target/mips/translate.c | 2 +-</div> -<div> target/ppc/translate.c | 28 ++--</div> -<div> target/ppc/translate/fp-impl.inc.c | 4 +-</div> -<div> target/ppc/translate/vmx-impl.inc.c | 34 ++---</div> -<div> target/ppc/translate/vsx-impl.inc.c | 18 +--</div> -<div> target/s390x/translate.c | 4 +-</div> -<div> target/s390x/translate_vx.inc.c | 6 +-</div> -<div> target/s390x/vec.h | 4 +-</div> -<div> target/sparc/translate.c | 4 +-</div> -<div> tcg/aarch64/tcg-target.inc.c | 20 +--</div> -<div> tcg/arm/tcg-target.inc.c | 12 +-</div> -<div> tcg/i386/tcg-target.inc.c | 42 +++---</div> -<div> tcg/mips/tcg-target.inc.c | 12 +-</div> -<div> tcg/ppc/tcg-target.inc.c | 18 +--</div> -<div> tcg/riscv/tcg-target.inc.c | 6 +-</div> -<div> tcg/s390/tcg-target.inc.c | 10 +-</div> -<div> tcg/sparc/tcg-target.inc.c | 8 +-</div> -<div> tcg/tcg-op-gvec.c | 132 +++++++++---------</div> -<div> tcg/tcg-op-vec.c | 14 +-</div> -<div> tcg/tcg-op.c | 24 ++--</div> -<div> tcg/tcg.h | 9 +-</div> -<div> 27 files changed, 430 insertions(+), 427 deletions(-)</div> -<div><br> -</div> -<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div> -<div>index fa705c4..1cfd746 100644</div> -<div>--- a/target/arm/sve_helper.c</div> -<div>+++ b/target/arm/sve_helper.c</div> -<div>@@ -5165,7 +5165,7 @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,</div> -<div> target_ulong addr;</div> -<div> </div> -<div> /* Skip to the first true predicate. */</div> -<div>- reg_off = find_next_active(vg, 0, reg_max, MO_64);</div> -<div>+ reg_off = find_next_active(vg, 0, reg_max, MO_UQ);</div> -<div> if (likely(reg_off < reg_max)) {</div> -<div> /* Perform one normal read, which will fault or not. */</div> -<div> set_helper_retaddr(ra);</div> -<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div> -<div>index 0b92e6d..3f9d103 100644</div> -<div>--- a/target/arm/translate-a64.c</div> -<div>+++ b/target/arm/translate-a64.c</div> -<div>@@ -463,7 +463,7 @@ static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)</div> -<div> /* Offset of the high half of the 128 bit vector Qn */</div> -<div> static inline int fp_reg_hi_offset(DisasContext *s, int regno)</div> -<div> {</div> -<div>- return vec_reg_offset(s, regno, 1, MO_64);</div> -<div>+ return vec_reg_offset(s, regno, 1, MO_UQ);</div> -<div> }</div> -<div> </div> -<div> /* Convenience accessors for reading and writing single and double</div> -<div>@@ -476,7 +476,7 @@ static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)</div> -<div> {</div> -<div> TCGv_i64 v = tcg_temp_new_i64();</div> -<div> </div> -<div>- tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));</div> -<div>+ tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_UQ));</div> -<div> return v;</div> -<div> }</div> -<div> </div> -<div>@@ -501,7 +501,7 @@ static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)</div> -<div> */</div> -<div> static void clear_vec_high(DisasContext *s, bool is_q, int rd)</div> -<div> {</div> -<div>- unsigned ofs = fp_reg_offset(s, rd, MO_64);</div> -<div>+ unsigned ofs = fp_reg_offset(s, rd, MO_UQ);</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div> </div> -<div> if (!is_q) {</div> -<div>@@ -516,7 +516,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)</div> -<div> </div> -<div> void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)</div> -<div> {</div> -<div>- unsigned ofs = fp_reg_offset(s, reg, MO_64);</div> -<div>+ unsigned ofs = fp_reg_offset(s, reg, MO_UQ);</div> -<div> </div> -<div> tcg_gen_st_i64(v, cpu_env, ofs);</div> -<div> clear_vec_high(s, false, reg);</div> -<div>@@ -918,7 +918,7 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)</div> -<div> {</div> -<div> /* This writes the bottom N bits of a 128 bit wide vector to memory */</div> -<div> TCGv_i64 tmp = tcg_temp_new_i64();</div> -<div>- tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64));</div> -<div>+ tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_UQ));</div> -<div> if (size < 4) {</div> -<div> tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s),</div> -<div> s->be_data + size);</div> -<div>@@ -928,10 +928,10 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)</div> -<div> </div> -<div> tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);</div> -<div> tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),</div> -<div>- s->be_data | MO_Q);</div> -<div>+ s->be_data | MO_UQ);</div> -<div> tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx));</div> -<div> tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),</div> -<div>- s->be_data | MO_Q);</div> -<div>+ s->be_data | MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_hiaddr);</div> -<div> }</div> -<div> </div> -<div>@@ -960,13 +960,13 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)</div> -<div> </div> -<div> tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);</div> -<div> tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),</div> -<div>- s->be_data | MO_Q);</div> -<div>+ s->be_data | MO_UQ);</div> -<div> tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),</div> -<div>- s->be_data | MO_Q);</div> -<div>+ s->be_data | MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_hiaddr);</div> -<div> }</div> -<div> </div> -<div>- tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));</div> -<div>+ tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_UQ));</div> -<div> tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));</div> -<div> </div> -<div> tcg_temp_free_i64(tmplo);</div> -<div>@@ -1011,8 +1011,8 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> case MO_SL:</div> -<div> tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>- case MO_64|MO_SIGN:</div> -<div>+ case MO_UQ:</div> -<div>+ case MO_SQ:</div> -<div> tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -1061,7 +1061,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div> -<div> case MO_UL:</div> -<div> tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_st_i64(tcg_src, cpu_env, vect_off);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -2207,7 +2207,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div> -<div> g_assert(size >= 2);</div> -<div> if (size == 2) {</div> -<div> /* The pair must be single-copy atomic for the doubleword. */</div> -<div>- memop |= MO_64 | MO_ALIGN;</div> -<div>+ memop |= MO_UQ | MO_ALIGN;</div> -<div> tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);</div> -<div> if (s->be_data == MO_LE) {</div> -<div> tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32);</div> -<div>@@ -2219,7 +2219,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div> -<div> } else {</div> -<div> /* The pair must be single-copy atomic for *each* doubleword, not</div> -<div> the entire quadword, however it must be quadword aligned. */</div> -<div>- memop |= MO_64;</div> -<div>+ memop |= MO_UQ;</div> -<div> tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx,</div> -<div> memop | MO_ALIGN_16);</div> -<div> </div> -<div>@@ -2271,7 +2271,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,</div> -<div> tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,</div> -<div> cpu_exclusive_val, tmp,</div> -<div> get_mem_index(s),</div> -<div>- MO_64 | MO_ALIGN | s->be_data);</div> -<div>+ MO_UQ | MO_ALIGN | s->be_data);</div> -<div> tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);</div> -<div> } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {</div> -<div> if (!HAVE_CMPXCHG128) {</div> -<div>@@ -2355,7 +2355,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,</div> -<div> }</div> -<div> </div> -<div> tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx,</div> -<div>- MO_64 | MO_ALIGN | s->be_data);</div> -<div>+ MO_UQ | MO_ALIGN | s->be_data);</div> -<div> tcg_temp_free_i64(val);</div> -<div> </div> -<div> if (s->be_data == MO_LE) {</div> -<div>@@ -2389,9 +2389,9 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,</div> -<div> </div> -<div> /* Load the two words, in memory order. */</div> -<div> tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,</div> -<div>- MO_64 | MO_ALIGN_16 | s->be_data);</div> -<div>+ MO_UQ | MO_ALIGN_16 | s->be_data);</div> -<div> tcg_gen_addi_i64(a2, clean_addr, 8);</div> -<div>- tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data);</div> -<div>+ tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_UQ | s->be_data);</div> -<div> </div> -<div> /* Compare the two words, also in memory order. */</div> -<div> tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1);</div> -<div>@@ -2401,8 +2401,8 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,</div> -<div> /* If compare equal, write back new data, else write back old data. */</div> -<div> tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1);</div> -<div> tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2);</div> -<div>- tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data);</div> -<div>- tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data);</div> -<div>+ tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_UQ | s->be_data);</div> -<div>+ tcg_gen_qemu_st_i64(c2, a2, memidx, MO_UQ | s->be_data);</div> -<div> tcg_temp_free_i64(a2);</div> -<div> tcg_temp_free_i64(c1);</div> -<div> tcg_temp_free_i64(c2);</div> -<div>@@ -5271,7 +5271,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div> -<div> TCGv_i64 tcg_flags = tcg_temp_new_i64();</div> -<div> TCGv_ptr fpst = get_fpstatus_ptr(size == MO_UW);</div> -<div> </div> -<div>- if (size == MO_64) {</div> -<div>+ if (size == MO_UQ) {</div> -<div> TCGv_i64 tcg_vn, tcg_vm;</div> -<div> </div> -<div> tcg_vn = read_fp_dreg(s, rn);</div> -<div>@@ -5357,7 +5357,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)</div> -<div> size = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div>- size = MO_64;</div> -<div>+ size = MO_UQ;</div> -<div> break;</div> -<div> case 3:</div> -<div> size = MO_UW;</div> -<div>@@ -5408,7 +5408,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)</div> -<div> size = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div>- size = MO_64;</div> -<div>+ size = MO_UQ;</div> -<div> break;</div> -<div> case 3:</div> -<div> size = MO_UW;</div> -<div>@@ -5474,7 +5474,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div> -<div> sz = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div>- sz = MO_64;</div> -<div>+ sz = MO_UQ;</div> -<div> break;</div> -<div> case 3:</div> -<div> sz = MO_UW;</div> -<div>@@ -6279,7 +6279,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div> -<div> sz = MO_UL;</div> -<div> break;</div> -<div> case 1:</div> -<div>- sz = MO_64;</div> -<div>+ sz = MO_UQ;</div> -<div> break;</div> -<div> case 3:</div> -<div> sz = MO_UW;</div> -<div>@@ -6585,7 +6585,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)</div> -<div> break;</div> -<div> case 1:</div> -<div> /* 64 bit */</div> -<div>- tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64));</div> -<div>+ tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_UQ));</div> -<div> break;</div> -<div> case 2:</div> -<div> /* 64 bits from top half */</div> -<div>@@ -6819,9 +6819,9 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)</div> -<div> * extracting 64 bits from a 64:64 concatenation.</div> -<div> */</div> -<div> if (!is_q) {</div> -<div>- read_vec_element(s, tcg_resl, rn, 0, MO_64);</div> -<div>+ read_vec_element(s, tcg_resl, rn, 0, MO_UQ);</div> -<div> if (pos != 0) {</div> -<div>- read_vec_element(s, tcg_resh, rm, 0, MO_64);</div> -<div>+ read_vec_element(s, tcg_resh, rm, 0, MO_UQ);</div> -<div> do_ext64(s, tcg_resh, tcg_resl, pos);</div> -<div> }</div> -<div> tcg_gen_movi_i64(tcg_resh, 0);</div> -<div>@@ -6839,22 +6839,22 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)</div> -<div> pos -= 64;</div> -<div> }</div> -<div> </div> -<div>- read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64);</div> -<div>+ read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_UQ);</div> -<div> elt++;</div> -<div>- read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64);</div> -<div>+ read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_UQ);</div> -<div> elt++;</div> -<div> if (pos != 0) {</div> -<div> do_ext64(s, tcg_resh, tcg_resl, pos);</div> -<div> tcg_hh = tcg_temp_new_i64();</div> -<div>- read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64);</div> -<div>+ read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_UQ);</div> -<div> do_ext64(s, tcg_hh, tcg_resh, pos);</div> -<div> tcg_temp_free_i64(tcg_hh);</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>- write_vec_element(s, tcg_resl, rd, 0, MO_64);</div> -<div>+ write_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_resl);</div> -<div>- write_vec_element(s, tcg_resh, rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_resh);</div> -<div> }</div> -<div> </div> -<div>@@ -6895,12 +6895,12 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)</div> -<div> tcg_resh = tcg_temp_new_i64();</div> -<div> </div> -<div> if (is_tblx) {</div> -<div>- read_vec_element(s, tcg_resl, rd, 0, MO_64);</div> -<div>+ read_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div> -<div> } else {</div> -<div> tcg_gen_movi_i64(tcg_resl, 0);</div> -<div> }</div> -<div> if (is_tblx && is_q) {</div> -<div>- read_vec_element(s, tcg_resh, rd, 1, MO_64);</div> -<div>+ read_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div> -<div> } else {</div> -<div> tcg_gen_movi_i64(tcg_resh, 0);</div> -<div> }</div> -<div>@@ -6908,11 +6908,11 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)</div> -<div> tcg_idx = tcg_temp_new_i64();</div> -<div> tcg_regno = tcg_const_i32(rn);</div> -<div> tcg_numregs = tcg_const_i32(len + 1);</div> -<div>- read_vec_element(s, tcg_idx, rm, 0, MO_64);</div> -<div>+ read_vec_element(s, tcg_idx, rm, 0, MO_UQ);</div> -<div> gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,</div> -<div> tcg_regno, tcg_numregs);</div> -<div> if (is_q) {</div> -<div>- read_vec_element(s, tcg_idx, rm, 1, MO_64);</div> -<div>+ read_vec_element(s, tcg_idx, rm, 1, MO_UQ);</div> -<div> gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,</div> -<div> tcg_regno, tcg_numregs);</div> -<div> }</div> -<div>@@ -6920,9 +6920,9 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)</div> -<div> tcg_temp_free_i32(tcg_regno);</div> -<div> tcg_temp_free_i32(tcg_numregs);</div> -<div> </div> -<div>- write_vec_element(s, tcg_resl, rd, 0, MO_64);</div> -<div>+ write_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_resl);</div> -<div>- write_vec_element(s, tcg_resh, rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_resh);</div> -<div> }</div> -<div> </div> -<div>@@ -7009,9 +7009,9 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_res);</div> -<div> </div> -<div>- write_vec_element(s, tcg_resl, rd, 0, MO_64);</div> -<div>+ write_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_resl);</div> -<div>- write_vec_element(s, tcg_resh, rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_resh);</div> -<div> }</div> -<div> </div> -<div>@@ -7625,9 +7625,9 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)</div> -<div> } else {</div> -<div> /* ORR or BIC, with BIC negation to AND handled above. */</div> -<div> if (is_neg) {</div> -<div>- gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64);</div> -<div>+ gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_UQ);</div> -<div> } else {</div> -<div>- gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64);</div> -<div>+ gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_UQ);</div> -<div> }</div> -<div> }</div> -<div> }</div> -<div>@@ -7702,7 +7702,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div> -<div> size = MO_UW;</div> -<div> }</div> -<div> } else {</div> -<div>- size = extract32(size, 0, 1) ? MO_64 : MO_UL;</div> -<div>+ size = extract32(size, 0, 1) ? MO_UQ : MO_UL;</div> -<div> }</div> -<div> </div> -<div> if (!fp_access_check(s)) {</div> -<div>@@ -7716,13 +7716,13 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div> -<div> return;</div> -<div> }</div> -<div> </div> -<div>- if (size == MO_64) {</div> -<div>+ if (size == MO_UQ) {</div> -<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, rn, 0, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rn, 1, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, 0, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rn, 1, MO_UQ);</div> -<div> </div> -<div> switch (opcode) {</div> -<div> case 0x3b: /* ADDP */</div> -<div>@@ -8085,9 +8085,9 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,</div> -<div> }</div> -<div> </div> -<div> if (!is_q) {</div> -<div>- write_vec_element(s, tcg_final, rd, 0, MO_64);</div> -<div>+ write_vec_element(s, tcg_final, rd, 0, MO_UQ);</div> -<div> } else {</div> -<div>- write_vec_element(s, tcg_final, rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_final, rd, 1, MO_UQ);</div> -<div> }</div> -<div> </div> -<div> if (round) {</div> -<div>@@ -8155,9 +8155,9 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div> -<div> for (pass = 0; pass < maxpass; pass++) {</div> -<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> genfn(tcg_op, cpu_env, tcg_op, tcg_shift);</div> -<div>- write_vec_element(s, tcg_op, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_op, rd, pass, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_op);</div> -<div> }</div> -<div>@@ -8228,11 +8228,11 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div> -<div> TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);</div> -<div> int pass;</div> -<div> </div> -<div>- if (fracbits || size == MO_64) {</div> -<div>+ if (fracbits || size == MO_UQ) {</div> -<div> tcg_shift = tcg_const_i32(fracbits);</div> -<div> }</div> -<div> </div> -<div>- if (size == MO_64) {</div> -<div>+ if (size == MO_UQ) {</div> -<div> TCGv_i64 tcg_int64 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_double = tcg_temp_new_i64();</div> -<div> </div> -<div>@@ -8249,7 +8249,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div> -<div> if (elements == 1) {</div> -<div> write_fp_dreg(s, rd, tcg_double);</div> -<div> } else {</div> -<div>- write_vec_element(s, tcg_double, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_double, rd, pass, MO_UQ);</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>@@ -8331,7 +8331,7 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,</div> -<div> int immhb = immh << 3 | immb;</div> -<div> </div> -<div> if (immh & 8) {</div> -<div>- size = MO_64;</div> -<div>+ size = MO_UQ;</div> -<div> if (!is_scalar && !is_q) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div>@@ -8376,7 +8376,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div> -<div> TCGv_i32 tcg_rmode, tcg_shift;</div> -<div> </div> -<div> if (immh & 0x8) {</div> -<div>- size = MO_64;</div> -<div>+ size = MO_UQ;</div> -<div> if (!is_scalar && !is_q) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div>@@ -8408,19 +8408,19 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div> -<div> fracbits = (16 << size) - immhb;</div> -<div> tcg_shift = tcg_const_i32(fracbits);</div> -<div> </div> -<div>- if (size == MO_64) {</div> -<div>+ if (size == MO_UQ) {</div> -<div> int maxpass = is_scalar ? 1 : 2;</div> -<div> </div> -<div> for (pass = 0; pass < maxpass; pass++) {</div> -<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> if (is_u) {</div> -<div> gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);</div> -<div> } else {</div> -<div> gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);</div> -<div> }</div> -<div>- write_vec_element(s, tcg_op, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_op, rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_op);</div> -<div> }</div> -<div> clear_vec_high(s, is_q, rd);</div> -<div>@@ -8601,7 +8601,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)</div> -<div> tcg_gen_neg_i64(tcg_res, tcg_res);</div> -<div> /* fall through */</div> -<div> case 0x9: /* SQDMLAL, SQDMLAL2 */</div> -<div>- read_vec_element(s, tcg_op1, rd, 0, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rd, 0, MO_UQ);</div> -<div> gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,</div> -<div> tcg_res, tcg_op1);</div> -<div> break;</div> -<div>@@ -8751,8 +8751,8 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div> -<div> </div> -<div> switch (fpopcode) {</div> -<div> case 0x39: /* FMLS */</div> -<div>@@ -8760,7 +8760,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div> -<div> gen_helper_vfp_negd(tcg_op1, tcg_op1);</div> -<div> /* fall through */</div> -<div> case 0x19: /* FMLA */</div> -<div>- read_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,</div> -<div> tcg_res, fpst);</div> -<div> break;</div> -<div>@@ -8820,7 +8820,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div> -<div> g_assert_not_reached();</div> -<div> }</div> -<div> </div> -<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_res);</div> -<div> tcg_temp_free_i64(tcg_op1);</div> -<div>@@ -8905,7 +8905,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div> -<div> TCGv_i64 tcg_tmp = tcg_temp_new_i64();</div> -<div> </div> -<div> tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);</div> -<div>- write_vec_element(s, tcg_tmp, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_tmp, rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_tmp);</div> -<div> } else {</div> -<div> write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div> -<div>@@ -9381,7 +9381,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div> -<div> bool is_scalar, bool is_u, bool is_q,</div> -<div> int size, int rn, int rd)</div> -<div> {</div> -<div>- bool is_double = (size == MO_64);</div> -<div>+ bool is_double = (size == MO_UQ);</div> -<div> TCGv_ptr fpst;</div> -<div> </div> -<div> if (!fp_access_check(s)) {</div> -<div>@@ -9419,13 +9419,13 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> if (swap) {</div> -<div> genfn(tcg_res, tcg_zero, tcg_op, fpst);</div> -<div> } else {</div> -<div> genfn(tcg_res, tcg_op, tcg_zero, fpst);</div> -<div> }</div> -<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> }</div> -<div> tcg_temp_free_i64(tcg_res);</div> -<div> tcg_temp_free_i64(tcg_zero);</div> -<div>@@ -9526,7 +9526,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div> -<div> int pass;</div> -<div> </div> -<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> switch (opcode) {</div> -<div> case 0x3d: /* FRECPE */</div> -<div> gen_helper_recpe_f64(tcg_res, tcg_op, fpst);</div> -<div>@@ -9540,7 +9540,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div> -<div> default:</div> -<div> g_assert_not_reached();</div> -<div> }</div> -<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> }</div> -<div> tcg_temp_free_i64(tcg_res);</div> -<div> tcg_temp_free_i64(tcg_op);</div> -<div>@@ -9615,7 +9615,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,</div> -<div> if (scalar) {</div> -<div> read_vec_element(s, tcg_op, rn, pass, size + 1);</div> -<div> } else {</div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> }</div> -<div> tcg_res[pass] = tcg_temp_new_i32();</div> -<div> </div> -<div>@@ -9711,15 +9711,15 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div> -<div> int pass;</div> -<div> </div> -<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div> -<div>- read_vec_element(s, tcg_rn, rn, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_rd, rd, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_rn, rn, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_rd, rd, pass, MO_UQ);</div> -<div> </div> -<div> if (is_u) { /* USQADD */</div> -<div> gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);</div> -<div> } else { /* SUQADD */</div> -<div> gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);</div> -<div> }</div> -<div>- write_vec_element(s, tcg_rd, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_rd, rd, pass, MO_UQ);</div> -<div> }</div> -<div> tcg_temp_free_i64(tcg_rd);</div> -<div> tcg_temp_free_i64(tcg_rn);</div> -<div>@@ -9776,7 +9776,7 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div> -<div> </div> -<div> if (is_scalar) {</div> -<div> TCGv_i64 tcg_zero = tcg_const_i64(0);</div> -<div>- write_vec_element(s, tcg_zero, rd, 0, MO_64);</div> -<div>+ write_vec_element(s, tcg_zero, rd, 0, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_zero);</div> -<div> }</div> -<div> write_vec_element_i32(s, tcg_rd, rd, pass, MO_UL);</div> -<div>@@ -10146,7 +10146,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,</div> -<div> * so if rd == rn we would overwrite parts of our input.</div> -<div> * So load everything right now and use shifts in the main loop.</div> -<div> */</div> -<div>- read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);</div> -<div>+ read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_UQ);</div> -<div> </div> -<div> for (i = 0; i < elements; i++) {</div> -<div> tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);</div> -<div>@@ -10183,7 +10183,7 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,</div> -<div> tcg_rn = tcg_temp_new_i64();</div> -<div> tcg_rd = tcg_temp_new_i64();</div> -<div> tcg_final = tcg_temp_new_i64();</div> -<div>- read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);</div> -<div>+ read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_UQ);</div> -<div> </div> -<div> if (round) {</div> -<div> uint64_t round_const = 1ULL << (shift - 1);</div> -<div>@@ -10201,9 +10201,9 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,</div> -<div> }</div> -<div> </div> -<div> if (!is_q) {</div> -<div>- write_vec_element(s, tcg_final, rd, 0, MO_64);</div> -<div>+ write_vec_element(s, tcg_final, rd, 0, MO_UQ);</div> -<div> } else {</div> -<div>- write_vec_element(s, tcg_final, rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_final, rd, 1, MO_UQ);</div> -<div> }</div> -<div> if (round) {</div> -<div> tcg_temp_free_i64(tcg_round);</div> -<div>@@ -10335,8 +10335,8 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div> -<div> }</div> -<div> </div> -<div> if (accop != 0) {</div> -<div>- read_vec_element(s, tcg_res[0], rd, 0, MO_64);</div> -<div>- read_vec_element(s, tcg_res[1], rd, 1, MO_64);</div> -<div>+ read_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div> -<div> }</div> -<div> </div> -<div> /* size == 2 means two 32x32->64 operations; this is worth special</div> -<div>@@ -10522,8 +10522,8 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div> -<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div> -<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_res[0]);</div> -<div> tcg_temp_free_i64(tcg_res[1]);</div> -<div> }</div> -<div>@@ -10546,7 +10546,7 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,</div> -<div> };</div> -<div> NeonGenWidenFn *widenfn = widenfns[size][is_u];</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div> -<div> read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_UL);</div> -<div> widenfn(tcg_op2_wide, tcg_op2);</div> -<div> tcg_temp_free_i32(tcg_op2);</div> -<div>@@ -10558,7 +10558,7 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_res[pass]);</div> -<div> }</div> -<div> }</div> -<div>@@ -10589,8 +10589,8 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,</div> -<div> };</div> -<div> NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div> -<div> </div> -<div> gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);</div> -<div> </div> -<div>@@ -10621,12 +10621,12 @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, rn, is_q, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rm, is_q, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, is_q, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rm, is_q, MO_UQ);</div> -<div> gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2);</div> -<div>- write_vec_element(s, tcg_res, rd, 0, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, 0, MO_UQ);</div> -<div> gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2);</div> -<div>- write_vec_element(s, tcg_res, rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, 1, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_op1);</div> -<div> tcg_temp_free_i64(tcg_op2);</div> -<div>@@ -10814,8 +10814,8 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> int passreg = (pass == 0) ? rn : rm;</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, passreg, 0, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, passreg, 1, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, passreg, 0, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, passreg, 1, MO_UQ);</div> -<div> tcg_res[pass] = tcg_temp_new_i64();</div> -<div> </div> -<div> switch (opcode) {</div> -<div>@@ -10846,7 +10846,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_res[pass]);</div> -<div> }</div> -<div> } else {</div> -<div>@@ -10971,7 +10971,7 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> }</div> -<div>- handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_UL,</div> -<div>+ handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_UQ : MO_UL,</div> -<div> rn, rm, rd);</div> -<div> return;</div> -<div> case 0x1b: /* FMULX */</div> -<div>@@ -11155,12 +11155,12 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div> -<div> </div> -<div> handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);</div> -<div> </div> -<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_res);</div> -<div> tcg_temp_free_i64(tcg_op1);</div> -<div>@@ -11714,7 +11714,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div> -<div> tcg_temp_free_i32(tcg_op);</div> -<div> }</div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_res[pass]);</div> -<div> }</div> -<div> } else {</div> -<div>@@ -11774,7 +11774,7 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div> -<div> case MO_UL:</div> -<div> tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -11803,8 +11803,8 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div> -<div> tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);</div> -<div> }</div> -<div> }</div> -<div>- write_vec_element(s, tcg_rd, rd, 0, MO_64);</div> -<div>- write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_rd, rd, 0, MO_UQ);</div> -<div>+ write_vec_element(s, tcg_rd_hi, rd, 1, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_rd_hi);</div> -<div> tcg_temp_free_i64(tcg_rd);</div> -<div>@@ -11839,7 +11839,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div> -<div> read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);</div> -<div> tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);</div> -<div> if (accum) {</div> -<div>- read_vec_element(s, tcg_op1, rd, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rd, pass, MO_UQ);</div> -<div> tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);</div> -<div> }</div> -<div> </div> -<div>@@ -11859,11 +11859,11 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div> -<div> </div> -<div> tcg_res[pass] = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> genfn(tcg_res[pass], tcg_op);</div> -<div> </div> -<div> if (accum) {</div> -<div>- read_vec_element(s, tcg_op, rd, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rd, pass, MO_UQ);</div> -<div> if (size == 0) {</div> -<div> gen_helper_neon_addl_u16(tcg_res[pass],</div> -<div> tcg_res[pass], tcg_op);</div> -<div>@@ -11879,7 +11879,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div> -<div> tcg_res[1] = tcg_const_i64(0);</div> -<div> }</div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_res[pass]);</div> -<div> }</div> -<div> }</div> -<div>@@ -11909,7 +11909,7 @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_res[pass]);</div> -<div> }</div> -<div> }</div> -<div>@@ -12233,12 +12233,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> </div> -<div> handle_2misc_64(s, opcode, u, tcg_res, tcg_op,</div> -<div> tcg_rmode, tcg_fpstatus);</div> -<div> </div> -<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_res);</div> -<div> tcg_temp_free_i64(tcg_op);</div> -<div>@@ -12856,7 +12856,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> is_fp16 = true;</div> -<div> break;</div> -<div> case MO_UL: /* single precision */</div> -<div>- case MO_64: /* double precision */</div> -<div>+ case MO_UQ: /* double precision */</div> -<div> break;</div> -<div> default:</div> -<div> unallocated_encoding(s);</div> -<div>@@ -12875,7 +12875,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> }</div> -<div> is_fp16 = true;</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> break;</div> -<div> default:</div> -<div> unallocated_encoding(s);</div> -<div>@@ -12886,7 +12886,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> default: /* integer */</div> -<div> switch (size) {</div> -<div> case MO_UB:</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div> }</div> -<div>@@ -12906,7 +12906,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> index = h << 1 | l;</div> -<div> rm |= m << 4;</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (l || !is_q) {</div> -<div> unallocated_encoding(s);</div> -<div> return;</div> -<div>@@ -12946,7 +12946,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> vec_full_reg_offset(s, rn),</div> -<div> vec_full_reg_offset(s, rm), fpst,</div> -<div> is_q ? 16 : 8, vec_full_reg_size(s), data,</div> -<div>- size == MO_64</div> -<div>+ size == MO_UQ</div> -<div> ? gen_helper_gvec_fcmlas_idx</div> -<div> : gen_helper_gvec_fcmlah_idx);</div> -<div> tcg_temp_free_ptr(fpst);</div> -<div>@@ -12976,13 +12976,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> assert(is_fp && is_q && !is_long);</div> -<div> </div> -<div>- read_vec_element(s, tcg_idx, rm, index, MO_64);</div> -<div>+ read_vec_element(s, tcg_idx, rm, index, MO_UQ);</div> -<div> </div> -<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div> -<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div> -<div> </div> -<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div> -<div> </div> -<div> switch (16 * u + opcode) {</div> -<div> case 0x05: /* FMLS */</div> -<div>@@ -12990,7 +12990,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> gen_helper_vfp_negd(tcg_op, tcg_op);</div> -<div> /* fall through */</div> -<div> case 0x01: /* FMLA */</div> -<div>- read_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);</div> -<div> break;</div> -<div> case 0x09: /* FMUL */</div> -<div>@@ -13003,7 +13003,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> g_assert_not_reached();</div> -<div> }</div> -<div> </div> -<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_op);</div> -<div> tcg_temp_free_i64(tcg_res);</div> -<div> }</div> -<div>@@ -13241,7 +13241,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> }</div> -<div> </div> -<div> /* Accumulating op: handle accumulate step */</div> -<div>- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> </div> -<div> switch (opcode) {</div> -<div> case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */</div> -<div>@@ -13316,7 +13316,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> }</div> -<div> </div> -<div> /* Accumulating op: handle accumulate step */</div> -<div>- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> </div> -<div> switch (opcode) {</div> -<div> case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */</div> -<div>@@ -13352,7 +13352,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> }</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div> -<div> tcg_temp_free_i64(tcg_res[pass]);</div> -<div> }</div> -<div> }</div> -<div>@@ -13639,14 +13639,14 @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)</div> -<div> tcg_res[1] = tcg_temp_new_i64();</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div> -<div> </div> -<div> tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);</div> -<div> tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);</div> -<div> }</div> -<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div> -<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div> -<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_op1);</div> -<div> tcg_temp_free_i64(tcg_op2);</div> -<div>@@ -13750,9 +13750,9 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)</div> -<div> tcg_res[1] = tcg_temp_new_i64();</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_op3, ra, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op3, ra, pass, MO_UQ);</div> -<div> </div> -<div> if (op0 == 0) {</div> -<div> /* EOR3 */</div> -<div>@@ -13763,8 +13763,8 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)</div> -<div> }</div> -<div> tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);</div> -<div> }</div> -<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div> -<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div> -<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_op1);</div> -<div> tcg_temp_free_i64(tcg_op2);</div> -<div>@@ -13832,14 +13832,14 @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)</div> -<div> tcg_res[1] = tcg_temp_new_i64();</div> -<div> </div> -<div> for (pass = 0; pass < 2; pass++) {</div> -<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div> -<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div> -<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div> -<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div> -<div> </div> -<div> tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);</div> -<div> tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6);</div> -<div> }</div> -<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div> -<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div> -<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div> -<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div> -<div> </div> -<div> tcg_temp_free_i64(tcg_op1);</div> -<div> tcg_temp_free_i64(tcg_op2);</div> -<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div> -<div>index f7c891d..423c461 100644</div> -<div>--- a/target/arm/translate-sve.c</div> -<div>+++ b/target/arm/translate-sve.c</div> -<div>@@ -1708,7 +1708,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div> -<div> tcg_temp_free_i64(t64);</div> -<div> break;</div> -<div> </div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (u) {</div> -<div> if (d) {</div> -<div> gen_helper_sve_uqsubi_d(dptr, nptr, val, desc);</div> -<div>@@ -1862,7 +1862,7 @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)</div> -<div> }</div> -<div> if (sve_access_check(s)) {</div> -<div> unsigned vsz = vec_full_reg_size(s);</div> -<div>- gvec_fn(MO_64, vec_full_reg_offset(s, a->rd),</div> -<div>+ gvec_fn(MO_UQ, vec_full_reg_offset(s, a->rd),</div> -<div> vec_full_reg_offset(s, a->rn), imm, vsz, vsz);</div> -<div> }</div> -<div> return true;</div> -<div>@@ -2076,7 +2076,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)</div> -<div> {</div> -<div> if (sve_access_check(s)) {</div> -<div> TCGv_i64 t = tcg_temp_new_i64();</div> -<div>- tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64));</div> -<div>+ tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_UQ));</div> -<div> do_insr_i64(s, a, t);</div> -<div> tcg_temp_free_i64(t);</div> -<div> }</div> -<div>@@ -3327,7 +3327,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div> -<div> .fno = gen_helper_sve_subri_d,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64,</div> -<div>+ .vece = MO_UQ,</div> -<div> .scalar_first = true }</div> -<div> };</div> -<div> </div> -<div>@@ -4571,7 +4571,7 @@ static const TCGMemOp dtype_mop[16] = {</div> -<div> MO_UB, MO_UB, MO_UB, MO_UB,</div> -<div> MO_SL, MO_UW, MO_UW, MO_UW,</div> -<div> MO_SW, MO_SW, MO_UL, MO_UL,</div> -<div>- MO_SB, MO_SB, MO_SB, MO_Q</div> -<div>+ MO_SB, MO_SB, MO_SB, MO_UQ</div> -<div> };</div> -<div> </div> -<div> #define dtype_msz(x) (dtype_mop[x] & MO_SIZE)</div> -<div>@@ -5261,7 +5261,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)</div> -<div> case MO_UL:</div> -<div> fn = gather_load_fn32[be][a->ff][a->xs][a->u][a->msz];</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> fn = gather_load_fn64[be][a->ff][a->xs][a->u][a->msz];</div> -<div> break;</div> -<div> }</div> -<div>@@ -5289,7 +5289,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)</div> -<div> case MO_UL:</div> -<div> fn = gather_load_fn32[be][a->ff][0][a->u][a->msz];</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> fn = gather_load_fn64[be][a->ff][2][a->u][a->msz];</div> -<div> break;</div> -<div> }</div> -<div>@@ -5367,7 +5367,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)</div> -<div> case MO_UL:</div> -<div> fn = scatter_store_fn32[be][a->xs][a->msz];</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> fn = scatter_store_fn64[be][a->xs][a->msz];</div> -<div> break;</div> -<div> default:</div> -<div>@@ -5395,7 +5395,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)</div> -<div> case MO_UL:</div> -<div> fn = scatter_store_fn32[be][0][a->msz];</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> fn = scatter_store_fn64[be][2][a->msz];</div> -<div> break;</div> -<div> }</div> -<div>diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c</div> -<div>index 5e0cd63..d71944d 100644</div> -<div>--- a/target/arm/translate-vfp.inc.c</div> -<div>+++ b/target/arm/translate-vfp.inc.c</div> -<div>@@ -40,7 +40,7 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8)</div> -<div> uint64_t imm;</div> -<div> </div> -<div> switch (size) {</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |</div> -<div> (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |</div> -<div> extract32(imm8, 0, 6);</div> -<div>@@ -1960,7 +1960,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>- fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));</div> -<div>+ fd = tcg_const_i64(vfp_expand_imm(MO_UQ, a->imm));</div> -<div> </div> -<div> for (;;) {</div> -<div> neon_store_reg64(fd, vd);</div> -<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div> -<div>index 5510ecd..306ef24 100644</div> -<div>--- a/target/arm/translate.c</div> -<div>+++ b/target/arm/translate.c</div> -<div>@@ -1171,7 +1171,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div> -<div> static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,</div> -<div> TCGv_i32 a32, int index)</div> -<div> {</div> -<div>- gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);</div> -<div>+ gen_aa32_ld_i64(s, val, a32, index, MO_UQ | s->be_data);</div> -<div> }</div> -<div> </div> -<div> static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div> -<div>@@ -1194,7 +1194,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div> -<div> static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,</div> -<div> TCGv_i32 a32, int index)</div> -<div> {</div> -<div>- gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);</div> -<div>+ gen_aa32_st_i64(s, val, a32, index, MO_UQ | s->be_data);</div> -<div> }</div> -<div> </div> -<div> DO_GEN_LD(8s, MO_SB)</div> -<div>@@ -1455,7 +1455,7 @@ static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)</div> -<div> case MO_UL:</div> -<div> tcg_gen_ld32u_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_ld_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -1502,7 +1502,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div> -<div> case MO_UL:</div> -<div> tcg_gen_st32_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_st_i64(var, cpu_env, offset);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -4278,7 +4278,7 @@ const GVecGen2i ssra_op[4] = {</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div> .opt_opc = vecop_list_ssra,</div> -<div> .load_dest = true,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div>@@ -4336,7 +4336,7 @@ const GVecGen2i usra_op[4] = {</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_usra,</div> -<div>- .vece = MO_64, },</div> -<div>+ .vece = MO_UQ, },</div> -<div> };</div> -<div> </div> -<div> static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div>@@ -4416,7 +4416,7 @@ const GVecGen2i sri_op[4] = {</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sri,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div> -<div>@@ -4494,7 +4494,7 @@ const GVecGen2i sli_op[4] = {</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_sli,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)</div> -<div>@@ -4590,7 +4590,7 @@ const GVecGen3 mla_op[4] = {</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mla,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> const GVecGen3 mls_op[4] = {</div> -<div>@@ -4614,7 +4614,7 @@ const GVecGen3 mls_op[4] = {</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div> .load_dest = true,</div> -<div> .opt_opc = vecop_list_mls,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> /* CMTST : test is "if (X & Y != 0)". */</div> -<div>@@ -4658,7 +4658,7 @@ const GVecGen3 cmtst_op[4] = {</div> -<div> .fniv = gen_cmtst_vec,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div> .opt_opc = vecop_list_cmtst,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div> -<div>@@ -4696,7 +4696,7 @@ const GVecGen4 uqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqadd_d,</div> -<div> .write_aofs = true,</div> -<div> .opt_opc = vecop_list_uqadd,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> static void gen_sqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div> -<div>@@ -4734,7 +4734,7 @@ const GVecGen4 sqadd_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqadd_d,</div> -<div> .opt_opc = vecop_list_sqadd,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> static void gen_uqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div> -<div>@@ -4772,7 +4772,7 @@ const GVecGen4 uqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_uqsub_d,</div> -<div> .opt_opc = vecop_list_uqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> static void gen_sqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div> -<div>@@ -4810,7 +4810,7 @@ const GVecGen4 sqsub_op[4] = {</div> -<div> .fno = gen_helper_gvec_sqsub_d,</div> -<div> .opt_opc = vecop_list_sqsub,</div> -<div> .write_aofs = true,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div> /* Translate a NEON data processing instruction. Return nonzero if the</div> -<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div> -<div>index 0e863d4..8d62b37 100644</div> -<div>--- a/target/i386/translate.c</div> -<div>+++ b/target/i386/translate.c</div> -<div>@@ -323,7 +323,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int reg)</div> -<div> static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div> -<div> {</div> -<div> if (CODE64(s)) {</div> -<div>- return ot == MO_UW ? MO_UW : MO_64;</div> -<div>+ return ot == MO_UW ? MO_UW : MO_UQ;</div> -<div> } else {</div> -<div> return ot;</div> -<div> }</div> -<div>@@ -332,14 +332,14 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div> -<div> /* Select the size of the stack pointer. */</div> -<div> static inline TCGMemOp mo_stacksize(DisasContext *s)</div> -<div> {</div> -<div>- return CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div> -<div>+ return CODE64(s) ? MO_UQ : s->ss32 ? MO_UL : MO_UW;</div> -<div> }</div> -<div> </div> -<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div> -<div> static inline TCGMemOp mo_64_32(TCGMemOp ot)</div> -<div> {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- return ot == MO_64 ? MO_64 : MO_UL;</div> -<div>+ return ot == MO_UQ ? MO_UQ : MO_UL;</div> -<div> #else</div> -<div> return MO_UL;</div> -<div> #endif</div> -<div>@@ -378,7 +378,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div> tcg_gen_ext32u_tl(cpu_regs[reg], t0);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_mov_tl(cpu_regs[reg], t0);</div> -<div> break;</div> -<div> #endif</div> -<div>@@ -456,7 +456,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div> -<div> {</div> -<div> switch (aflag) {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (ovr_seg < 0) {</div> -<div> tcg_gen_mov_tl(s->A0, a0);</div> -<div> return;</div> -<div>@@ -492,7 +492,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div> -<div> if (ovr_seg >= 0) {</div> -<div> TCGv seg = cpu_seg_base[ovr_seg];</div> -<div> </div> -<div>- if (aflag == MO_64) {</div> -<div>+ if (aflag == MO_UQ) {</div> -<div> tcg_gen_add_tl(s->A0, a0, seg);</div> -<div> } else if (CODE64(s)) {</div> -<div> tcg_gen_ext32u_tl(s->A0, a0);</div> -<div>@@ -1469,7 +1469,7 @@ static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,</div> -<div> static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> int is_right, int is_arith)</div> -<div> {</div> -<div>- target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div>+ target_ulong mask = (ot == MO_UQ ? 0x3f : 0x1f);</div> -<div> </div> -<div> /* load */</div> -<div> if (op1 == OR_TMP0) {</div> -<div>@@ -1505,7 +1505,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> int is_right, int is_arith)</div> -<div> {</div> -<div>- int mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div>+ int mask = (ot == MO_UQ ? 0x3f : 0x1f);</div> -<div> </div> -<div> /* load */</div> -<div> if (op1 == OR_TMP0)</div> -<div>@@ -1544,7 +1544,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> </div> -<div> static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div> -<div> {</div> -<div>- target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div>+ target_ulong mask = (ot == MO_UQ ? 0x3f : 0x1f);</div> -<div> TCGv_i32 t0, t1;</div> -<div> </div> -<div> /* load */</div> -<div>@@ -1630,7 +1630,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div> -<div> static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> int is_right)</div> -<div> {</div> -<div>- int mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div>+ int mask = (ot == MO_UQ ? 0x3f : 0x1f);</div> -<div> int shift;</div> -<div> </div> -<div> /* load */</div> -<div>@@ -1729,7 +1729,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> gen_helper_rcrl(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> gen_helper_rcrq(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> #endif</div> -<div>@@ -1748,7 +1748,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> gen_helper_rcll(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> gen_helper_rclq(s->T0, cpu_env, s->T0, s->T1);</div> -<div> break;</div> -<div> #endif</div> -<div>@@ -1764,7 +1764,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> bool is_right, TCGv count_in)</div> -<div> {</div> -<div>- target_ulong mask = (ot == MO_64 ? 63 : 31);</div> -<div>+ target_ulong mask = (ot == MO_UQ ? 63 : 31);</div> -<div> TCGv count;</div> -<div> </div> -<div> /* load */</div> -<div>@@ -1983,7 +1983,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,</div> -<div> }</div> -<div> </div> -<div> switch (s->aflag) {</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> case MO_UL:</div> -<div> havesib = 0;</div> -<div> if (rm == 4) {</div> -<div>@@ -2192,7 +2192,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div> -<div> break;</div> -<div> case MO_UL:</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> #endif</div> -<div> ret = x86_ldl_code(env, s);</div> -<div> break;</div> -<div>@@ -2443,7 +2443,7 @@ static void gen_popa(DisasContext *s)</div> -<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div> -<div> {</div> -<div> TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div> -<div>+ TCGMemOp a_ot = CODE64(s) ? MO_UQ : s->ss32 ? MO_UL : MO_UW;</div> -<div> int size = 1 << d_ot;</div> -<div> </div> -<div> /* Push BP; compute FrameTemp into T1. */</div> -<div>@@ -3150,8 +3150,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> break;</div> -<div> case 0x6e: /* movd mm, ea */</div> -<div> #ifdef TARGET_X86_64</div> -<div>- if (s->dflag == MO_64) {</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);</div> -<div>+ if (s->dflag == MO_UQ) {</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 0);</div> -<div> tcg_gen_st_tl(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State, fpregs[reg].mmx));</div> -<div> } else</div> -<div>@@ -3166,8 +3166,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> break;</div> -<div> case 0x16e: /* movd xmm, ea */</div> -<div> #ifdef TARGET_X86_64</div> -<div>- if (s->dflag == MO_64) {</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);</div> -<div>+ if (s->dflag == MO_UQ) {</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 0);</div> -<div> tcg_gen_addi_ptr(s->ptr0, cpu_env,</div> -<div> offsetof(CPUX86State,xmm_regs[reg]));</div> -<div> gen_helper_movq_mm_T0_xmm(s->ptr0, s->T0);</div> -<div>@@ -3337,10 +3337,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> break;</div> -<div> case 0x7e: /* movd ea, mm */</div> -<div> #ifdef TARGET_X86_64</div> -<div>- if (s->dflag == MO_64) {</div> -<div>+ if (s->dflag == MO_UQ) {</div> -<div> tcg_gen_ld_i64(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State,fpregs[reg].mmx));</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 1);</div> -<div> } else</div> -<div> #endif</div> -<div> {</div> -<div>@@ -3351,10 +3351,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> break;</div> -<div> case 0x17e: /* movd ea, xmm */</div> -<div> #ifdef TARGET_X86_64</div> -<div>- if (s->dflag == MO_64) {</div> -<div>+ if (s->dflag == MO_UQ) {</div> -<div> tcg_gen_ld_i64(s->T0, cpu_env,</div> -<div> offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));</div> -<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);</div> -<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 1);</div> -<div> } else</div> -<div> #endif</div> -<div> {</div> -<div>@@ -3785,10 +3785,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> }</div> -<div> if ((b & 0xff) == 0xf0) {</div> -<div> ot = MO_UB;</div> -<div>- } else if (s->dflag != MO_64) {</div> -<div>+ } else if (s->dflag != MO_UQ) {</div> -<div> ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div> -<div> } else {</div> -<div>- ot = MO_64;</div> -<div>+ ot = MO_UQ;</div> -<div> }</div> -<div> </div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[reg]);</div> -<div>@@ -3814,10 +3814,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div>- if (s->dflag != MO_64) {</div> -<div>+ if (s->dflag != MO_UQ) {</div> -<div> ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div> -<div> } else {</div> -<div>- ot = MO_64;</div> -<div>+ ot = MO_UQ;</div> -<div> }</div> -<div> </div> -<div> gen_lea_modrm(env, s, modrm);</div> -<div>@@ -3861,7 +3861,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> tcg_gen_ext8u_tl(s->A0, cpu_regs[s->vex_v]);</div> -<div> tcg_gen_shr_tl(s->T0, s->T0, s->A0);</div> -<div> </div> -<div>- bound = tcg_const_tl(ot == MO_64 ? 63 : 31);</div> -<div>+ bound = tcg_const_tl(ot == MO_UQ ? 63 : 31);</div> -<div> zero = tcg_const_tl(0);</div> -<div> tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound,</div> -<div> s->T0, zero);</div> -<div>@@ -3894,7 +3894,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div> -<div> tcg_gen_ext8u_tl(s->T1, cpu_regs[s->vex_v]);</div> -<div> {</div> -<div>- TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31);</div> -<div>+ TCGv bound = tcg_const_tl(ot == MO_UQ ? 63 : 31);</div> -<div> /* Note that since we're using BMILG (in order to get O</div> -<div> cleared) we need to store the inverse into C. */</div> -<div> tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src,</div> -<div>@@ -3929,7 +3929,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp3_i32);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_mulu2_i64(s->T0, s->T1,</div> -<div> s->T0, cpu_regs[R_EDX]);</div> -<div> tcg_gen_mov_i64(cpu_regs[s->vex_v], s->T0);</div> -<div>@@ -3949,7 +3949,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div> -<div> /* Note that by zero-extending the mask operand, we</div> -<div> automatically handle zero-extending the result. */</div> -<div>- if (ot == MO_64) {</div> -<div>+ if (ot == MO_UQ) {</div> -<div> tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]);</div> -<div> } else {</div> -<div> tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]);</div> -<div>@@ -3967,7 +3967,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div> -<div> /* Note that by zero-extending the mask operand, we</div> -<div> automatically handle zero-extending the result. */</div> -<div>- if (ot == MO_64) {</div> -<div>+ if (ot == MO_UQ) {</div> -<div> tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]);</div> -<div> } else {</div> -<div> tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]);</div> -<div>@@ -4063,7 +4063,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> }</div> -<div> ot = mo_64_32(s->dflag);</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div> -<div>- if (ot == MO_64) {</div> -<div>+ if (ot == MO_UQ) {</div> -<div> tcg_gen_andi_tl(s->T1, cpu_regs[s->vex_v], 63);</div> -<div> } else {</div> -<div> tcg_gen_andi_tl(s->T1, cpu_regs[s->vex_v], 31);</div> -<div>@@ -4071,12 +4071,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> if (b == 0x1f7) {</div> -<div> tcg_gen_shl_tl(s->T0, s->T0, s->T1);</div> -<div> } else if (b == 0x2f7) {</div> -<div>- if (ot != MO_64) {</div> -<div>+ if (ot != MO_UQ) {</div> -<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div> -<div> }</div> -<div> tcg_gen_sar_tl(s->T0, s->T0, s->T1);</div> -<div> } else {</div> -<div>- if (ot != MO_64) {</div> -<div>+ if (ot != MO_UQ) {</div> -<div> tcg_gen_ext32u_tl(s->T0, s->T0);</div> -<div> }</div> -<div> tcg_gen_shr_tl(s->T0, s->T0, s->T1);</div> -<div>@@ -4302,7 +4302,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> if ((b & 0xfc) == 0x60) { /* pcmpXstrX */</div> -<div> set_cc_op(s, CC_OP_EFLAGS);</div> -<div> </div> -<div>- if (s->dflag == MO_64) {</div> -<div>+ if (s->dflag == MO_UQ) {</div> -<div> /* The helper must use entire 64-bit gp registers */</div> -<div> val |= 1 << 8;</div> -<div> }</div> -<div>@@ -4329,7 +4329,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> ot = mo_64_32(s->dflag);</div> -<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div> -<div> b = x86_ldub_code(env, s);</div> -<div>- if (ot == MO_64) {</div> -<div>+ if (ot == MO_UQ) {</div> -<div> tcg_gen_rotri_tl(s->T0, s->T0, b & 63);</div> -<div> } else {</div> -<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div> -<div>@@ -4630,9 +4630,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> /* In 64-bit mode, the default data size is 32-bit. Select 64-bit</div> -<div> data with rex_w, and 16-bit data with 0x66; rex_w takes precedence</div> -<div> over 0x66 if both are present. */</div> -<div>- dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_UL);</div> -<div>+ dflag = (rex_w > 0 ? MO_UQ : prefixes & PREFIX_DATA ? MO_UW : MO_UL);</div> -<div> /* In 64-bit mode, 0x67 selects 32-bit addressing. */</div> -<div>- aflag = (prefixes & PREFIX_ADR ? MO_UL : MO_64);</div> -<div>+ aflag = (prefixes & PREFIX_ADR ? MO_UL : MO_UQ);</div> -<div> } else {</div> -<div> /* In 16/32-bit mode, 0x66 selects the opposite data size. */</div> -<div> if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {</div> -<div>@@ -4903,7 +4903,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> set_cc_op(s, CC_OP_MULL);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],</div> -<div> s->T0, cpu_regs[R_EAX]);</div> -<div> tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);</div> -<div>@@ -4956,7 +4956,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> set_cc_op(s, CC_OP_MULL);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],</div> -<div> s->T0, cpu_regs[R_EAX]);</div> -<div> tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);</div> -<div>@@ -4980,7 +4980,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_helper_divl_EAX(cpu_env, s->T0);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> gen_helper_divq_EAX(cpu_env, s->T0);</div> -<div> break;</div> -<div> #endif</div> -<div>@@ -4999,7 +4999,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> gen_helper_idivl_EAX(cpu_env, s->T0);</div> -<div> break;</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> gen_helper_idivq_EAX(cpu_env, s->T0);</div> -<div> break;</div> -<div> #endif</div> -<div>@@ -5024,7 +5024,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (CODE64(s)) {</div> -<div> if (op == 2 || op == 4) {</div> -<div> /* operand size for jumps is 64 bit */</div> -<div>- ot = MO_64;</div> -<div>+ ot = MO_UQ;</div> -<div> } else if (op == 3 || op == 5) {</div> -<div> ot = dflag != MO_UW ? MO_UL + (rex_w == 1) : MO_UW;</div> -<div> } else if (op == 6) {</div> -<div>@@ -5145,10 +5145,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x98: /* CWDE/CBW */</div> -<div> switch (dflag) {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div> -<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div> -<div>- gen_op_mov_reg_v(s, MO_64, R_EAX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UQ, R_EAX, s->T0);</div> -<div> break;</div> -<div> #endif</div> -<div> case MO_UL:</div> -<div>@@ -5168,10 +5168,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x99: /* CDQ/CWD */</div> -<div> switch (dflag) {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>- gen_op_mov_v_reg(s, MO_64, s->T0, R_EAX);</div> -<div>+ case MO_UQ:</div> -<div>+ gen_op_mov_v_reg(s, MO_UQ, s->T0, R_EAX);</div> -<div> tcg_gen_sari_tl(s->T0, s->T0, 63);</div> -<div>- gen_op_mov_reg_v(s, MO_64, R_EDX, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UQ, R_EDX, s->T0);</div> -<div> break;</div> -<div> #endif</div> -<div> case MO_UL:</div> -<div>@@ -5212,7 +5212,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> }</div> -<div> switch (ot) {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_muls2_i64(cpu_regs[reg], s->T1, s->T0, s->T1);</div> -<div> tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);</div> -<div> tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);</div> -<div>@@ -5338,7 +5338,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> goto illegal_op;</div> -<div> }</div> -<div> #ifdef TARGET_X86_64</div> -<div>- if (dflag == MO_64) {</div> -<div>+ if (dflag == MO_UQ) {</div> -<div> if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) {</div> -<div> goto illegal_op;</div> -<div> }</div> -<div>@@ -5636,7 +5636,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> ot = mo_b_d(b, dflag);</div> -<div> switch (s->aflag) {</div> -<div> #ifdef TARGET_X86_64</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> offset_addr = x86_ldq_code(env, s);</div> -<div> break;</div> -<div> #endif</div> -<div>@@ -5671,13 +5671,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> break;</div> -<div> case 0xb8 ... 0xbf: /* mov R, Iv */</div> -<div> #ifdef TARGET_X86_64</div> -<div>- if (dflag == MO_64) {</div> -<div>+ if (dflag == MO_UQ) {</div> -<div> uint64_t tmp;</div> -<div> /* 64 bit case */</div> -<div> tmp = x86_ldq_code(env, s);</div> -<div> reg = (b & 7) | REX_B(s);</div> -<div> tcg_gen_movi_tl(s->T0, tmp);</div> -<div>- gen_op_mov_reg_v(s, MO_64, reg, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UQ, reg, s->T0);</div> -<div> } else</div> -<div> #endif</div> -<div> {</div> -<div>@@ -7119,10 +7119,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x1c8 ... 0x1cf: /* bswap reg */</div> -<div> reg = (b & 7) | REX_B(s);</div> -<div> #ifdef TARGET_X86_64</div> -<div>- if (dflag == MO_64) {</div> -<div>- gen_op_mov_v_reg(s, MO_64, s->T0, reg);</div> -<div>+ if (dflag == MO_UQ) {</div> -<div>+ gen_op_mov_v_reg(s, MO_UQ, s->T0, reg);</div> -<div> tcg_gen_bswap64_i64(s->T0, s->T0);</div> -<div>- gen_op_mov_reg_v(s, MO_64, reg, s->T0);</div> -<div>+ gen_op_mov_reg_v(s, MO_UQ, reg, s->T0);</div> -<div> } else</div> -<div> #endif</div> -<div> {</div> -<div>@@ -7700,7 +7700,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> if (mod == 3) {</div> -<div> gen_op_mov_v_reg(s, MO_UL, s->T0, rm);</div> -<div> /* sign extend */</div> -<div>- if (d_ot == MO_64) {</div> -<div>+ if (d_ot == MO_UQ) {</div> -<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div> -<div> }</div> -<div> gen_op_mov_reg_v(s, d_ot, reg, s->T0);</div> -<div>@@ -8014,7 +8014,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> rm = (modrm & 7) | REX_B(s);</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div> if (CODE64(s))</div> -<div>- ot = MO_64;</div> -<div>+ ot = MO_UQ;</div> -<div> else</div> -<div> ot = MO_UL;</div> -<div> if ((prefixes & PREFIX_LOCK) && (reg == 0) &&</div> -<div>@@ -8071,7 +8071,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> rm = (modrm & 7) | REX_B(s);</div> -<div> reg = ((modrm >> 3) & 7) | rex_r;</div> -<div> if (CODE64(s))</div> -<div>- ot = MO_64;</div> -<div>+ ot = MO_UQ;</div> -<div> else</div> -<div> ot = MO_UL;</div> -<div> if (reg >= 8) {</div> -<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div> -<div>index 525c7fe..1023f68 100644</div> -<div>--- a/target/mips/translate.c</div> -<div>+++ b/target/mips/translate.c</div> -<div>@@ -3766,7 +3766,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,</div> -<div> </div> -<div> tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));</div> -<div> tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,</div> -<div>- eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);</div> -<div>+ eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_UQ);</div> -<div> if (reg1 != 0) {</div> -<div> tcg_gen_movi_tl(cpu_gpr[reg1], 1);</div> -<div> }</div> -<div>diff --git a/target/ppc/translate.c b/target/ppc/translate.c</div> -<div>index 4a5de28..f39dd94 100644</div> -<div>--- a/target/ppc/translate.c</div> -<div>+++ b/target/ppc/translate.c</div> -<div>@@ -2470,10 +2470,10 @@ GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))</div> -<div> GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))</div> -<div> GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))</div> -<div> GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))</div> -<div>-GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))</div> -<div>+GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ))</div> -<div> </div> -<div> #if defined(TARGET_PPC64)</div> -<div>-GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))</div> -<div>+GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))</div> -<div> #endif</div> -<div> </div> -<div> #define GEN_QEMU_STORE_TL(stop, op) \</div> -<div>@@ -2502,10 +2502,10 @@ static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \</div> -<div> GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))</div> -<div> GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))</div> -<div> GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))</div> -<div>-GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))</div> -<div>+GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ))</div> -<div> </div> -<div> #if defined(TARGET_PPC64)</div> -<div>-GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))</div> -<div>+GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))</div> -<div> #endif</div> -<div> </div> -<div> #define GEN_LD(name, ldop, opc, type) \</div> -<div>@@ -2605,7 +2605,7 @@ GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)</div> -<div> GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)</div> -<div> GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)</div> -<div> #if defined(TARGET_PPC64)</div> -<div>-GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)</div> -<div>+GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)</div> -<div> #endif</div> -<div> </div> -<div> #if defined(TARGET_PPC64)</div> -<div>@@ -2808,7 +2808,7 @@ GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)</div> -<div> GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)</div> -<div> GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)</div> -<div> #if defined(TARGET_PPC64)</div> -<div>-GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)</div> -<div>+GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04)</div> -<div> #endif</div> -<div> </div> -<div> #if defined(TARGET_PPC64)</div> -<div>@@ -3244,7 +3244,7 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)</div> -<div> TCGv t1 = tcg_temp_new();</div> -<div> </div> -<div> tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);</div> -<div>- if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {</div> -<div>+ if ((memop & MO_SIZE) == MO_UQ || TARGET_LONG_BITS == 32) {</div> -<div> tcg_gen_mov_tl(t1, src);</div> -<div> } else {</div> -<div> tcg_gen_ext32u_tl(t1, src);</div> -<div>@@ -3302,7 +3302,7 @@ static void gen_lwat(DisasContext *ctx)</div> -<div> #ifdef TARGET_PPC64</div> -<div> static void gen_ldat(DisasContext *ctx)</div> -<div> {</div> -<div>- gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));</div> -<div>+ gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));</div> -<div> }</div> -<div> #endif</div> -<div> </div> -<div>@@ -3385,7 +3385,7 @@ static void gen_stwat(DisasContext *ctx)</div> -<div> #ifdef TARGET_PPC64</div> -<div> static void gen_stdat(DisasContext *ctx)</div> -<div> {</div> -<div>- gen_st_atomic(ctx, DEF_MEMOP(MO_Q));</div> -<div>+ gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));</div> -<div> }</div> -<div> #endif</div> -<div> </div> -<div>@@ -3437,9 +3437,9 @@ STCX(stwcx_, DEF_MEMOP(MO_UL))</div> -<div> </div> -<div> #if defined(TARGET_PPC64)</div> -<div> /* ldarx */</div> -<div>-LARX(ldarx, DEF_MEMOP(MO_Q))</div> -<div>+LARX(ldarx, DEF_MEMOP(MO_UQ))</div> -<div> /* stdcx. */</div> -<div>-STCX(stdcx_, DEF_MEMOP(MO_Q))</div> -<div>+STCX(stdcx_, DEF_MEMOP(MO_UQ))</div> -<div> </div> -<div> /* lqarx */</div> -<div> static void gen_lqarx(DisasContext *ctx)</div> -<div>@@ -3520,7 +3520,7 @@ static void gen_stqcx_(DisasContext *ctx)</div> -<div> </div> -<div> if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {</div> -<div> if (HAVE_CMPXCHG128) {</div> -<div>- TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);</div> -<div>+ TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_UQ) | MO_ALIGN_16);</div> -<div> if (ctx->le_mode) {</div> -<div> gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,</div> -<div> EA, lo, hi, oi);</div> -<div>@@ -7366,7 +7366,7 @@ GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)</div> -<div> GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)</div> -<div> GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)</div> -<div> #if defined(TARGET_PPC64)</div> -<div>-GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)</div> -<div>+GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)</div> -<div> #endif</div> -<div> </div> -<div> #undef GEN_ST</div> -<div>@@ -7412,7 +7412,7 @@ GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)</div> -<div> GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)</div> -<div> GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)</div> -<div> #if defined(TARGET_PPC64)</div> -<div>-GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)</div> -<div>+GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04)</div> -<div> #endif</div> -<div> </div> -<div> #undef GEN_CRLOGIC</div> -<div>diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c</div> -<div>index 9dcff94..3fd54ac 100644</div> -<div>--- a/target/ppc/translate/fp-impl.inc.c</div> -<div>+++ b/target/ppc/translate/fp-impl.inc.c</div> -<div>@@ -855,7 +855,7 @@ static void gen_lfdepx(DisasContext *ctx)</div> -<div> EA = tcg_temp_new();</div> -<div> t0 = tcg_temp_new_i64();</div> -<div> gen_addr_reg_index(ctx, EA);</div> -<div>- tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q));</div> -<div>+ tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UQ));</div> -<div> set_fpr(rD(ctx->opcode), t0);</div> -<div> tcg_temp_free(EA);</div> -<div> tcg_temp_free_i64(t0);</div> -<div>@@ -1091,7 +1091,7 @@ static void gen_stfdepx(DisasContext *ctx)</div> -<div> t0 = tcg_temp_new_i64();</div> -<div> gen_addr_reg_index(ctx, EA);</div> -<div> get_fpr(t0, rD(ctx->opcode));</div> -<div>- tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q));</div> -<div>+ tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_UQ));</div> -<div> tcg_temp_free(EA);</div> -<div> tcg_temp_free_i64(t0);</div> -<div> }</div> -<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div> -<div>index 8aa767e..867dc52 100644</div> -<div>--- a/target/ppc/translate/vmx-impl.inc.c</div> -<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div> -<div>@@ -290,14 +290,14 @@ static void glue(gen_, name)(DisasContext *ctx) \</div> -<div> }</div> -<div> </div> -<div> /* Logical operations */</div> -<div>-GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);</div> -<div>-GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);</div> -<div>-GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);</div> -<div>-GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);</div> -<div>-GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);</div> -<div>-GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);</div> -<div>-GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);</div> -<div>-GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);</div> -<div>+GEN_VXFORM_V(vand, MO_UQ, tcg_gen_gvec_and, 2, 16);</div> -<div>+GEN_VXFORM_V(vandc, MO_UQ, tcg_gen_gvec_andc, 2, 17);</div> -<div>+GEN_VXFORM_V(vor, MO_UQ, tcg_gen_gvec_or, 2, 18);</div> -<div>+GEN_VXFORM_V(vxor, MO_UQ, tcg_gen_gvec_xor, 2, 19);</div> -<div>+GEN_VXFORM_V(vnor, MO_UQ, tcg_gen_gvec_nor, 2, 20);</div> -<div>+GEN_VXFORM_V(veqv, MO_UQ, tcg_gen_gvec_eqv, 2, 26);</div> -<div>+GEN_VXFORM_V(vnand, MO_UQ, tcg_gen_gvec_nand, 2, 22);</div> -<div>+GEN_VXFORM_V(vorc, MO_UQ, tcg_gen_gvec_orc, 2, 21);</div> -<div> </div> -<div> #define GEN_VXFORM(name, opc2, opc3) \</div> -<div> static void glue(gen_, name)(DisasContext *ctx) \</div> -<div>@@ -410,27 +410,27 @@ GEN_VXFORM_V(vadduhm, MO_UW, tcg_gen_gvec_add, 0, 1);</div> -<div> GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div> -<div> GEN_VXFORM_V(vadduwm, MO_UL, tcg_gen_gvec_add, 0, 2);</div> -<div>-GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div> -<div>+GEN_VXFORM_V(vaddudm, MO_UQ, tcg_gen_gvec_add, 0, 3);</div> -<div> GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div> -<div> GEN_VXFORM_V(vsubuhm, MO_UW, tcg_gen_gvec_sub, 0, 17);</div> -<div> GEN_VXFORM_V(vsubuwm, MO_UL, tcg_gen_gvec_sub, 0, 18);</div> -<div>-GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div> -<div>+GEN_VXFORM_V(vsubudm, MO_UQ, tcg_gen_gvec_sub, 0, 19);</div> -<div> GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div> -<div> GEN_VXFORM_V(vmaxuh, MO_UW, tcg_gen_gvec_umax, 1, 1);</div> -<div> GEN_VXFORM_V(vmaxuw, MO_UL, tcg_gen_gvec_umax, 1, 2);</div> -<div>-GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div> -<div>+GEN_VXFORM_V(vmaxud, MO_UQ, tcg_gen_gvec_umax, 1, 3);</div> -<div> GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div> -<div> GEN_VXFORM_V(vmaxsh, MO_UW, tcg_gen_gvec_smax, 1, 5);</div> -<div> GEN_VXFORM_V(vmaxsw, MO_UL, tcg_gen_gvec_smax, 1, 6);</div> -<div>-GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div> -<div>+GEN_VXFORM_V(vmaxsd, MO_UQ, tcg_gen_gvec_smax, 1, 7);</div> -<div> GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div> -<div> GEN_VXFORM_V(vminuh, MO_UW, tcg_gen_gvec_umin, 1, 9);</div> -<div> GEN_VXFORM_V(vminuw, MO_UL, tcg_gen_gvec_umin, 1, 10);</div> -<div>-GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div> -<div>+GEN_VXFORM_V(vminud, MO_UQ, tcg_gen_gvec_umin, 1, 11);</div> -<div> GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div> -<div> GEN_VXFORM_V(vminsh, MO_UW, tcg_gen_gvec_smin, 1, 13);</div> -<div> GEN_VXFORM_V(vminsw, MO_UL, tcg_gen_gvec_smin, 1, 14);</div> -<div>-GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div> -<div>+GEN_VXFORM_V(vminsd, MO_UQ, tcg_gen_gvec_smin, 1, 15);</div> -<div> GEN_VXFORM(vavgub, 1, 16);</div> -<div> GEN_VXFORM(vabsdub, 1, 16);</div> -<div> GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \</div> -<div>@@ -536,15 +536,15 @@ GEN_VXFORM_V(vslw, MO_UL, tcg_gen_gvec_shlv, 2, 6);</div> -<div> GEN_VXFORM(vrlwnm, 2, 6);</div> -<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \</div> -<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div> -<div>-GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div> -<div>+GEN_VXFORM_V(vsld, MO_UQ, tcg_gen_gvec_shlv, 2, 23);</div> -<div> GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div> -<div> GEN_VXFORM_V(vsrh, MO_UW, tcg_gen_gvec_shrv, 2, 9);</div> -<div> GEN_VXFORM_V(vsrw, MO_UL, tcg_gen_gvec_shrv, 2, 10);</div> -<div>-GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div> -<div>+GEN_VXFORM_V(vsrd, MO_UQ, tcg_gen_gvec_shrv, 2, 27);</div> -<div> GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div> -<div> GEN_VXFORM_V(vsrah, MO_UW, tcg_gen_gvec_sarv, 2, 13);</div> -<div> GEN_VXFORM_V(vsraw, MO_UL, tcg_gen_gvec_sarv, 2, 14);</div> -<div>-GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div> -<div>+GEN_VXFORM_V(vsrad, MO_UQ, tcg_gen_gvec_sarv, 2, 15);</div> -<div> GEN_VXFORM(vsrv, 2, 28);</div> -<div> GEN_VXFORM(vslv, 2, 29);</div> -<div> GEN_VXFORM(vslo, 6, 16);</div> -<div>diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c</div> -<div>index 212817e..d607974 100644</div> -<div>--- a/target/ppc/translate/vsx-impl.inc.c</div> -<div>+++ b/target/ppc/translate/vsx-impl.inc.c</div> -<div>@@ -1475,14 +1475,14 @@ static void glue(gen_, name)(DisasContext *ctx) \</div> -<div> vsr_full_offset(xB(ctx->opcode)), 16, 16); \</div> -<div> }</div> -<div> </div> -<div>-VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)</div> -<div>-VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)</div> -<div>-VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)</div> -<div>-VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)</div> -<div>-VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)</div> -<div>-VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)</div> -<div>-VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)</div> -<div>-VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)</div> -<div>+VSX_LOGICAL(xxland, MO_UQ, tcg_gen_gvec_and)</div> -<div>+VSX_LOGICAL(xxlandc, MO_UQ, tcg_gen_gvec_andc)</div> -<div>+VSX_LOGICAL(xxlor, MO_UQ, tcg_gen_gvec_or)</div> -<div>+VSX_LOGICAL(xxlxor, MO_UQ, tcg_gen_gvec_xor)</div> -<div>+VSX_LOGICAL(xxlnor, MO_UQ, tcg_gen_gvec_nor)</div> -<div>+VSX_LOGICAL(xxleqv, MO_UQ, tcg_gen_gvec_eqv)</div> -<div>+VSX_LOGICAL(xxlnand, MO_UQ, tcg_gen_gvec_nand)</div> -<div>+VSX_LOGICAL(xxlorc, MO_UQ, tcg_gen_gvec_orc)</div> -<div> </div> -<div> #define VSX_XXMRG(name, high) \</div> -<div> static void glue(gen_, name)(DisasContext *ctx) \</div> -<div>@@ -1535,7 +1535,7 @@ static void gen_xxsel(DisasContext *ctx)</div> -<div> gen_exception(ctx, POWERPC_EXCP_VSXU);</div> -<div> return;</div> -<div> }</div> -<div>- tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc),</div> -<div>+ tcg_gen_gvec_bitsel(MO_UQ, vsr_full_offset(rt), vsr_full_offset(rc),</div> -<div> vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);</div> -<div> }</div> -<div> </div> -<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div> -<div>index 9e646f1..5c72db1 100644</div> -<div>--- a/target/s390x/translate.c</div> -<div>+++ b/target/s390x/translate.c</div> -<div>@@ -180,7 +180,7 @@ static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div> -<div> * the two 8 byte elements have to be loaded separately. Let's force all</div> -<div> * 16 byte operations to handle it in a special way.</div> -<div> */</div> -<div>- g_assert(es <= MO_64);</div> -<div>+ g_assert(es <= MO_UQ);</div> -<div> #ifndef HOST_WORDS_BIGENDIAN</div> -<div> offs ^= (8 - bytes);</div> -<div> #endif</div> -<div>@@ -190,7 +190,7 @@ static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div> -<div> static inline int freg64_offset(uint8_t reg)</div> -<div> {</div> -<div> g_assert(reg < 16);</div> -<div>- return vec_reg_offset(reg, 0, MO_64);</div> -<div>+ return vec_reg_offset(reg, 0, MO_UQ);</div> -<div> }</div> -<div> </div> -<div> static inline int freg32_offset(uint8_t reg)</div> -<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div> -<div>index 75d788c..6252262 100644</div> -<div>--- a/target/s390x/translate_vx.inc.c</div> -<div>+++ b/target/s390x/translate_vx.inc.c</div> -<div>@@ -30,8 +30,8 @@</div> -<div> * Sizes:</div> -<div> * On s390x, the operand size (oprsz) and the maximum size (maxsz) are</div> -<div> * always 16 (128 bit). What gvec code calls "vece", s390x calls "es",</div> -<div>- * a.k.a. "element size". These values nicely map to MO_UB ... MO_64. Only</div> -<div>- * 128 bit element size has to be treated in a special way (MO_64 + 1).</div> -<div>+ * a.k.a. "element size". These values nicely map to MO_UB ... MO_UQ. Only</div> -<div>+ * 128 bit element size has to be treated in a special way (MO_UQ + 1).</div> -<div> * We will use ES_* instead of MO_* for this reason in this file.</div> -<div> *</div> -<div> * CC handling:</div> -<div>@@ -49,7 +49,7 @@</div> -<div> #define ES_8 MO_UB</div> -<div> #define ES_16 MO_UW</div> -<div> #define ES_32 MO_UL</div> -<div>-#define ES_64 MO_64</div> -<div>+#define ES_64 MO_UQ</div> -<div> #define ES_128 4</div> -<div> </div> -<div> /* Floating-Point Format */</div> -<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div> -<div>index f67392c..b59da65 100644</div> -<div>--- a/target/s390x/vec.h</div> -<div>+++ b/target/s390x/vec.h</div> -<div>@@ -82,7 +82,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div> -<div> return s390_vec_read_element16(v, enr);</div> -<div> case MO_UL:</div> -<div> return s390_vec_read_element32(v, enr);</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> return s390_vec_read_element64(v, enr);</div> -<div> default:</div> -<div> g_assert_not_reached();</div> -<div>@@ -130,7 +130,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div> -<div> case MO_UL:</div> -<div> s390_vec_write_element32(v, enr, data);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> s390_vec_write_element64(v, enr, data);</div> -<div> break;</div> -<div> default:</div> -<div>diff --git a/target/sparc/translate.c b/target/sparc/translate.c</div> -<div>index 091bab5..499622b 100644</div> -<div>--- a/target/sparc/translate.c</div> -<div>+++ b/target/sparc/translate.c</div> -<div>@@ -2840,7 +2840,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)</div> -<div> default:</div> -<div> {</div> -<div> TCGv_i32 r_asi = tcg_const_i32(da.asi);</div> -<div>- TCGv_i32 r_mop = tcg_const_i32(MO_Q);</div> -<div>+ TCGv_i32 r_mop = tcg_const_i32(MO_UQ);</div> -<div> </div> -<div> save_state(dc);</div> -<div> gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);</div> -<div>@@ -2896,7 +2896,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,</div> -<div> default:</div> -<div> {</div> -<div> TCGv_i32 r_asi = tcg_const_i32(da.asi);</div> -<div>- TCGv_i32 r_mop = tcg_const_i32(MO_Q);</div> -<div>+ TCGv_i32 r_mop = tcg_const_i32(MO_UQ);</div> -<div> </div> -<div> save_state(dc);</div> -<div> gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);</div> -<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div> -<div>index dc4fd21..d14afa9 100644</div> -<div>--- a/tcg/aarch64/tcg-target.inc.c</div> -<div>+++ b/tcg/aarch64/tcg-target.inc.c</div> -<div>@@ -432,12 +432,12 @@ typedef enum {</div> -<div> I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div> -<div> I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_UW << 30,</div> -<div> I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_UL << 30,</div> -<div>- I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div> -<div>+ I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_UQ << 30,</div> -<div> </div> -<div> I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div> -<div> I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_UW << 30,</div> -<div> I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_UL << 30,</div> -<div>- I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div> -<div>+ I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_UQ << 30,</div> -<div> </div> -<div> I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div> -<div> I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_UW << 30,</div> -<div>@@ -449,8 +449,8 @@ typedef enum {</div> -<div> I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_UL << 30,</div> -<div> I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_UL << 30,</div> -<div> </div> -<div>- I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,</div> -<div>- I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,</div> -<div>+ I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_UQ << 30,</div> -<div>+ I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_UQ << 30,</div> -<div> </div> -<div> I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,</div> -<div> I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,</div> -<div>@@ -1595,7 +1595,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> if (opc & MO_SIGN) {</div> -<div> tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0);</div> -<div> } else {</div> -<div>- tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0);</div> -<div>+ tcg_out_mov(s, size == MO_UQ, lb->datalo_reg, TCG_REG_X0);</div> -<div> }</div> -<div> </div> -<div> tcg_out_goto(s, lb->raddr);</div> -<div>@@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> </div> -<div> tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);</div> -<div> tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);</div> -<div>- tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);</div> -<div>+ tcg_out_mov(s, size == MO_UQ, TCG_REG_X2, lb->datalo_reg);</div> -<div> tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi);</div> -<div> tcg_out_adr(s, TCG_REG_X4, lb->raddr);</div> -<div> tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);</div> -<div>@@ -1754,7 +1754,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div> -<div> tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);</div> -<div> if (bswap) {</div> -<div> tcg_out_rev64(s, data_r, data_r);</div> -<div>@@ -1789,7 +1789,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div> -<div> }</div> -<div> tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (bswap && data_r != TCG_REG_XZR) {</div> -<div> tcg_out_rev64(s, TCG_REG_TMP, data_r);</div> -<div> data_r = TCG_REG_TMP;</div> -<div>@@ -1838,7 +1838,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div> -<div> tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);</div> -<div> tcg_out_qemu_st_direct(s, memop, data_reg,</div> -<div> TCG_REG_X1, otype, addr_reg);</div> -<div>- add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,</div> -<div>+ add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE) == MO_UQ,</div> -<div> data_reg, addr_reg, s->code_ptr, label_ptr);</div> -<div> #else /* !CONFIG_SOFTMMU */</div> -<div> if (USE_GUEST_BASE) {</div> -<div>@@ -2506,7 +2506,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> case INDEX_op_smin_vec:</div> -<div> case INDEX_op_umax_vec:</div> -<div> case INDEX_op_umin_vec:</div> -<div>- return vece < MO_64;</div> -<div>+ return vece < MO_UQ;</div> -<div> </div> -<div> default:</div> -<div> return 0;</div> -<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div> -<div>index 05560a2..70eeb8a 100644</div> -<div>--- a/tcg/arm/tcg-target.inc.c</div> -<div>+++ b/tcg/arm/tcg-target.inc.c</div> -<div>@@ -1389,7 +1389,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> default:</div> -<div> tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> if (datalo != TCG_REG_R1) {</div> -<div> tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);</div> -<div> tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);</div> -<div>@@ -1439,7 +1439,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> default:</div> -<div> argreg = tcg_out_arg_reg32(s, argreg, datalo);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi);</div> -<div> break;</div> -<div> }</div> -<div>@@ -1487,7 +1487,7 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,</div> -<div> tcg_out_bswap32(s, COND_AL, datalo, datalo);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> {</div> -<div> TCGReg dl = (bswap ? datahi : datalo);</div> -<div> TCGReg dh = (bswap ? datalo : datahi);</div> -<div>@@ -1548,7 +1548,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc,</div> -<div> tcg_out_bswap32(s, COND_AL, datalo, datalo);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> {</div> -<div> TCGReg dl = (bswap ? datahi : datalo);</div> -<div> TCGReg dh = (bswap ? datalo : datahi);</div> -<div>@@ -1641,7 +1641,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div> -<div> tcg_out_st32_r(s, cond, datalo, addrlo, addend);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> /* Avoid strd for user-only emulation, to handle unaligned. */</div> -<div> if (bswap) {</div> -<div> tcg_out_bswap32(s, cond, TCG_REG_R0, datahi);</div> -<div>@@ -1686,7 +1686,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div> -<div> tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> /* Avoid strd for user-only emulation, to handle unaligned. */</div> -<div> if (bswap) {</div> -<div> tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi);</div> -<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div> -<div>index 93e4c63..3a73334 100644</div> -<div>--- a/tcg/i386/tcg-target.inc.c</div> -<div>+++ b/tcg/i386/tcg-target.inc.c</div> -<div>@@ -902,7 +902,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> /* imm8 operand: all output lanes selected from input lane 0. */</div> -<div> tcg_out8(s, 0);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -921,7 +921,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div> -<div> r, 0, base, offset);</div> -<div> } else {</div> -<div> switch (vece) {</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset);</div> -<div> break;</div> -<div> case MO_UL:</div> -<div>@@ -1868,7 +1868,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> case MO_UL:</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);</div> -<div> } else if (data_reg == TCG_REG_EDX) {</div> -<div>@@ -1923,7 +1923,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs);</div> -<div> ofs += 4;</div> -<div> </div> -<div>- if (s_bits == MO_64) {</div> -<div>+ if (s_bits == MO_UQ) {</div> -<div> tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs);</div> -<div> ofs += 4;</div> -<div> }</div> -<div>@@ -1937,7 +1937,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> } else {</div> -<div> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);</div> -<div> /* The second argument is already loaded with addrlo. */</div> -<div>- tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),</div> -<div>+ tcg_out_mov(s, (s_bits == MO_UQ ? TCG_TYPE_I64 : TCG_TYPE_I32),</div> -<div> tcg_target_call_iarg_regs[2], l->datalo_reg);</div> -<div> tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi);</div> -<div> </div> -<div>@@ -2060,7 +2060,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div> -<div> }</div> -<div> break;</div> -<div> #endif</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,</div> -<div> base, index, 0, ofs);</div> -<div>@@ -2181,7 +2181,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div> -<div> }</div> -<div> tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> if (bswap) {</div> -<div> tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);</div> -<div>@@ -2755,7 +2755,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div> -<div> OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ</div> -<div> };</div> -<div> static int const sarv_insn[4] = {</div> -<div>- /* TODO: AVX512 adds support for MO_UW, MO_64. */</div> -<div>+ /* TODO: AVX512 adds support for MO_UW, MO_UQ. */</div> -<div> OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2</div> -<div> };</div> -<div> static int const shls_insn[4] = {</div> -<div>@@ -2768,7 +2768,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div> -<div> OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2</div> -<div> };</div> -<div> static int const abs_insn[4] = {</div> -<div>- /* TODO: AVX512 adds support for MO_64. */</div> -<div>+ /* TODO: AVX512 adds support for MO_UQ. */</div> -<div> OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2</div> -<div> };</div> -<div> </div> -<div>@@ -2898,7 +2898,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div> -<div> sub = 2;</div> -<div> goto gen_shift;</div> -<div> case INDEX_op_sari_vec:</div> -<div>- tcg_debug_assert(vece != MO_64);</div> -<div>+ tcg_debug_assert(vece != MO_UQ);</div> -<div> sub = 4;</div> -<div> gen_shift:</div> -<div> tcg_debug_assert(vece != MO_UB);</div> -<div>@@ -3281,9 +3281,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> if (vece == MO_UB) {</div> -<div> return -1;</div> -<div> }</div> -<div>- /* We can emulate this for MO_64, but it does not pay off</div> -<div>- unless we're producing at least 4 values. */</div> -<div>- if (vece == MO_64) {</div> -<div>+ /*</div> -<div>+ * We can emulate this for MO_UQ, but it does not pay off</div> -<div>+ * unless we're producing at least 4 values.</div> -<div>+ */</div> -<div>+ if (vece == MO_UQ) {</div> -<div> return type >= TCG_TYPE_V256 ? -1 : 0;</div> -<div> }</div> -<div> return 1;</div> -<div>@@ -3305,7 +3307,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div> -<div> /* We can expand the operation for MO_UB. */</div> -<div> return -1;</div> -<div> }</div> -<div>- if (vece == MO_64) {</div> -<div>+ if (vece == MO_UQ) {</div> -<div> return 0;</div> -<div> }</div> -<div> return 1;</div> -<div>@@ -3389,7 +3391,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div> -<div> tcg_temp_free_vec(t2);</div> -<div> break;</div> -<div> </div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (imm <= 32) {</div> -<div> /* We can emulate a small sign extend by performing an arithmetic</div> -<div> * 32-bit shift and overwriting the high half of a 64-bit logical</div> -<div>@@ -3397,7 +3399,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div> -<div> */</div> -<div> t1 = tcg_temp_new_vec(type);</div> -<div> tcg_gen_sari_vec(MO_UL, t1, v1, imm);</div> -<div>- tcg_gen_shri_vec(MO_64, v0, v1, imm);</div> -<div>+ tcg_gen_shri_vec(MO_UQ, v0, v1, imm);</div> -<div> vec_gen_4(INDEX_op_x86_blend_vec, type, MO_UL,</div> -<div> tcgv_vec_arg(v0), tcgv_vec_arg(v0),</div> -<div> tcgv_vec_arg(t1), 0xaa);</div> -<div>@@ -3407,10 +3409,10 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div> -<div> * the sign-extend, shift and merge.</div> -<div> */</div> -<div> t1 = tcg_const_zeros_vec(type);</div> -<div>- tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);</div> -<div>- tcg_gen_shri_vec(MO_64, v0, v1, imm);</div> -<div>- tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);</div> -<div>- tcg_gen_or_vec(MO_64, v0, v0, t1);</div> -<div>+ tcg_gen_cmp_vec(TCG_COND_GT, MO_UQ, t1, t1, v1);</div> -<div>+ tcg_gen_shri_vec(MO_UQ, v0, v1, imm);</div> -<div>+ tcg_gen_shli_vec(MO_UQ, t1, t1, 64 - imm);</div> -<div>+ tcg_gen_or_vec(MO_UQ, v0, v0, t1);</div> -<div> tcg_temp_free_vec(t1);</div> -<div> }</div> -<div> break;</div> -<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div> -<div>index a78fe87..ef31fc8 100644</div> -<div>--- a/tcg/mips/tcg-target.inc.c</div> -<div>+++ b/tcg/mips/tcg-target.inc.c</div> -<div>@@ -1336,7 +1336,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);</div> -<div> </div> -<div> v0 = l->datalo_reg;</div> -<div>- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {</div> -<div>+ if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_UQ) {</div> -<div> /* We eliminated V0 from the possible output registers, so it</div> -<div> cannot be clobbered here. So we must move V1 first. */</div> -<div> if (MIPS_BE) {</div> -<div>@@ -1389,7 +1389,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> case MO_UL:</div> -<div> i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (TCG_TARGET_REG_BITS == 32) {</div> -<div> i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);</div> -<div> } else {</div> -<div>@@ -1470,7 +1470,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> case MO_SL:</div> -<div> tcg_out_opc_imm(s, OPC_LW, lo, base, 0);</div> -<div> break;</div> -<div>- case MO_Q | MO_BSWAP:</div> -<div>+ case MO_UQ | MO_BSWAP:</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> if (use_mips32r2_instructions) {</div> -<div> tcg_out_opc_imm(s, OPC_LD, lo, base, 0);</div> -<div>@@ -1499,7 +1499,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> /* Prefer to load from offset 0 first, but allow for overlap. */</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> tcg_out_opc_imm(s, OPC_LD, lo, base, 0);</div> -<div>@@ -1587,7 +1587,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> tcg_out_opc_imm(s, OPC_SW, lo, base, 0);</div> -<div> break;</div> -<div> </div> -<div>- case MO_64 | MO_BSWAP:</div> -<div>+ case MO_UQ | MO_BSWAP:</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> tcg_out_bswap64(s, TCG_TMP3, lo);</div> -<div> tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);</div> -<div>@@ -1605,7 +1605,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> tcg_out_opc_imm(s, OPC_SD, lo, base, 0);</div> -<div> } else {</div> -<div>diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c</div> -<div>index 835336a..13a2437 100644</div> -<div>--- a/tcg/ppc/tcg-target.inc.c</div> -<div>+++ b/tcg/ppc/tcg-target.inc.c</div> -<div>@@ -1445,24 +1445,24 @@ static const uint32_t qemu_ldx_opc[16] = {</div> -<div> [MO_UB] = LBZX,</div> -<div> [MO_UW] = LHZX,</div> -<div> [MO_UL] = LWZX,</div> -<div>- [MO_Q] = LDX,</div> -<div>+ [MO_UQ] = LDX,</div> -<div> [MO_SW] = LHAX,</div> -<div> [MO_SL] = LWAX,</div> -<div> [MO_BSWAP | MO_UB] = LBZX,</div> -<div> [MO_BSWAP | MO_UW] = LHBRX,</div> -<div> [MO_BSWAP | MO_UL] = LWBRX,</div> -<div>- [MO_BSWAP | MO_Q] = LDBRX,</div> -<div>+ [MO_BSWAP | MO_UQ] = LDBRX,</div> -<div> };</div> -<div> </div> -<div> static const uint32_t qemu_stx_opc[16] = {</div> -<div> [MO_UB] = STBX,</div> -<div> [MO_UW] = STHX,</div> -<div> [MO_UL] = STWX,</div> -<div>- [MO_Q] = STDX,</div> -<div>+ [MO_UQ] = STDX,</div> -<div> [MO_BSWAP | MO_UB] = STBX,</div> -<div> [MO_BSWAP | MO_UW] = STHBRX,</div> -<div> [MO_BSWAP | MO_UL] = STWBRX,</div> -<div>- [MO_BSWAP | MO_Q] = STDBRX,</div> -<div>+ [MO_BSWAP | MO_UQ] = STDBRX,</div> -<div> };</div> -<div> </div> -<div> static const uint32_t qemu_exts_opc[4] = {</div> -<div>@@ -1663,7 +1663,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> </div> -<div> lo = lb->datalo_reg;</div> -<div> hi = lb->datahi_reg;</div> -<div>- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {</div> -<div>+ if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_UQ) {</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);</div> -<div> tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);</div> -<div> } else if (opc & MO_SIGN) {</div> -<div>@@ -1708,7 +1708,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> hi = lb->datahi_reg;</div> -<div> if (TCG_TARGET_REG_BITS == 32) {</div> -<div> switch (s_bits) {</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> #ifdef TCG_TARGET_CALL_ALIGN_ARGS</div> -<div> arg |= 1;</div> -<div> #endif</div> -<div>@@ -1722,7 +1722,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> break;</div> -<div> }</div> -<div> } else {</div> -<div>- if (s_bits == MO_64) {</div> -<div>+ if (s_bits == MO_UQ) {</div> -<div> tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);</div> -<div> } else {</div> -<div> tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));</div> -<div>@@ -1775,7 +1775,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> }</div> -<div> #endif</div> -<div> </div> -<div>- if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {</div> -<div>+ if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_UQ) {</div> -<div> if (opc & MO_BSWAP) {</div> -<div> tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));</div> -<div> tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));</div> -<div>@@ -1850,7 +1850,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> }</div> -<div> #endif</div> -<div> </div> -<div>- if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {</div> -<div>+ if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_UQ) {</div> -<div> if (opc & MO_BSWAP) {</div> -<div> tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));</div> -<div> tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));</div> -<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div> -<div>index 1905986..90363df 100644</div> -<div>--- a/tcg/riscv/tcg-target.inc.c</div> -<div>+++ b/tcg/riscv/tcg-target.inc.c</div> -<div>@@ -1068,7 +1068,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);</div> -<div> </div> -<div> tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);</div> -<div>- tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);</div> -<div>+ tcg_out_mov(s, (opc & MO_SIZE) == MO_UQ, l->datalo_reg, a0);</div> -<div> </div> -<div> tcg_out_goto(s, l->raddr);</div> -<div> return true;</div> -<div>@@ -1150,7 +1150,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> case MO_SL:</div> -<div> tcg_out_opc_imm(s, OPC_LW, lo, base, 0);</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> /* Prefer to load from offset 0 first, but allow for overlap. */</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> tcg_out_opc_imm(s, OPC_LD, lo, base, 0);</div> -<div>@@ -1225,7 +1225,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div> case MO_UL:</div> -<div> tcg_out_opc_store(s, OPC_SW, base, lo, 0);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> tcg_out_opc_store(s, OPC_SD, base, lo, 0);</div> -<div> } else {</div> -<div>diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c</div> -<div>index fe42939..db1102e 100644</div> -<div>--- a/tcg/s390/tcg-target.inc.c</div> -<div>+++ b/tcg/s390/tcg-target.inc.c</div> -<div>@@ -1477,10 +1477,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div> -<div> tcg_out_insn(s, RXY, LGF, data, base, index, disp);</div> -<div> break;</div> -<div> </div> -<div>- case MO_Q | MO_BSWAP:</div> -<div>+ case MO_UQ | MO_BSWAP:</div> -<div> tcg_out_insn(s, RXY, LRVG, data, base, index, disp);</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> tcg_out_insn(s, RXY, LG, data, base, index, disp);</div> -<div> break;</div> -<div> </div> -<div>@@ -1523,10 +1523,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div> -<div> }</div> -<div> break;</div> -<div> </div> -<div>- case MO_Q | MO_BSWAP:</div> -<div>+ case MO_UQ | MO_BSWAP:</div> -<div> tcg_out_insn(s, RXY, STRVG, data, base, index, disp);</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> tcg_out_insn(s, RXY, STG, data, base, index, disp);</div> -<div> break;</div> -<div> </div> -<div>@@ -1660,7 +1660,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> case MO_UL:</div> -<div> tgen_ext32u(s, TCG_REG_R4, data_reg);</div> -<div> break;</div> -<div>- case MO_Q:</div> -<div>+ case MO_UQ:</div> -<div> tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);</div> -<div> break;</div> -<div> default:</div> -<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div> -<div>index ac0d3a3..7c50118 100644</div> -<div>--- a/tcg/sparc/tcg-target.inc.c</div> -<div>+++ b/tcg/sparc/tcg-target.inc.c</div> -<div>@@ -894,7 +894,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div> -<div> tcg_out_arith(s, r, r, 0, SHIFT_SRL);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> break;</div> -<div> }</div> -<div> }</div> -<div>@@ -977,7 +977,7 @@ static void build_trampolines(TCGContext *s)</div> -<div> } else {</div> -<div> ra += 1;</div> -<div> }</div> -<div>- if ((i & MO_SIZE) == MO_64) {</div> -<div>+ if ((i & MO_SIZE) == MO_UQ) {</div> -<div> /* Install the high part of the data. */</div> -<div> tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);</div> -<div> ra += 2;</div> -<div>@@ -1217,7 +1217,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,</div> -<div> tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);</div> -<div> }</div> -<div> } else {</div> -<div>- if ((memop & MO_SIZE) == MO_64) {</div> -<div>+ if ((memop & MO_SIZE) == MO_UQ) {</div> -<div> tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);</div> -<div> tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);</div> -<div> tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);</div> -<div>@@ -1274,7 +1274,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,</div> -<div> param++;</div> -<div> }</div> -<div> tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);</div> -<div>- if (!SPARC64 && (memop & MO_SIZE) == MO_64) {</div> -<div>+ if (!SPARC64 && (memop & MO_SIZE) == MO_UQ) {</div> -<div> /* Skip the high-part; we'll perform the extract in the trampoline. */</div> -<div> param++;</div> -<div> }</div> -<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div> -<div>index e63622c..0c0eea5 100644</div> -<div>--- a/tcg/tcg-op-gvec.c</div> -<div>+++ b/tcg/tcg-op-gvec.c</div> -<div>@@ -312,7 +312,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div> -<div> return 0x0001000100010001ull * (uint16_t)c;</div> -<div> case MO_UL:</div> -<div> return 0x0000000100000001ull * (uint32_t)c;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> return c;</div> -<div> default:</div> -<div> g_assert_not_reached();</div> -<div>@@ -352,7 +352,7 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div> -<div> case MO_UL:</div> -<div> tcg_gen_deposit_i64(out, in, in, 32, 32);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_mov_i64(out, in);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -443,7 +443,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> TCGv_ptr t_ptr;</div> -<div> uint32_t i;</div> -<div> </div> -<div>- assert(vece <= (in_32 ? MO_UL : MO_64));</div> -<div>+ assert(vece <= (in_32 ? MO_UL : MO_UQ));</div> -<div> assert(in_32 == NULL || in_64 == NULL);</div> -<div> </div> -<div> /* If we're storing 0, expand oprsz to maxsz. */</div> -<div>@@ -459,7 +459,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> */</div> -<div> type = choose_vector_type(NULL, vece, oprsz,</div> -<div> (TCG_TARGET_REG_BITS == 64 && in_32 == NULL</div> -<div>- && (in_64 == NULL || vece == MO_64)));</div> -<div>+ && (in_64 == NULL || vece == MO_UQ)));</div> -<div> if (type != 0) {</div> -<div> TCGv_vec t_vec = tcg_temp_new_vec(type);</div> -<div> </div> -<div>@@ -502,7 +502,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> /* For 64-bit hosts, use 64-bit constants for "simple" constants</div> -<div> or when we'd need too many 32-bit stores, or when a 64-bit</div> -<div> constant is really required. */</div> -<div>- if (vece == MO_64</div> -<div>+ if (vece == MO_UQ</div> -<div> || (TCG_TARGET_REG_BITS == 64</div> -<div> && (in_c == 0 || in_c == -1</div> -<div> || !check_size_impl(oprsz, 4)))) {</div> -<div>@@ -534,7 +534,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);</div> -<div> t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));</div> -<div> </div> -<div>- if (vece == MO_64) {</div> -<div>+ if (vece == MO_UQ) {</div> -<div> if (in_64) {</div> -<div> gen_helper_gvec_dup64(t_ptr, t_desc, in_64);</div> -<div> } else {</div> -<div>@@ -1438,7 +1438,7 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,</div> -<div> uint32_t maxsz, TCGv_i64 in)</div> -<div> {</div> -<div> check_size_align(oprsz, maxsz, dofs);</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);</div> -<div> }</div> -<div> </div> -<div>@@ -1446,7 +1446,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> uint32_t oprsz, uint32_t maxsz)</div> -<div> {</div> -<div> check_size_align(oprsz, maxsz, dofs);</div> -<div>- if (vece <= MO_64) {</div> -<div>+ if (vece <= MO_UQ) {</div> -<div> TCGType type = choose_vector_type(NULL, vece, oprsz, 0);</div> -<div> if (type != 0) {</div> -<div> TCGv_vec t_vec = tcg_temp_new_vec(type);</div> -<div>@@ -1512,7 +1512,7 @@ void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,</div> -<div> uint32_t maxsz, uint64_t x)</div> -<div> {</div> -<div> check_size_align(oprsz, maxsz, dofs);</div> -<div>- do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div>+ do_dup(MO_UQ, dofs, oprsz, maxsz, NULL, NULL, x);</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,</div> -<div>@@ -1624,10 +1624,10 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_add64,</div> -<div> .opt_opc = vecop_list_add,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1655,10 +1655,10 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_adds64,</div> -<div> .opt_opc = vecop_list_add,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1696,10 +1696,10 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_subs64,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1775,10 +1775,10 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_sub64,</div> -<div> .opt_opc = vecop_list_sub,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1806,10 +1806,10 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_mul64,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1835,10 +1835,10 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_muls64,</div> -<div> .opt_opc = vecop_list_mul,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1870,9 +1870,9 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_ssadd_vec,</div> -<div> .fno = gen_helper_gvec_ssadd64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1896,9 +1896,9 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> { .fniv = tcg_gen_sssub_vec,</div> -<div> .fno = gen_helper_gvec_sssub64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1940,9 +1940,9 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_usadd_vec,</div> -<div> .fno = gen_helper_gvec_usadd64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 }</div> -<div>+ .vece = MO_UQ }</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -1984,9 +1984,9 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_ussub_vec,</div> -<div> .fno = gen_helper_gvec_ussub64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 }</div> -<div>+ .vece = MO_UQ }</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2012,9 +2012,9 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_smin_vec,</div> -<div> .fno = gen_helper_gvec_smin64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 }</div> -<div>+ .vece = MO_UQ }</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2040,9 +2040,9 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_umin_vec,</div> -<div> .fno = gen_helper_gvec_umin64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 }</div> -<div>+ .vece = MO_UQ }</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2068,9 +2068,9 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_smax_vec,</div> -<div> .fno = gen_helper_gvec_smax64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 }</div> -<div>+ .vece = MO_UQ }</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2096,9 +2096,9 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fniv = tcg_gen_umax_vec,</div> -<div> .fno = gen_helper_gvec_umax64,</div> -<div> .opt_opc = vecop_list,</div> -<div>- .vece = MO_64 }</div> -<div>+ .vece = MO_UQ }</div> -<div> };</div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2171,10 +2171,10 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_neg64,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2234,10 +2234,10 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_abs64,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2382,7 +2382,7 @@ static const GVecGen2s gop_ands = {</div> -<div> .fniv = tcg_gen_and_vec,</div> -<div> .fno = gen_helper_gvec_ands,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64</div> -<div>+ .vece = MO_UQ</div> -<div> };</div> -<div> </div> -<div> void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div>@@ -2407,7 +2407,7 @@ static const GVecGen2s gop_xors = {</div> -<div> .fniv = tcg_gen_xor_vec,</div> -<div> .fno = gen_helper_gvec_xors,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64</div> -<div>+ .vece = MO_UQ</div> -<div> };</div> -<div> </div> -<div> void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div>@@ -2432,7 +2432,7 @@ static const GVecGen2s gop_ors = {</div> -<div> .fniv = tcg_gen_or_vec,</div> -<div> .fno = gen_helper_gvec_ors,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64</div> -<div>+ .vece = MO_UQ</div> -<div> };</div> -<div> </div> -<div> void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div>@@ -2491,10 +2491,10 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_shl64i,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_debug_assert(shift >= 0 && shift < (8 << vece));</div> -<div> if (shift == 0) {</div> -<div> tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);</div> -<div>@@ -2542,10 +2542,10 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_shr64i,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_debug_assert(shift >= 0 && shift < (8 << vece));</div> -<div> if (shift == 0) {</div> -<div> tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);</div> -<div>@@ -2607,10 +2607,10 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_sar64i,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_debug_assert(shift >= 0 && shift < (8 << vece));</div> -<div> if (shift == 0) {</div> -<div> tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);</div> -<div>@@ -2660,7 +2660,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div> -<div> check_overlap_2(dofs, aofs, maxsz);</div> -<div> </div> -<div> /* If the backend has a scalar expansion, great. */</div> -<div>- type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64);</div> -<div>+ type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_UQ);</div> -<div> if (type) {</div> -<div> const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);</div> -<div> switch (type) {</div> -<div>@@ -2692,15 +2692,15 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div> -<div> }</div> -<div> </div> -<div> /* If the backend supports variable vector shifts, also cool. */</div> -<div>- type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64);</div> -<div>+ type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_UQ);</div> -<div> if (type) {</div> -<div> const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);</div> -<div> TCGv_vec v_shift = tcg_temp_new_vec(type);</div> -<div> </div> -<div>- if (vece == MO_64) {</div> -<div>+ if (vece == MO_UQ) {</div> -<div> TCGv_i64 sh64 = tcg_temp_new_i64();</div> -<div> tcg_gen_extu_i32_i64(sh64, shift);</div> -<div>- tcg_gen_dup_i64_vec(MO_64, v_shift, sh64);</div> -<div>+ tcg_gen_dup_i64_vec(MO_UQ, v_shift, sh64);</div> -<div> tcg_temp_free_i64(sh64);</div> -<div> } else {</div> -<div> tcg_gen_dup_i32_vec(vece, v_shift, shift);</div> -<div>@@ -2738,7 +2738,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div> -<div> /* Otherwise fall back to integral... */</div> -<div> if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div> -<div> expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4);</div> -<div>- } else if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div> -<div>+ } else if (vece == MO_UQ && check_size_impl(oprsz, 8)) {</div> -<div> TCGv_i64 sh64 = tcg_temp_new_i64();</div> -<div> tcg_gen_extu_i32_i64(sh64, shift);</div> -<div> expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8);</div> -<div>@@ -2785,7 +2785,7 @@ void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .v_list = { INDEX_op_shlv_vec, 0 },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);</div> -<div> }</div> -<div> </div> -<div>@@ -2807,7 +2807,7 @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .v_list = { INDEX_op_shrv_vec, 0 },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);</div> -<div> }</div> -<div> </div> -<div>@@ -2829,7 +2829,7 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .v_list = { INDEX_op_sarv_vec, 0 },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);</div> -<div> }</div> -<div> </div> -<div>@@ -2895,10 +2895,10 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_shl64v,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -2958,10 +2958,10 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_shr64v,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -3021,10 +3021,10 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div> -<div> .fno = gen_helper_gvec_sar64v,</div> -<div> .opt_opc = vecop_list,</div> -<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div> -<div>- .vece = MO_64 },</div> -<div>+ .vece = MO_UQ },</div> -<div> };</div> -<div> </div> -<div>- tcg_debug_assert(vece <= MO_64);</div> -<div>+ tcg_debug_assert(vece <= MO_UQ);</div> -<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div> -<div> }</div> -<div> </div> -<div>@@ -3140,7 +3140,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div> -<div> */</div> -<div> hold_list = tcg_swap_vecop_list(cmp_list);</div> -<div> type = choose_vector_type(cmp_list, vece, oprsz,</div> -<div>- TCG_TARGET_REG_BITS == 64 && vece == MO_64);</div> -<div>+ TCG_TARGET_REG_BITS == 64 && vece == MO_UQ);</div> -<div> switch (type) {</div> -<div> case TCG_TYPE_V256:</div> -<div> /* Recall that ARM SVE allows vector sizes that are not a</div> -<div>@@ -3166,7 +3166,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div> -<div> break;</div> -<div> </div> -<div> case 0:</div> -<div>- if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div> -<div>+ if (vece == MO_UQ && check_size_impl(oprsz, 8)) {</div> -<div> expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);</div> -<div> } else if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div> -<div> expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);</div> -<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div> -<div>index ff723ab..e8aea38 100644</div> -<div>--- a/tcg/tcg-op-vec.c</div> -<div>+++ b/tcg/tcg-op-vec.c</div> -<div>@@ -216,7 +216,7 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_UL)</div> -<div>+#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_UQ : MO_UL)</div> -<div> </div> -<div> static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)</div> -<div> {</div> -<div>@@ -255,10 +255,10 @@ void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)</div> -<div> if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {</div> -<div> do_dupi_vec(r, MO_UL, a);</div> -<div> } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {</div> -<div>- do_dupi_vec(r, MO_64, a);</div> -<div>+ do_dupi_vec(r, MO_UQ, a);</div> -<div> } else {</div> -<div> TCGv_i64 c = tcg_const_i64(a);</div> -<div>- tcg_gen_dup_i64_vec(MO_64, r, c);</div> -<div>+ tcg_gen_dup_i64_vec(MO_UQ, r, c);</div> -<div> tcg_temp_free_i64(c);</div> -<div> }</div> -<div> }</div> -<div>@@ -292,10 +292,10 @@ void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)</div> -<div> if (TCG_TARGET_REG_BITS == 64) {</div> -<div> TCGArg ai = tcgv_i64_arg(a);</div> -<div> vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);</div> -<div>- } else if (vece == MO_64) {</div> -<div>+ } else if (vece == MO_UQ) {</div> -<div> TCGArg al = tcgv_i32_arg(TCGV_LOW(a));</div> -<div> TCGArg ah = tcgv_i32_arg(TCGV_HIGH(a));</div> -<div>- vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah);</div> -<div>+ vec_gen_3(INDEX_op_dup2_vec, type, MO_UQ, ri, al, ah);</div> -<div> } else {</div> -<div> TCGArg ai = tcgv_i32_arg(TCGV_LOW(a));</div> -<div> vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);</div> -<div>@@ -709,10 +709,10 @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,</div> -<div> } else {</div> -<div> TCGv_vec vec_s = tcg_temp_new_vec(type);</div> -<div> </div> -<div>- if (vece == MO_64) {</div> -<div>+ if (vece == MO_UQ) {</div> -<div> TCGv_i64 s64 = tcg_temp_new_i64();</div> -<div> tcg_gen_extu_i32_i64(s64, s);</div> -<div>- tcg_gen_dup_i64_vec(MO_64, vec_s, s64);</div> -<div>+ tcg_gen_dup_i64_vec(MO_UQ, vec_s, s64);</div> -<div> tcg_temp_free_i64(s64);</div> -<div> } else {</div> -<div> tcg_gen_dup_i32_vec(vece, vec_s, s);</div> -<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div> -<div>index 447683d..a9f3e13 100644</div> -<div>--- a/tcg/tcg-op.c</div> -<div>+++ b/tcg/tcg-op.c</div> -<div>@@ -2730,7 +2730,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div> -<div> op &= ~MO_SIGN;</div> -<div> }</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> if (!is64) {</div> -<div> tcg_abort();</div> -<div> }</div> -<div>@@ -2862,7 +2862,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> {</div> -<div> TCGMemOp orig_memop;</div> -<div> </div> -<div>- if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {</div> -<div>+ if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_UQ) {</div> -<div> tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);</div> -<div> if (memop & MO_SIGN) {</div> -<div> tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);</div> -<div>@@ -2881,7 +2881,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {</div> -<div> memop &= ~MO_BSWAP;</div> -<div> /* The bswap primitive requires zero-extended input. */</div> -<div>- if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) {</div> -<div>+ if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_UQ) {</div> -<div> memop &= ~MO_SIGN;</div> -<div> }</div> -<div> }</div> -<div>@@ -2902,7 +2902,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> tcg_gen_ext32s_i64(val, val);</div> -<div> }</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_bswap64_i64(val, val);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -2915,7 +2915,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> {</div> -<div> TCGv_i64 swap = NULL;</div> -<div> </div> -<div>- if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {</div> -<div>+ if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_UQ) {</div> -<div> tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);</div> -<div> return;</div> -<div> }</div> -<div>@@ -2936,7 +2936,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> tcg_gen_ext32u_i64(swap, val);</div> -<div> tcg_gen_bswap32_i64(swap, swap);</div> -<div> break;</div> -<div>- case MO_64:</div> -<div>+ case MO_UQ:</div> -<div> tcg_gen_bswap64_i64(swap, val);</div> -<div> break;</div> -<div> default:</div> -<div>@@ -3029,8 +3029,8 @@ static void * const table_cmpxchg[16] = {</div> -<div> [MO_UW | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div> -<div> [MO_UL | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div> -<div> [MO_UL | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div> -<div>- WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div> -<div>- WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be)</div> -<div>+ WITH_ATOMIC64([MO_UQ | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div> -<div>+ WITH_ATOMIC64([MO_UQ | MO_BE] = gen_helper_atomic_cmpxchgq_be)</div> -<div> };</div> -<div> </div> -<div> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,</div> -<div>@@ -3099,7 +3099,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,</div> -<div> tcg_gen_mov_i64(retv, t1);</div> -<div> }</div> -<div> tcg_temp_free_i64(t1);</div> -<div>- } else if ((memop & MO_SIZE) == MO_64) {</div> -<div>+ } else if ((memop & MO_SIZE) == MO_UQ) {</div> -<div> #ifdef CONFIG_ATOMIC64</div> -<div> gen_atomic_cx_i64 gen;</div> -<div> </div> -<div>@@ -3207,7 +3207,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div> -<div> {</div> -<div> memop = tcg_canonicalize_memop(memop, 1, 0);</div> -<div> </div> -<div>- if ((memop & MO_SIZE) == MO_64) {</div> -<div>+ if ((memop & MO_SIZE) == MO_UQ) {</div> -<div> #ifdef CONFIG_ATOMIC64</div> -<div> gen_atomic_op_i64 gen;</div> -<div> </div> -<div>@@ -3253,8 +3253,8 @@ static void * const table_##NAME[16] = { \</div> -<div> [MO_UW | MO_BE] = gen_helper_atomic_##NAME##w_be, \</div> -<div> [MO_UL | MO_LE] = gen_helper_atomic_##NAME##l_le, \</div> -<div> [MO_UL | MO_BE] = gen_helper_atomic_##NAME##l_be, \</div> -<div>- WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \</div> -<div>- WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \</div> -<div>+ WITH_ATOMIC64([MO_UQ | MO_LE] = gen_helper_atomic_##NAME##q_le) \</div> -<div>+ WITH_ATOMIC64([MO_UQ | MO_BE] = gen_helper_atomic_##NAME##q_be) \</div> -<div> }; \</div> -<div> void tcg_gen_atomic_##NAME##_i32 \</div> -<div> (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \</div> -<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div> -<div>index 4b6ee89..63e9897 100644</div> -<div>--- a/tcg/tcg.h</div> -<div>+++ b/tcg/tcg.h</div> -<div>@@ -371,28 +371,29 @@ typedef enum TCGMemOp {</div> -<div> MO_UB = MO_8,</div> -<div> MO_UW = MO_16,</div> -<div> MO_UL = MO_32,</div> -<div>+ MO_UQ = MO_64,</div> -<div> MO_SB = MO_SIGN | MO_8,</div> -<div> MO_SW = MO_SIGN | MO_16,</div> -<div> MO_SL = MO_SIGN | MO_32,</div> -<div>- MO_Q = MO_64,</div> -<div>+ MO_SQ = MO_SIGN | MO_64,</div> -<div> </div> -<div> MO_LEUW = MO_LE | MO_UW,</div> -<div> MO_LEUL = MO_LE | MO_UL,</div> -<div> MO_LESW = MO_LE | MO_SW,</div> -<div> MO_LESL = MO_LE | MO_SL,</div> -<div>- MO_LEQ = MO_LE | MO_Q,</div> -<div>+ MO_LEQ = MO_LE | MO_UQ,</div> -<div> </div> -<div> MO_BEUW = MO_BE | MO_UW,</div> -<div> MO_BEUL = MO_BE | MO_UL,</div> -<div> MO_BESW = MO_BE | MO_SW,</div> -<div> MO_BESL = MO_BE | MO_SL,</div> -<div>- MO_BEQ = MO_BE | MO_Q,</div> -<div>+ MO_BEQ = MO_BE | MO_UQ,</div> -<div> </div> -<div> MO_TEUW = MO_TE | MO_UW,</div> -<div> MO_TEUL = MO_TE | MO_UL,</div> -<div> MO_TESW = MO_TE | MO_SW,</div> -<div> MO_TESL = MO_TE | MO_SL,</div> -<div>- MO_TEQ = MO_TE | MO_Q,</div> -<div>+ MO_TEQ = MO_TE | MO_UQ,</div> -<div> </div> -<div> MO_SSIZE = MO_SIZE | MO_SIGN,</div> -<div> } TCGMemOp;</div> -<div>-- </div> -<div>1.8.3.1</div> -<div><br> -<br> -</div> -<p><br> -</p> -</body> -</html> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index e54d0ae..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/html; charset="iso-8859-1" -Content-Transfer-Encoding: quoted-printable diff --git a/a/content_digest b/N1/content_digest index 5de88c9..db42956 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,34 +1,34 @@ "ref\0e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net\0" "From\0<tony.nguyen@bt.com>\0" - "Subject\0[Qemu-riscv] [Qemu-devel] [PATCH v2 04/20] tcg: Replace MO_64 with MO_UQ alias\0" + "Subject\0[Qemu-devel] [PATCH v2 04/20] tcg: Replace MO_64 with MO_UQ alias\0" "Date\0Mon, 22 Jul 2019 15:42:43 +0000\0" "To\0<qemu-devel@nongnu.org>\0" - "Cc\0<peter.maydell@linaro.org>" - <walling@linux.ibm.com> - <david@redhat.com> - <palmer@sifive.com> - <mark.cave-ayland@ilande.co.uk> - <Alistair.Francis@wdc.com> - <arikalo@wavecomp.com> - <mst@redhat.com> - <pasic@linux.ibm.com> - <borntraeger@de.ibm.com> - <rth@twiddle.net> - <atar4qemu@gmail.com> - <ehabkost@redhat.com> - <sw@weilnetz.de> - <alex.williamson@redhat.com> - <qemu-arm@nongnu.org> - <david@gibson.dropbear.id.au> - <qemu-riscv@nongnu.org> - <cohuck@redhat.com> - <claudio.fontana@huawei.com> - <qemu-s390x@nongnu.org> - <qemu-ppc@nongnu.org> - <amarkovic@wavecomp.com> - <pbonzini@redhat.com> - " <aurelien@aurel32.net>\0" - "\01:1\0" + "Cc\0peter.maydell@linaro.org" + walling@linux.ibm.com + mst@redhat.com + palmer@sifive.com + mark.cave-ayland@ilande.co.uk + Alistair.Francis@wdc.com + arikalo@wavecomp.com + david@redhat.com + pasic@linux.ibm.com + borntraeger@de.ibm.com + rth@twiddle.net + atar4qemu@gmail.com + ehabkost@redhat.com + sw@weilnetz.de + qemu-s390x@nongnu.org + qemu-arm@nongnu.org + david@gibson.dropbear.id.au + qemu-riscv@nongnu.org + cohuck@redhat.com + claudio.fontana@huawei.com + alex.williamson@redhat.com + qemu-ppc@nongnu.org + amarkovic@wavecomp.com + pbonzini@redhat.com + " aurelien@aurel32.net\0" + "\00:1\0" "b\0" "Preparation for splitting MO_64 out from TCGMemOp into new accelerator\n" "independent MemOp.\n" @@ -3312,3307 +3312,5 @@ " } TCGMemOp;\n" "--\n" 1.8.3.1 - "\01:2\0" - "b\0" - "<html>\r\n" - "<head>\r\n" - "<meta http-equiv=\"Content-Type\" content=\"text/html; charset=iso-8859-1\">\r\n" - "<style type=\"text/css\" style=\"display:none\"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style>\r\n" - "</head>\r\n" - "<body dir=\"ltr\" style=\"font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;\">\r\n" - "<p></p>\r\n" - "<div><span style=\"font-size: 12pt;\">Preparation for splitting MO_64 out from TCGMemOp into new accelerator</span><br>\r\n" - "</div>\r\n" - "<div>independent MemOp.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>As MO_64 will be a value of MemOp, existing TCGMemOp comparisons and</div>\r\n" - "<div>coercions will trigger -Wenum-compare and -Wenum-conversion.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div>\r\n" - "<div>---</div>\r\n" - "<div> target/arm/sve_helper.c | 2 +-</div>\r\n" - "<div> target/arm/translate-a64.c | 270 ++++++++++++++++++------------------</div>\r\n" - "<div> target/arm/translate-sve.c | 18 +--</div>\r\n" - "<div> target/arm/translate-vfp.inc.c | 4 +-</div>\r\n" - "<div> target/arm/translate.c | 30 ++--</div>\r\n" - "<div> target/i386/translate.c | 122 ++++++++--------</div>\r\n" - "<div> target/mips/translate.c | 2 +-</div>\r\n" - "<div> target/ppc/translate.c | 28 ++--</div>\r\n" - "<div> target/ppc/translate/fp-impl.inc.c | 4 +-</div>\r\n" - "<div> target/ppc/translate/vmx-impl.inc.c | 34 ++---</div>\r\n" - "<div> target/ppc/translate/vsx-impl.inc.c | 18 +--</div>\r\n" - "<div> target/s390x/translate.c | 4 +-</div>\r\n" - "<div> target/s390x/translate_vx.inc.c | 6 +-</div>\r\n" - "<div> target/s390x/vec.h | 4 +-</div>\r\n" - "<div> target/sparc/translate.c | 4 +-</div>\r\n" - "<div> tcg/aarch64/tcg-target.inc.c | 20 +--</div>\r\n" - "<div> tcg/arm/tcg-target.inc.c | 12 +-</div>\r\n" - "<div> tcg/i386/tcg-target.inc.c | 42 +++---</div>\r\n" - "<div> tcg/mips/tcg-target.inc.c | 12 +-</div>\r\n" - "<div> tcg/ppc/tcg-target.inc.c | 18 +--</div>\r\n" - "<div> tcg/riscv/tcg-target.inc.c | 6 +-</div>\r\n" - "<div> tcg/s390/tcg-target.inc.c | 10 +-</div>\r\n" - "<div> tcg/sparc/tcg-target.inc.c | 8 +-</div>\r\n" - "<div> tcg/tcg-op-gvec.c | 132 +++++++++---------</div>\r\n" - "<div> tcg/tcg-op-vec.c | 14 +-</div>\r\n" - "<div> tcg/tcg-op.c | 24 ++--</div>\r\n" - "<div> tcg/tcg.h | 9 +-</div>\r\n" - "<div> 27 files changed, 430 insertions(+), 427 deletions(-)</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c</div>\r\n" - "<div>index fa705c4..1cfd746 100644</div>\r\n" - "<div>--- a/target/arm/sve_helper.c</div>\r\n" - "<div>+++ b/target/arm/sve_helper.c</div>\r\n" - "<div>@@ -5165,7 +5165,7 @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,</div>\r\n" - "<div> target_ulong addr;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Skip to the first true predicate. */</div>\r\n" - "<div>- reg_off = find_next_active(vg, 0, reg_max, MO_64);</div>\r\n" - "<div>+ reg_off = find_next_active(vg, 0, reg_max, MO_UQ);</div>\r\n" - "<div> if (likely(reg_off < reg_max)) {</div>\r\n" - "<div> /* Perform one normal read, which will fault or not. */</div>\r\n" - "<div> set_helper_retaddr(ra);</div>\r\n" - "<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div>\r\n" - "<div>index 0b92e6d..3f9d103 100644</div>\r\n" - "<div>--- a/target/arm/translate-a64.c</div>\r\n" - "<div>+++ b/target/arm/translate-a64.c</div>\r\n" - "<div>@@ -463,7 +463,7 @@ static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)</div>\r\n" - "<div> /* Offset of the high half of the 128 bit vector Qn */</div>\r\n" - "<div> static inline int fp_reg_hi_offset(DisasContext *s, int regno)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return vec_reg_offset(s, regno, 1, MO_64);</div>\r\n" - "<div>+ return vec_reg_offset(s, regno, 1, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Convenience accessors for reading and writing single and double</div>\r\n" - "<div>@@ -476,7 +476,7 @@ static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 v = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));</div>\r\n" - "<div>+ tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_UQ));</div>\r\n" - "<div> return v;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -501,7 +501,7 @@ static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)</div>\r\n" - "<div> */</div>\r\n" - "<div> static void clear_vec_high(DisasContext *s, bool is_q, int rd)</div>\r\n" - "<div> {</div>\r\n" - "<div>- unsigned ofs = fp_reg_offset(s, rd, MO_64);</div>\r\n" - "<div>+ unsigned ofs = fp_reg_offset(s, rd, MO_UQ);</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div> </div>\r\n" - "<div> if (!is_q) {</div>\r\n" - "<div>@@ -516,7 +516,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)</div>\r\n" - "<div> </div>\r\n" - "<div> void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)</div>\r\n" - "<div> {</div>\r\n" - "<div>- unsigned ofs = fp_reg_offset(s, reg, MO_64);</div>\r\n" - "<div>+ unsigned ofs = fp_reg_offset(s, reg, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_st_i64(v, cpu_env, ofs);</div>\r\n" - "<div> clear_vec_high(s, false, reg);</div>\r\n" - "<div>@@ -918,7 +918,7 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)</div>\r\n" - "<div> {</div>\r\n" - "<div> /* This writes the bottom N bits of a 128 bit wide vector to memory */</div>\r\n" - "<div> TCGv_i64 tmp = tcg_temp_new_i64();</div>\r\n" - "<div>- tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64));</div>\r\n" - "<div>+ tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_UQ));</div>\r\n" - "<div> if (size < 4) {</div>\r\n" - "<div> tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s),</div>\r\n" - "<div> s->be_data + size);</div>\r\n" - "<div>@@ -928,10 +928,10 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);</div>\r\n" - "<div> tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),</div>\r\n" - "<div>- s->be_data | MO_Q);</div>\r\n" - "<div>+ s->be_data | MO_UQ);</div>\r\n" - "<div> tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx));</div>\r\n" - "<div> tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),</div>\r\n" - "<div>- s->be_data | MO_Q);</div>\r\n" - "<div>+ s->be_data | MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_hiaddr);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -960,13 +960,13 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);</div>\r\n" - "<div> tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),</div>\r\n" - "<div>- s->be_data | MO_Q);</div>\r\n" - "<div>+ s->be_data | MO_UQ);</div>\r\n" - "<div> tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),</div>\r\n" - "<div>- s->be_data | MO_Q);</div>\r\n" - "<div>+ s->be_data | MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_hiaddr);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));</div>\r\n" - "<div>+ tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_UQ));</div>\r\n" - "<div> tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tmplo);</div>\r\n" - "<div>@@ -1011,8 +1011,8 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> case MO_SL:</div>\r\n" - "<div> tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>- case MO_64|MO_SIGN:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div>+ case MO_SQ:</div>\r\n" - "<div> tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -1061,7 +1061,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_st_i64(tcg_src, cpu_env, vect_off);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -2207,7 +2207,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div>\r\n" - "<div> g_assert(size >= 2);</div>\r\n" - "<div> if (size == 2) {</div>\r\n" - "<div> /* The pair must be single-copy atomic for the doubleword. */</div>\r\n" - "<div>- memop |= MO_64 | MO_ALIGN;</div>\r\n" - "<div>+ memop |= MO_UQ | MO_ALIGN;</div>\r\n" - "<div> tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);</div>\r\n" - "<div> if (s->be_data == MO_LE) {</div>\r\n" - "<div> tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32);</div>\r\n" - "<div>@@ -2219,7 +2219,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div>\r\n" - "<div> } else {</div>\r\n" - "<div> /* The pair must be single-copy atomic for *each* doubleword, not</div>\r\n" - "<div> the entire quadword, however it must be quadword aligned. */</div>\r\n" - "<div>- memop |= MO_64;</div>\r\n" - "<div>+ memop |= MO_UQ;</div>\r\n" - "<div> tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx,</div>\r\n" - "<div> memop | MO_ALIGN_16);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2271,7 +2271,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,</div>\r\n" - "<div> tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,</div>\r\n" - "<div> cpu_exclusive_val, tmp,</div>\r\n" - "<div> get_mem_index(s),</div>\r\n" - "<div>- MO_64 | MO_ALIGN | s->be_data);</div>\r\n" - "<div>+ MO_UQ | MO_ALIGN | s->be_data);</div>\r\n" - "<div> tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);</div>\r\n" - "<div> } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {</div>\r\n" - "<div> if (!HAVE_CMPXCHG128) {</div>\r\n" - "<div>@@ -2355,7 +2355,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx,</div>\r\n" - "<div>- MO_64 | MO_ALIGN | s->be_data);</div>\r\n" - "<div>+ MO_UQ | MO_ALIGN | s->be_data);</div>\r\n" - "<div> tcg_temp_free_i64(val);</div>\r\n" - "<div> </div>\r\n" - "<div> if (s->be_data == MO_LE) {</div>\r\n" - "<div>@@ -2389,9 +2389,9 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,</div>\r\n" - "<div> </div>\r\n" - "<div> /* Load the two words, in memory order. */</div>\r\n" - "<div> tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,</div>\r\n" - "<div>- MO_64 | MO_ALIGN_16 | s->be_data);</div>\r\n" - "<div>+ MO_UQ | MO_ALIGN_16 | s->be_data);</div>\r\n" - "<div> tcg_gen_addi_i64(a2, clean_addr, 8);</div>\r\n" - "<div>- tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data);</div>\r\n" - "<div>+ tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_UQ | s->be_data);</div>\r\n" - "<div> </div>\r\n" - "<div> /* Compare the two words, also in memory order. */</div>\r\n" - "<div> tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1);</div>\r\n" - "<div>@@ -2401,8 +2401,8 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,</div>\r\n" - "<div> /* If compare equal, write back new data, else write back old data. */</div>\r\n" - "<div> tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1);</div>\r\n" - "<div> tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2);</div>\r\n" - "<div>- tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data);</div>\r\n" - "<div>- tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data);</div>\r\n" - "<div>+ tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_UQ | s->be_data);</div>\r\n" - "<div>+ tcg_gen_qemu_st_i64(c2, a2, memidx, MO_UQ | s->be_data);</div>\r\n" - "<div> tcg_temp_free_i64(a2);</div>\r\n" - "<div> tcg_temp_free_i64(c1);</div>\r\n" - "<div> tcg_temp_free_i64(c2);</div>\r\n" - "<div>@@ -5271,7 +5271,7 @@ static void handle_fp_compare(DisasContext *s, int size,</div>\r\n" - "<div> TCGv_i64 tcg_flags = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_ptr fpst = get_fpstatus_ptr(size == MO_UW);</div>\r\n" - "<div> </div>\r\n" - "<div>- if (size == MO_64) {</div>\r\n" - "<div>+ if (size == MO_UQ) {</div>\r\n" - "<div> TCGv_i64 tcg_vn, tcg_vm;</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_vn = read_fp_dreg(s, rn);</div>\r\n" - "<div>@@ -5357,7 +5357,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div>- size = MO_64;</div>\r\n" - "<div>+ size = MO_UQ;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div>@@ -5408,7 +5408,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div>- size = MO_64;</div>\r\n" - "<div>+ size = MO_UQ;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div>@@ -5474,7 +5474,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> sz = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div>- sz = MO_64;</div>\r\n" - "<div>+ sz = MO_UQ;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div> sz = MO_UW;</div>\r\n" - "<div>@@ -6279,7 +6279,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> sz = MO_UL;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div>- sz = MO_64;</div>\r\n" - "<div>+ sz = MO_UQ;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 3:</div>\r\n" - "<div> sz = MO_UW;</div>\r\n" - "<div>@@ -6585,7 +6585,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 1:</div>\r\n" - "<div> /* 64 bit */</div>\r\n" - "<div>- tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64));</div>\r\n" - "<div>+ tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_UQ));</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 2:</div>\r\n" - "<div> /* 64 bits from top half */</div>\r\n" - "<div>@@ -6819,9 +6819,9 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> * extracting 64 bits from a 64:64 concatenation.</div>\r\n" - "<div> */</div>\r\n" - "<div> if (!is_q) {</div>\r\n" - "<div>- read_vec_element(s, tcg_resl, rn, 0, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_resl, rn, 0, MO_UQ);</div>\r\n" - "<div> if (pos != 0) {</div>\r\n" - "<div>- read_vec_element(s, tcg_resh, rm, 0, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_resh, rm, 0, MO_UQ);</div>\r\n" - "<div> do_ext64(s, tcg_resh, tcg_resl, pos);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_movi_i64(tcg_resh, 0);</div>\r\n" - "<div>@@ -6839,22 +6839,22 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> pos -= 64;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_UQ);</div>\r\n" - "<div> elt++;</div>\r\n" - "<div>- read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_UQ);</div>\r\n" - "<div> elt++;</div>\r\n" - "<div> if (pos != 0) {</div>\r\n" - "<div> do_ext64(s, tcg_resh, tcg_resl, pos);</div>\r\n" - "<div> tcg_hh = tcg_temp_new_i64();</div>\r\n" - "<div>- read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_UQ);</div>\r\n" - "<div> do_ext64(s, tcg_hh, tcg_resh, pos);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_hh);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_resl, rd, 0, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_resl);</div>\r\n" - "<div>- write_vec_element(s, tcg_resh, rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_resh);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -6895,12 +6895,12 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_resh = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> if (is_tblx) {</div>\r\n" - "<div>- read_vec_element(s, tcg_resl, rd, 0, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_movi_i64(tcg_resl, 0);</div>\r\n" - "<div> }</div>\r\n" - "<div> if (is_tblx && is_q) {</div>\r\n" - "<div>- read_vec_element(s, tcg_resh, rd, 1, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_movi_i64(tcg_resh, 0);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6908,11 +6908,11 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_idx = tcg_temp_new_i64();</div>\r\n" - "<div> tcg_regno = tcg_const_i32(rn);</div>\r\n" - "<div> tcg_numregs = tcg_const_i32(len + 1);</div>\r\n" - "<div>- read_vec_element(s, tcg_idx, rm, 0, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_idx, rm, 0, MO_UQ);</div>\r\n" - "<div> gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,</div>\r\n" - "<div> tcg_regno, tcg_numregs);</div>\r\n" - "<div> if (is_q) {</div>\r\n" - "<div>- read_vec_element(s, tcg_idx, rm, 1, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_idx, rm, 1, MO_UQ);</div>\r\n" - "<div> gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,</div>\r\n" - "<div> tcg_regno, tcg_numregs);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -6920,9 +6920,9 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_temp_free_i32(tcg_regno);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_numregs);</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_resl, rd, 0, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_resl);</div>\r\n" - "<div>- write_vec_element(s, tcg_resh, rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_resh);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -7009,9 +7009,9 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_res);</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_resl, rd, 0, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_resl, rd, 0, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_resl);</div>\r\n" - "<div>- write_vec_element(s, tcg_resh, rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_resh, rd, 1, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_resh);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -7625,9 +7625,9 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> } else {</div>\r\n" - "<div> /* ORR or BIC, with BIC negation to AND handled above. */</div>\r\n" - "<div> if (is_neg) {</div>\r\n" - "<div>- gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64);</div>\r\n" - "<div>+ gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_UQ);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64);</div>\r\n" - "<div>+ gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -7702,7 +7702,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> size = MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- size = extract32(size, 0, 1) ? MO_64 : MO_UL;</div>\r\n" - "<div>+ size = extract32(size, 0, 1) ? MO_UQ : MO_UL;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> if (!fp_access_check(s)) {</div>\r\n" - "<div>@@ -7716,13 +7716,13 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- if (size == MO_64) {</div>\r\n" - "<div>+ if (size == MO_UQ) {</div>\r\n" - "<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, 0, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rn, 1, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, 0, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rn, 1, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0x3b: /* ADDP */</div>\r\n" - "<div>@@ -8085,9 +8085,9 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> if (!is_q) {</div>\r\n" - "<div>- write_vec_element(s, tcg_final, rd, 0, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_final, rd, 0, MO_UQ);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- write_vec_element(s, tcg_final, rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_final, rd, 1, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> if (round) {</div>\r\n" - "<div>@@ -8155,9 +8155,9 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div>\r\n" - "<div> for (pass = 0; pass < maxpass; pass++) {</div>\r\n" - "<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> genfn(tcg_op, cpu_env, tcg_op, tcg_shift);</div>\r\n" - "<div>- write_vec_element(s, tcg_op, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_op, rd, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_op);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -8228,11 +8228,11 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div>\r\n" - "<div> TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);</div>\r\n" - "<div> int pass;</div>\r\n" - "<div> </div>\r\n" - "<div>- if (fracbits || size == MO_64) {</div>\r\n" - "<div>+ if (fracbits || size == MO_UQ) {</div>\r\n" - "<div> tcg_shift = tcg_const_i32(fracbits);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- if (size == MO_64) {</div>\r\n" - "<div>+ if (size == MO_UQ) {</div>\r\n" - "<div> TCGv_i64 tcg_int64 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_double = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -8249,7 +8249,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div>\r\n" - "<div> if (elements == 1) {</div>\r\n" - "<div> write_fp_dreg(s, rd, tcg_double);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- write_vec_element(s, tcg_double, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_double, rd, pass, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -8331,7 +8331,7 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> int immhb = immh << 3 | immb;</div>\r\n" - "<div> </div>\r\n" - "<div> if (immh & 8) {</div>\r\n" - "<div>- size = MO_64;</div>\r\n" - "<div>+ size = MO_UQ;</div>\r\n" - "<div> if (!is_scalar && !is_q) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -8376,7 +8376,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> TCGv_i32 tcg_rmode, tcg_shift;</div>\r\n" - "<div> </div>\r\n" - "<div> if (immh & 0x8) {</div>\r\n" - "<div>- size = MO_64;</div>\r\n" - "<div>+ size = MO_UQ;</div>\r\n" - "<div> if (!is_scalar && !is_q) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -8408,19 +8408,19 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,</div>\r\n" - "<div> fracbits = (16 << size) - immhb;</div>\r\n" - "<div> tcg_shift = tcg_const_i32(fracbits);</div>\r\n" - "<div> </div>\r\n" - "<div>- if (size == MO_64) {</div>\r\n" - "<div>+ if (size == MO_UQ) {</div>\r\n" - "<div> int maxpass = is_scalar ? 1 : 2;</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < maxpass; pass++) {</div>\r\n" - "<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> if (is_u) {</div>\r\n" - "<div> gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_op, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_op, rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op);</div>\r\n" - "<div> }</div>\r\n" - "<div> clear_vec_high(s, is_q, rd);</div>\r\n" - "<div>@@ -8601,7 +8601,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_gen_neg_i64(tcg_res, tcg_res);</div>\r\n" - "<div> /* fall through */</div>\r\n" - "<div> case 0x9: /* SQDMLAL, SQDMLAL2 */</div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rd, 0, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rd, 0, MO_UQ);</div>\r\n" - "<div> gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,</div>\r\n" - "<div> tcg_res, tcg_op1);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -8751,8 +8751,8 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (fpopcode) {</div>\r\n" - "<div> case 0x39: /* FMLS */</div>\r\n" - "<div>@@ -8760,7 +8760,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div>\r\n" - "<div> gen_helper_vfp_negd(tcg_op1, tcg_op1);</div>\r\n" - "<div> /* fall through */</div>\r\n" - "<div> case 0x19: /* FMLA */</div>\r\n" - "<div>- read_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,</div>\r\n" - "<div> tcg_res, fpst);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -8820,7 +8820,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op1);</div>\r\n" - "<div>@@ -8905,7 +8905,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,</div>\r\n" - "<div> TCGv_i64 tcg_tmp = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);</div>\r\n" - "<div>- write_vec_element(s, tcg_tmp, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_tmp, rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_tmp);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> write_vec_element_i32(s, tcg_res, rd, pass, MO_UL);</div>\r\n" - "<div>@@ -9381,7 +9381,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div>\r\n" - "<div> bool is_scalar, bool is_u, bool is_q,</div>\r\n" - "<div> int size, int rn, int rd)</div>\r\n" - "<div> {</div>\r\n" - "<div>- bool is_double = (size == MO_64);</div>\r\n" - "<div>+ bool is_double = (size == MO_UQ);</div>\r\n" - "<div> TCGv_ptr fpst;</div>\r\n" - "<div> </div>\r\n" - "<div> if (!fp_access_check(s)) {</div>\r\n" - "<div>@@ -9419,13 +9419,13 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> if (swap) {</div>\r\n" - "<div> genfn(tcg_res, tcg_zero, tcg_op, fpst);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> genfn(tcg_res, tcg_op, tcg_zero, fpst);</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_zero);</div>\r\n" - "<div>@@ -9526,7 +9526,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div>\r\n" - "<div> int pass;</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0x3d: /* FRECPE */</div>\r\n" - "<div> gen_helper_recpe_f64(tcg_res, tcg_op, fpst);</div>\r\n" - "<div>@@ -9540,7 +9540,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,</div>\r\n" - "<div> default:</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op);</div>\r\n" - "<div>@@ -9615,7 +9615,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,</div>\r\n" - "<div> if (scalar) {</div>\r\n" - "<div> read_vec_element(s, tcg_op, rn, pass, size + 1);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i32();</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -9711,15 +9711,15 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div>\r\n" - "<div> int pass;</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div>\r\n" - "<div>- read_vec_element(s, tcg_rn, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_rd, rd, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_rn, rn, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_rd, rd, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> if (is_u) { /* USQADD */</div>\r\n" - "<div> gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);</div>\r\n" - "<div> } else { /* SUQADD */</div>\r\n" - "<div> gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_rd, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_rd, rd, pass, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_temp_free_i64(tcg_rd);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_rn);</div>\r\n" - "<div>@@ -9776,7 +9776,7 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,</div>\r\n" - "<div> </div>\r\n" - "<div> if (is_scalar) {</div>\r\n" - "<div> TCGv_i64 tcg_zero = tcg_const_i64(0);</div>\r\n" - "<div>- write_vec_element(s, tcg_zero, rd, 0, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_zero, rd, 0, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_zero);</div>\r\n" - "<div> }</div>\r\n" - "<div> write_vec_element_i32(s, tcg_rd, rd, pass, MO_UL);</div>\r\n" - "<div>@@ -10146,7 +10146,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,</div>\r\n" - "<div> * so if rd == rn we would overwrite parts of our input.</div>\r\n" - "<div> * So load everything right now and use shifts in the main loop.</div>\r\n" - "<div> */</div>\r\n" - "<div>- read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> for (i = 0; i < elements; i++) {</div>\r\n" - "<div> tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);</div>\r\n" - "<div>@@ -10183,7 +10183,7 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,</div>\r\n" - "<div> tcg_rn = tcg_temp_new_i64();</div>\r\n" - "<div> tcg_rd = tcg_temp_new_i64();</div>\r\n" - "<div> tcg_final = tcg_temp_new_i64();</div>\r\n" - "<div>- read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> if (round) {</div>\r\n" - "<div> uint64_t round_const = 1ULL << (shift - 1);</div>\r\n" - "<div>@@ -10201,9 +10201,9 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> if (!is_q) {</div>\r\n" - "<div>- write_vec_element(s, tcg_final, rd, 0, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_final, rd, 0, MO_UQ);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- write_vec_element(s, tcg_final, rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_final, rd, 1, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> if (round) {</div>\r\n" - "<div> tcg_temp_free_i64(tcg_round);</div>\r\n" - "<div>@@ -10335,8 +10335,8 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> if (accop != 0) {</div>\r\n" - "<div>- read_vec_element(s, tcg_res[0], rd, 0, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_res[1], rd, 1, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* size == 2 means two 32x32->64 operations; this is worth special</div>\r\n" - "<div>@@ -10522,8 +10522,8 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div>\r\n" - "<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[0]);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[1]);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -10546,7 +10546,7 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> };</div>\r\n" - "<div> NeonGenWidenFn *widenfn = widenfns[size][is_u];</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div>\r\n" - "<div> read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_UL);</div>\r\n" - "<div> widenfn(tcg_op2_wide, tcg_op2);</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op2);</div>\r\n" - "<div>@@ -10558,7 +10558,7 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -10589,8 +10589,8 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> };</div>\r\n" - "<div> NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -10621,12 +10621,12 @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, is_q, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, is_q, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, is_q, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, is_q, MO_UQ);</div>\r\n" - "<div> gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2);</div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, 0, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, 0, MO_UQ);</div>\r\n" - "<div> gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2);</div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, 1, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_op1);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op2);</div>\r\n" - "<div>@@ -10814,8 +10814,8 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> int passreg = (pass == 0) ? rn : rm;</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, passreg, 0, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, passreg, 1, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, passreg, 0, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, passreg, 1, MO_UQ);</div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div>@@ -10846,7 +10846,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -10971,7 +10971,7 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>- handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_UL,</div>\r\n" - "<div>+ handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_UQ : MO_UL,</div>\r\n" - "<div> rn, rm, rd);</div>\r\n" - "<div> return;</div>\r\n" - "<div> case 0x1b: /* FMULX */</div>\r\n" - "<div>@@ -11155,12 +11155,12 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op1);</div>\r\n" - "<div>@@ -11714,7 +11714,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,</div>\r\n" - "<div> tcg_temp_free_i32(tcg_op);</div>\r\n" - "<div> }</div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -11774,7 +11774,7 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -11803,8 +11803,8 @@ static void handle_rev(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_rd, rd, 0, MO_64);</div>\r\n" - "<div>- write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_rd, rd, 0, MO_UQ);</div>\r\n" - "<div>+ write_vec_element(s, tcg_rd_hi, rd, 1, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_rd_hi);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_rd);</div>\r\n" - "<div>@@ -11839,7 +11839,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);</div>\r\n" - "<div> tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);</div>\r\n" - "<div> if (accum) {</div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rd, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -11859,11 +11859,11 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_res[pass] = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> genfn(tcg_res[pass], tcg_op);</div>\r\n" - "<div> </div>\r\n" - "<div> if (accum) {</div>\r\n" - "<div>- read_vec_element(s, tcg_op, rd, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rd, pass, MO_UQ);</div>\r\n" - "<div> if (size == 0) {</div>\r\n" - "<div> gen_helper_neon_addl_u16(tcg_res[pass],</div>\r\n" - "<div> tcg_res[pass], tcg_op);</div>\r\n" - "<div>@@ -11879,7 +11879,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> tcg_res[1] = tcg_const_i64(0);</div>\r\n" - "<div> }</div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -11909,7 +11909,7 @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -12233,12 +12233,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> handle_2misc_64(s, opcode, u, tcg_res, tcg_op,</div>\r\n" - "<div> tcg_rmode, tcg_fpstatus);</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_res);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op);</div>\r\n" - "<div>@@ -12856,7 +12856,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> is_fp16 = true;</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_UL: /* single precision */</div>\r\n" - "<div>- case MO_64: /* double precision */</div>\r\n" - "<div>+ case MO_UQ: /* double precision */</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div>@@ -12875,7 +12875,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> }</div>\r\n" - "<div> is_fp16 = true;</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div>@@ -12886,7 +12886,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> default: /* integer */</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -12906,7 +12906,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> index = h << 1 | l;</div>\r\n" - "<div> rm |= m << 4;</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (l || !is_q) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -12946,7 +12946,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> vec_full_reg_offset(s, rn),</div>\r\n" - "<div> vec_full_reg_offset(s, rm), fpst,</div>\r\n" - "<div> is_q ? 16 : 8, vec_full_reg_size(s), data,</div>\r\n" - "<div>- size == MO_64</div>\r\n" - "<div>+ size == MO_UQ</div>\r\n" - "<div> ? gen_helper_gvec_fcmlas_idx</div>\r\n" - "<div> : gen_helper_gvec_fcmlah_idx);</div>\r\n" - "<div> tcg_temp_free_ptr(fpst);</div>\r\n" - "<div>@@ -12976,13 +12976,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> assert(is_fp && is_q && !is_long);</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_idx, rm, index, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_idx, rm, index, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {</div>\r\n" - "<div> TCGv_i64 tcg_op = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_res = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>- read_vec_element(s, tcg_op, rn, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op, rn, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (16 * u + opcode) {</div>\r\n" - "<div> case 0x05: /* FMLS */</div>\r\n" - "<div>@@ -12990,7 +12990,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> gen_helper_vfp_negd(tcg_op, tcg_op);</div>\r\n" - "<div> /* fall through */</div>\r\n" - "<div> case 0x01: /* FMLA */</div>\r\n" - "<div>- read_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x09: /* FMUL */</div>\r\n" - "<div>@@ -13003,7 +13003,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- write_vec_element(s, tcg_res, rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res, rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -13241,7 +13241,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Accumulating op: handle accumulate step */</div>\r\n" - "<div>- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */</div>\r\n" - "<div>@@ -13316,7 +13316,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Accumulating op: handle accumulate step */</div>\r\n" - "<div>- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opcode) {</div>\r\n" - "<div> case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */</div>\r\n" - "<div>@@ -13352,7 +13352,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[pass], rd, pass, MO_UQ);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_res[pass]);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -13639,14 +13639,14 @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_res[1] = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);</div>\r\n" - "<div> tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div>\r\n" - "<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_op1);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op2);</div>\r\n" - "<div>@@ -13750,9 +13750,9 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_res[1] = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op3, ra, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op3, ra, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> if (op0 == 0) {</div>\r\n" - "<div> /* EOR3 */</div>\r\n" - "<div>@@ -13763,8 +13763,8 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div>\r\n" - "<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_op1);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op2);</div>\r\n" - "<div>@@ -13832,14 +13832,14 @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> tcg_res[1] = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < 2; pass++) {</div>\r\n" - "<div>- read_vec_element(s, tcg_op1, rn, pass, MO_64);</div>\r\n" - "<div>- read_vec_element(s, tcg_op2, rm, pass, MO_64);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op1, rn, pass, MO_UQ);</div>\r\n" - "<div>+ read_vec_element(s, tcg_op2, rm, pass, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);</div>\r\n" - "<div> tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6);</div>\r\n" - "<div> }</div>\r\n" - "<div>- write_vec_element(s, tcg_res[0], rd, 0, MO_64);</div>\r\n" - "<div>- write_vec_element(s, tcg_res[1], rd, 1, MO_64);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[0], rd, 0, MO_UQ);</div>\r\n" - "<div>+ write_vec_element(s, tcg_res[1], rd, 1, MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_temp_free_i64(tcg_op1);</div>\r\n" - "<div> tcg_temp_free_i64(tcg_op2);</div>\r\n" - "<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div>\r\n" - "<div>index f7c891d..423c461 100644</div>\r\n" - "<div>--- a/target/arm/translate-sve.c</div>\r\n" - "<div>+++ b/target/arm/translate-sve.c</div>\r\n" - "<div>@@ -1708,7 +1708,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,</div>\r\n" - "<div> tcg_temp_free_i64(t64);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (u) {</div>\r\n" - "<div> if (d) {</div>\r\n" - "<div> gen_helper_sve_uqsubi_d(dptr, nptr, val, desc);</div>\r\n" - "<div>@@ -1862,7 +1862,7 @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)</div>\r\n" - "<div> }</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> unsigned vsz = vec_full_reg_size(s);</div>\r\n" - "<div>- gvec_fn(MO_64, vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div>+ gvec_fn(MO_UQ, vec_full_reg_offset(s, a->rd),</div>\r\n" - "<div> vec_full_reg_offset(s, a->rn), imm, vsz, vsz);</div>\r\n" - "<div> }</div>\r\n" - "<div> return true;</div>\r\n" - "<div>@@ -2076,7 +2076,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (sve_access_check(s)) {</div>\r\n" - "<div> TCGv_i64 t = tcg_temp_new_i64();</div>\r\n" - "<div>- tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64));</div>\r\n" - "<div>+ tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_UQ));</div>\r\n" - "<div> do_insr_i64(s, a, t);</div>\r\n" - "<div> tcg_temp_free_i64(t);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -3327,7 +3327,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)</div>\r\n" - "<div> .fno = gen_helper_sve_subri_d,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64,</div>\r\n" - "<div>+ .vece = MO_UQ,</div>\r\n" - "<div> .scalar_first = true }</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -4571,7 +4571,7 @@ static const TCGMemOp dtype_mop[16] = {</div>\r\n" - "<div> MO_UB, MO_UB, MO_UB, MO_UB,</div>\r\n" - "<div> MO_SL, MO_UW, MO_UW, MO_UW,</div>\r\n" - "<div> MO_SW, MO_SW, MO_UL, MO_UL,</div>\r\n" - "<div>- MO_SB, MO_SB, MO_SB, MO_Q</div>\r\n" - "<div>+ MO_SB, MO_SB, MO_SB, MO_UQ</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> #define dtype_msz(x) (dtype_mop[x] & MO_SIZE)</div>\r\n" - "<div>@@ -5261,7 +5261,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> fn = gather_load_fn32[be][a->ff][a->xs][a->u][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> fn = gather_load_fn64[be][a->ff][a->xs][a->u][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -5289,7 +5289,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> fn = gather_load_fn32[be][a->ff][0][a->u][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> fn = gather_load_fn64[be][a->ff][2][a->u][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -5367,7 +5367,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> fn = scatter_store_fn32[be][a->xs][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> fn = scatter_store_fn64[be][a->xs][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -5395,7 +5395,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> fn = scatter_store_fn32[be][0][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> fn = scatter_store_fn64[be][2][a->msz];</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>index 5e0cd63..d71944d 100644</div>\r\n" - "<div>--- a/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>+++ b/target/arm/translate-vfp.inc.c</div>\r\n" - "<div>@@ -40,7 +40,7 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8)</div>\r\n" - "<div> uint64_t imm;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |</div>\r\n" - "<div> (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |</div>\r\n" - "<div> extract32(imm8, 0, 6);</div>\r\n" - "<div>@@ -1960,7 +1960,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));</div>\r\n" - "<div>+ fd = tcg_const_i64(vfp_expand_imm(MO_UQ, a->imm));</div>\r\n" - "<div> </div>\r\n" - "<div> for (;;) {</div>\r\n" - "<div> neon_store_reg64(fd, vd);</div>\r\n" - "<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div>\r\n" - "<div>index 5510ecd..306ef24 100644</div>\r\n" - "<div>--- a/target/arm/translate.c</div>\r\n" - "<div>+++ b/target/arm/translate.c</div>\r\n" - "<div>@@ -1171,7 +1171,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div>\r\n" - "<div> static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,</div>\r\n" - "<div> TCGv_i32 a32, int index)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);</div>\r\n" - "<div>+ gen_aa32_ld_i64(s, val, a32, index, MO_UQ | s->be_data);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div>\r\n" - "<div>@@ -1194,7 +1194,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div>\r\n" - "<div> static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,</div>\r\n" - "<div> TCGv_i32 a32, int index)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);</div>\r\n" - "<div>+ gen_aa32_st_i64(s, val, a32, index, MO_UQ | s->be_data);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> DO_GEN_LD(8s, MO_SB)</div>\r\n" - "<div>@@ -1455,7 +1455,7 @@ static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tcg_gen_ld32u_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_ld_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -1502,7 +1502,7 @@ static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tcg_gen_st32_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_st_i64(var, cpu_env, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -4278,7 +4278,7 @@ const GVecGen2i ssra_op[4] = {</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div> .opt_opc = vecop_list_ssra,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div>@@ -4336,7 +4336,7 @@ const GVecGen2i usra_op[4] = {</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_usra,</div>\r\n" - "<div>- .vece = MO_64, },</div>\r\n" - "<div>+ .vece = MO_UQ, },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div>@@ -4416,7 +4416,7 @@ const GVecGen2i sri_op[4] = {</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sri,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)</div>\r\n" - "<div>@@ -4494,7 +4494,7 @@ const GVecGen2i sli_op[4] = {</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_sli,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)</div>\r\n" - "<div>@@ -4590,7 +4590,7 @@ const GVecGen3 mla_op[4] = {</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mla,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> const GVecGen3 mls_op[4] = {</div>\r\n" - "<div>@@ -4614,7 +4614,7 @@ const GVecGen3 mls_op[4] = {</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div> .load_dest = true,</div>\r\n" - "<div> .opt_opc = vecop_list_mls,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> /* CMTST : test is "if (X & Y != 0)". */</div>\r\n" - "<div>@@ -4658,7 +4658,7 @@ const GVecGen3 cmtst_op[4] = {</div>\r\n" - "<div> .fniv = gen_cmtst_vec,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div> .opt_opc = vecop_list_cmtst,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div>\r\n" - "<div>@@ -4696,7 +4696,7 @@ const GVecGen4 uqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqadd_d,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div> .opt_opc = vecop_list_uqadd,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_sqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div>\r\n" - "<div>@@ -4734,7 +4734,7 @@ const GVecGen4 sqadd_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqadd_d,</div>\r\n" - "<div> .opt_opc = vecop_list_sqadd,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_uqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div>\r\n" - "<div>@@ -4772,7 +4772,7 @@ const GVecGen4 uqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_uqsub_d,</div>\r\n" - "<div> .opt_opc = vecop_list_uqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_sqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,</div>\r\n" - "<div>@@ -4810,7 +4810,7 @@ const GVecGen4 sqsub_op[4] = {</div>\r\n" - "<div> .fno = gen_helper_gvec_sqsub_d,</div>\r\n" - "<div> .opt_opc = vecop_list_sqsub,</div>\r\n" - "<div> .write_aofs = true,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> /* Translate a NEON data processing instruction. Return nonzero if the</div>\r\n" - "<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div>\r\n" - "<div>index 0e863d4..8d62b37 100644</div>\r\n" - "<div>--- a/target/i386/translate.c</div>\r\n" - "<div>+++ b/target/i386/translate.c</div>\r\n" - "<div>@@ -323,7 +323,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int reg)</div>\r\n" - "<div> static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (CODE64(s)) {</div>\r\n" - "<div>- return ot == MO_UW ? MO_UW : MO_64;</div>\r\n" - "<div>+ return ot == MO_UW ? MO_UW : MO_UQ;</div>\r\n" - "<div> } else {</div>\r\n" - "<div> return ot;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -332,14 +332,14 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> /* Select the size of the stack pointer. */</div>\r\n" - "<div> static inline TCGMemOp mo_stacksize(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- return CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div>+ return CODE64(s) ? MO_UQ : s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div>\r\n" - "<div> static inline TCGMemOp mo_64_32(TCGMemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- return ot == MO_64 ? MO_64 : MO_UL;</div>\r\n" - "<div>+ return ot == MO_UQ ? MO_UQ : MO_UL;</div>\r\n" - "<div> #else</div>\r\n" - "<div> return MO_UL;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -378,7 +378,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div> tcg_gen_ext32u_tl(cpu_regs[reg], t0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_regs[reg], t0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -456,7 +456,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (aflag) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (ovr_seg < 0) {</div>\r\n" - "<div> tcg_gen_mov_tl(s->A0, a0);</div>\r\n" - "<div> return;</div>\r\n" - "<div>@@ -492,7 +492,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div>\r\n" - "<div> if (ovr_seg >= 0) {</div>\r\n" - "<div> TCGv seg = cpu_seg_base[ovr_seg];</div>\r\n" - "<div> </div>\r\n" - "<div>- if (aflag == MO_64) {</div>\r\n" - "<div>+ if (aflag == MO_UQ) {</div>\r\n" - "<div> tcg_gen_add_tl(s->A0, a0, seg);</div>\r\n" - "<div> } else if (CODE64(s)) {</div>\r\n" - "<div> tcg_gen_ext32u_tl(s->A0, a0);</div>\r\n" - "<div>@@ -1469,7 +1469,7 @@ static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,</div>\r\n" - "<div> static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> int is_right, int is_arith)</div>\r\n" - "<div> {</div>\r\n" - "<div>- target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div>+ target_ulong mask = (ot == MO_UQ ? 0x3f : 0x1f);</div>\r\n" - "<div> </div>\r\n" - "<div> /* load */</div>\r\n" - "<div> if (op1 == OR_TMP0) {</div>\r\n" - "<div>@@ -1505,7 +1505,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> int is_right, int is_arith)</div>\r\n" - "<div> {</div>\r\n" - "<div>- int mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div>+ int mask = (ot == MO_UQ ? 0x3f : 0x1f);</div>\r\n" - "<div> </div>\r\n" - "<div> /* load */</div>\r\n" - "<div> if (op1 == OR_TMP0)</div>\r\n" - "<div>@@ -1544,7 +1544,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div>\r\n" - "<div> {</div>\r\n" - "<div>- target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div>+ target_ulong mask = (ot == MO_UQ ? 0x3f : 0x1f);</div>\r\n" - "<div> TCGv_i32 t0, t1;</div>\r\n" - "<div> </div>\r\n" - "<div> /* load */</div>\r\n" - "<div>@@ -1630,7 +1630,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div>\r\n" - "<div> static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> int is_right)</div>\r\n" - "<div> {</div>\r\n" - "<div>- int mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div>+ int mask = (ot == MO_UQ ? 0x3f : 0x1f);</div>\r\n" - "<div> int shift;</div>\r\n" - "<div> </div>\r\n" - "<div> /* load */</div>\r\n" - "<div>@@ -1729,7 +1729,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> gen_helper_rcrl(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> gen_helper_rcrq(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -1748,7 +1748,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> gen_helper_rcll(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> gen_helper_rclq(s->T0, cpu_env, s->T0, s->T1);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -1764,7 +1764,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> bool is_right, TCGv count_in)</div>\r\n" - "<div> {</div>\r\n" - "<div>- target_ulong mask = (ot == MO_64 ? 63 : 31);</div>\r\n" - "<div>+ target_ulong mask = (ot == MO_UQ ? 63 : 31);</div>\r\n" - "<div> TCGv count;</div>\r\n" - "<div> </div>\r\n" - "<div> /* load */</div>\r\n" - "<div>@@ -1983,7 +1983,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> switch (s->aflag) {</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> havesib = 0;</div>\r\n" - "<div> if (rm == 4) {</div>\r\n" - "<div>@@ -2192,7 +2192,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> #endif</div>\r\n" - "<div> ret = x86_ldl_code(env, s);</div>\r\n" - "<div> break;</div>\r\n" - "<div>@@ -2443,7 +2443,7 @@ static void gen_popa(DisasContext *s)</div>\r\n" - "<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div>+ TCGMemOp a_ot = CODE64(s) ? MO_UQ : s->ss32 ? MO_UL : MO_UW;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Push BP; compute FrameTemp into T1. */</div>\r\n" - "<div>@@ -3150,8 +3150,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x6e: /* movd mm, ea */</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- if (s->dflag == MO_64) {</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);</div>\r\n" - "<div>+ if (s->dflag == MO_UQ) {</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 0);</div>\r\n" - "<div> tcg_gen_st_tl(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State, fpregs[reg].mmx));</div>\r\n" - "<div> } else</div>\r\n" - "<div>@@ -3166,8 +3166,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x16e: /* movd xmm, ea */</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- if (s->dflag == MO_64) {</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);</div>\r\n" - "<div>+ if (s->dflag == MO_UQ) {</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 0);</div>\r\n" - "<div> tcg_gen_addi_ptr(s->ptr0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,xmm_regs[reg]));</div>\r\n" - "<div> gen_helper_movq_mm_T0_xmm(s->ptr0, s->T0);</div>\r\n" - "<div>@@ -3337,10 +3337,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x7e: /* movd ea, mm */</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- if (s->dflag == MO_64) {</div>\r\n" - "<div>+ if (s->dflag == MO_UQ) {</div>\r\n" - "<div> tcg_gen_ld_i64(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,fpregs[reg].mmx));</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 1);</div>\r\n" - "<div> } else</div>\r\n" - "<div> #endif</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -3351,10 +3351,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0x17e: /* movd ea, xmm */</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- if (s->dflag == MO_64) {</div>\r\n" - "<div>+ if (s->dflag == MO_UQ) {</div>\r\n" - "<div> tcg_gen_ld_i64(s->T0, cpu_env,</div>\r\n" - "<div> offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));</div>\r\n" - "<div>- gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);</div>\r\n" - "<div>+ gen_ldst_modrm(env, s, modrm, MO_UQ, OR_TMP0, 1);</div>\r\n" - "<div> } else</div>\r\n" - "<div> #endif</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -3785,10 +3785,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> }</div>\r\n" - "<div> if ((b & 0xff) == 0xf0) {</div>\r\n" - "<div> ot = MO_UB;</div>\r\n" - "<div>- } else if (s->dflag != MO_64) {</div>\r\n" - "<div>+ } else if (s->dflag != MO_UQ) {</div>\r\n" - "<div> ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- ot = MO_64;</div>\r\n" - "<div>+ ot = MO_UQ;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[reg]);</div>\r\n" - "<div>@@ -3814,10 +3814,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div>- if (s->dflag != MO_64) {</div>\r\n" - "<div>+ if (s->dflag != MO_UQ) {</div>\r\n" - "<div> ot = (s->prefix & PREFIX_DATA ? MO_UW : MO_UL);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- ot = MO_64;</div>\r\n" - "<div>+ ot = MO_UQ;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> gen_lea_modrm(env, s, modrm);</div>\r\n" - "<div>@@ -3861,7 +3861,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> tcg_gen_ext8u_tl(s->A0, cpu_regs[s->vex_v]);</div>\r\n" - "<div> tcg_gen_shr_tl(s->T0, s->T0, s->A0);</div>\r\n" - "<div> </div>\r\n" - "<div>- bound = tcg_const_tl(ot == MO_64 ? 63 : 31);</div>\r\n" - "<div>+ bound = tcg_const_tl(ot == MO_UQ ? 63 : 31);</div>\r\n" - "<div> zero = tcg_const_tl(0);</div>\r\n" - "<div> tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound,</div>\r\n" - "<div> s->T0, zero);</div>\r\n" - "<div>@@ -3894,7 +3894,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div>\r\n" - "<div> tcg_gen_ext8u_tl(s->T1, cpu_regs[s->vex_v]);</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31);</div>\r\n" - "<div>+ TCGv bound = tcg_const_tl(ot == MO_UQ ? 63 : 31);</div>\r\n" - "<div> /* Note that since we're using BMILG (in order to get O</div>\r\n" - "<div> cleared) we need to store the inverse into C. */</div>\r\n" - "<div> tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src,</div>\r\n" - "<div>@@ -3929,7 +3929,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp3_i32);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_mulu2_i64(s->T0, s->T1,</div>\r\n" - "<div> s->T0, cpu_regs[R_EDX]);</div>\r\n" - "<div> tcg_gen_mov_i64(cpu_regs[s->vex_v], s->T0);</div>\r\n" - "<div>@@ -3949,7 +3949,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div>\r\n" - "<div> /* Note that by zero-extending the mask operand, we</div>\r\n" - "<div> automatically handle zero-extending the result. */</div>\r\n" - "<div>- if (ot == MO_64) {</div>\r\n" - "<div>+ if (ot == MO_UQ) {</div>\r\n" - "<div> tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]);</div>\r\n" - "<div>@@ -3967,7 +3967,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div>\r\n" - "<div> /* Note that by zero-extending the mask operand, we</div>\r\n" - "<div> automatically handle zero-extending the result. */</div>\r\n" - "<div>- if (ot == MO_64) {</div>\r\n" - "<div>+ if (ot == MO_UQ) {</div>\r\n" - "<div> tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]);</div>\r\n" - "<div>@@ -4063,7 +4063,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> }</div>\r\n" - "<div> ot = mo_64_32(s->dflag);</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div>\r\n" - "<div>- if (ot == MO_64) {</div>\r\n" - "<div>+ if (ot == MO_UQ) {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T1, cpu_regs[s->vex_v], 63);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_andi_tl(s->T1, cpu_regs[s->vex_v], 31);</div>\r\n" - "<div>@@ -4071,12 +4071,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> if (b == 0x1f7) {</div>\r\n" - "<div> tcg_gen_shl_tl(s->T0, s->T0, s->T1);</div>\r\n" - "<div> } else if (b == 0x2f7) {</div>\r\n" - "<div>- if (ot != MO_64) {</div>\r\n" - "<div>+ if (ot != MO_UQ) {</div>\r\n" - "<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_sar_tl(s->T0, s->T0, s->T1);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- if (ot != MO_64) {</div>\r\n" - "<div>+ if (ot != MO_UQ) {</div>\r\n" - "<div> tcg_gen_ext32u_tl(s->T0, s->T0);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_gen_shr_tl(s->T0, s->T0, s->T1);</div>\r\n" - "<div>@@ -4302,7 +4302,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> if ((b & 0xfc) == 0x60) { /* pcmpXstrX */</div>\r\n" - "<div> set_cc_op(s, CC_OP_EFLAGS);</div>\r\n" - "<div> </div>\r\n" - "<div>- if (s->dflag == MO_64) {</div>\r\n" - "<div>+ if (s->dflag == MO_UQ) {</div>\r\n" - "<div> /* The helper must use entire 64-bit gp registers */</div>\r\n" - "<div> val |= 1 << 8;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -4329,7 +4329,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> ot = mo_64_32(s->dflag);</div>\r\n" - "<div> gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);</div>\r\n" - "<div> b = x86_ldub_code(env, s);</div>\r\n" - "<div>- if (ot == MO_64) {</div>\r\n" - "<div>+ if (ot == MO_UQ) {</div>\r\n" - "<div> tcg_gen_rotri_tl(s->T0, s->T0, b & 63);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);</div>\r\n" - "<div>@@ -4630,9 +4630,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> /* In 64-bit mode, the default data size is 32-bit. Select 64-bit</div>\r\n" - "<div> data with rex_w, and 16-bit data with 0x66; rex_w takes precedence</div>\r\n" - "<div> over 0x66 if both are present. */</div>\r\n" - "<div>- dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_UW : MO_UL);</div>\r\n" - "<div>+ dflag = (rex_w > 0 ? MO_UQ : prefixes & PREFIX_DATA ? MO_UW : MO_UL);</div>\r\n" - "<div> /* In 64-bit mode, 0x67 selects 32-bit addressing. */</div>\r\n" - "<div>- aflag = (prefixes & PREFIX_ADR ? MO_UL : MO_64);</div>\r\n" - "<div>+ aflag = (prefixes & PREFIX_ADR ? MO_UL : MO_UQ);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> /* In 16/32-bit mode, 0x66 selects the opposite data size. */</div>\r\n" - "<div> if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {</div>\r\n" - "<div>@@ -4903,7 +4903,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULL);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],</div>\r\n" - "<div> s->T0, cpu_regs[R_EAX]);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);</div>\r\n" - "<div>@@ -4956,7 +4956,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> set_cc_op(s, CC_OP_MULL);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],</div>\r\n" - "<div> s->T0, cpu_regs[R_EAX]);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);</div>\r\n" - "<div>@@ -4980,7 +4980,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_helper_divl_EAX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> gen_helper_divq_EAX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -4999,7 +4999,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> gen_helper_idivl_EAX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> gen_helper_idivq_EAX(cpu_env, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -5024,7 +5024,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (CODE64(s)) {</div>\r\n" - "<div> if (op == 2 || op == 4) {</div>\r\n" - "<div> /* operand size for jumps is 64 bit */</div>\r\n" - "<div>- ot = MO_64;</div>\r\n" - "<div>+ ot = MO_UQ;</div>\r\n" - "<div> } else if (op == 3 || op == 5) {</div>\r\n" - "<div> ot = dflag != MO_UW ? MO_UL + (rex_w == 1) : MO_UW;</div>\r\n" - "<div> } else if (op == 6) {</div>\r\n" - "<div>@@ -5145,10 +5145,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x98: /* CWDE/CBW */</div>\r\n" - "<div> switch (dflag) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> gen_op_mov_v_reg(s, MO_UL, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_64, R_EAX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UQ, R_EAX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div>@@ -5168,10 +5168,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x99: /* CDQ/CWD */</div>\r\n" - "<div> switch (dflag) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_64, s->T0, R_EAX);</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UQ, s->T0, R_EAX);</div>\r\n" - "<div> tcg_gen_sari_tl(s->T0, s->T0, 63);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_64, R_EDX, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UQ, R_EDX, s->T0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div>@@ -5212,7 +5212,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> }</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_muls2_i64(cpu_regs[reg], s->T1, s->T0, s->T1);</div>\r\n" - "<div> tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);</div>\r\n" - "<div> tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);</div>\r\n" - "<div>@@ -5338,7 +5338,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- if (dflag == MO_64) {</div>\r\n" - "<div>+ if (dflag == MO_UQ) {</div>\r\n" - "<div> if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) {</div>\r\n" - "<div> goto illegal_op;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -5636,7 +5636,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> ot = mo_b_d(b, dflag);</div>\r\n" - "<div> switch (s->aflag) {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> offset_addr = x86_ldq_code(env, s);</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -5671,13 +5671,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> break;</div>\r\n" - "<div> case 0xb8 ... 0xbf: /* mov R, Iv */</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- if (dflag == MO_64) {</div>\r\n" - "<div>+ if (dflag == MO_UQ) {</div>\r\n" - "<div> uint64_t tmp;</div>\r\n" - "<div> /* 64 bit case */</div>\r\n" - "<div> tmp = x86_ldq_code(env, s);</div>\r\n" - "<div> reg = (b & 7) | REX_B(s);</div>\r\n" - "<div> tcg_gen_movi_tl(s->T0, tmp);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_64, reg, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UQ, reg, s->T0);</div>\r\n" - "<div> } else</div>\r\n" - "<div> #endif</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -7119,10 +7119,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x1c8 ... 0x1cf: /* bswap reg */</div>\r\n" - "<div> reg = (b & 7) | REX_B(s);</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div>- if (dflag == MO_64) {</div>\r\n" - "<div>- gen_op_mov_v_reg(s, MO_64, s->T0, reg);</div>\r\n" - "<div>+ if (dflag == MO_UQ) {</div>\r\n" - "<div>+ gen_op_mov_v_reg(s, MO_UQ, s->T0, reg);</div>\r\n" - "<div> tcg_gen_bswap64_i64(s->T0, s->T0);</div>\r\n" - "<div>- gen_op_mov_reg_v(s, MO_64, reg, s->T0);</div>\r\n" - "<div>+ gen_op_mov_reg_v(s, MO_UQ, reg, s->T0);</div>\r\n" - "<div> } else</div>\r\n" - "<div> #endif</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -7700,7 +7700,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> if (mod == 3) {</div>\r\n" - "<div> gen_op_mov_v_reg(s, MO_UL, s->T0, rm);</div>\r\n" - "<div> /* sign extend */</div>\r\n" - "<div>- if (d_ot == MO_64) {</div>\r\n" - "<div>+ if (d_ot == MO_UQ) {</div>\r\n" - "<div> tcg_gen_ext32s_tl(s->T0, s->T0);</div>\r\n" - "<div> }</div>\r\n" - "<div> gen_op_mov_reg_v(s, d_ot, reg, s->T0);</div>\r\n" - "<div>@@ -8014,7 +8014,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> rm = (modrm & 7) | REX_B(s);</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div> if (CODE64(s))</div>\r\n" - "<div>- ot = MO_64;</div>\r\n" - "<div>+ ot = MO_UQ;</div>\r\n" - "<div> else</div>\r\n" - "<div> ot = MO_UL;</div>\r\n" - "<div> if ((prefixes & PREFIX_LOCK) && (reg == 0) &&</div>\r\n" - "<div>@@ -8071,7 +8071,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> rm = (modrm & 7) | REX_B(s);</div>\r\n" - "<div> reg = ((modrm >> 3) & 7) | rex_r;</div>\r\n" - "<div> if (CODE64(s))</div>\r\n" - "<div>- ot = MO_64;</div>\r\n" - "<div>+ ot = MO_UQ;</div>\r\n" - "<div> else</div>\r\n" - "<div> ot = MO_UL;</div>\r\n" - "<div> if (reg >= 8) {</div>\r\n" - "<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div>\r\n" - "<div>index 525c7fe..1023f68 100644</div>\r\n" - "<div>--- a/target/mips/translate.c</div>\r\n" - "<div>+++ b/target/mips/translate.c</div>\r\n" - "<div>@@ -3766,7 +3766,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));</div>\r\n" - "<div> tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,</div>\r\n" - "<div>- eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);</div>\r\n" - "<div>+ eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_UQ);</div>\r\n" - "<div> if (reg1 != 0) {</div>\r\n" - "<div> tcg_gen_movi_tl(cpu_gpr[reg1], 1);</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/target/ppc/translate.c b/target/ppc/translate.c</div>\r\n" - "<div>index 4a5de28..f39dd94 100644</div>\r\n" - "<div>--- a/target/ppc/translate.c</div>\r\n" - "<div>+++ b/target/ppc/translate.c</div>\r\n" - "<div>@@ -2470,10 +2470,10 @@ GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))</div>\r\n" - "<div> GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))</div>\r\n" - "<div> GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))</div>\r\n" - "<div> GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))</div>\r\n" - "<div>-GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))</div>\r\n" - "<div>+GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ))</div>\r\n" - "<div> </div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>-GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))</div>\r\n" - "<div>+GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> #define GEN_QEMU_STORE_TL(stop, op) \\</div>\r\n" - "<div>@@ -2502,10 +2502,10 @@ static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \\</div>\r\n" - "<div> GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))</div>\r\n" - "<div> GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))</div>\r\n" - "<div> GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))</div>\r\n" - "<div>-GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))</div>\r\n" - "<div>+GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ))</div>\r\n" - "<div> </div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>-GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))</div>\r\n" - "<div>+GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> #define GEN_LD(name, ldop, opc, type) \\</div>\r\n" - "<div>@@ -2605,7 +2605,7 @@ GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)</div>\r\n" - "<div> GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)</div>\r\n" - "<div> GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)</div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>-GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)</div>\r\n" - "<div>+GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>@@ -2808,7 +2808,7 @@ GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)</div>\r\n" - "<div> GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)</div>\r\n" - "<div> GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)</div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>-GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)</div>\r\n" - "<div>+GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04)</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>@@ -3244,7 +3244,7 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)</div>\r\n" - "<div> TCGv t1 = tcg_temp_new();</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);</div>\r\n" - "<div>- if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {</div>\r\n" - "<div>+ if ((memop & MO_SIZE) == MO_UQ || TARGET_LONG_BITS == 32) {</div>\r\n" - "<div> tcg_gen_mov_tl(t1, src);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_ext32u_tl(t1, src);</div>\r\n" - "<div>@@ -3302,7 +3302,7 @@ static void gen_lwat(DisasContext *ctx)</div>\r\n" - "<div> #ifdef TARGET_PPC64</div>\r\n" - "<div> static void gen_ldat(DisasContext *ctx)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));</div>\r\n" - "<div>+ gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));</div>\r\n" - "<div> }</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3385,7 +3385,7 @@ static void gen_stwat(DisasContext *ctx)</div>\r\n" - "<div> #ifdef TARGET_PPC64</div>\r\n" - "<div> static void gen_stdat(DisasContext *ctx)</div>\r\n" - "<div> {</div>\r\n" - "<div>- gen_st_atomic(ctx, DEF_MEMOP(MO_Q));</div>\r\n" - "<div>+ gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));</div>\r\n" - "<div> }</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3437,9 +3437,9 @@ STCX(stwcx_, DEF_MEMOP(MO_UL))</div>\r\n" - "<div> </div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div> /* ldarx */</div>\r\n" - "<div>-LARX(ldarx, DEF_MEMOP(MO_Q))</div>\r\n" - "<div>+LARX(ldarx, DEF_MEMOP(MO_UQ))</div>\r\n" - "<div> /* stdcx. */</div>\r\n" - "<div>-STCX(stdcx_, DEF_MEMOP(MO_Q))</div>\r\n" - "<div>+STCX(stdcx_, DEF_MEMOP(MO_UQ))</div>\r\n" - "<div> </div>\r\n" - "<div> /* lqarx */</div>\r\n" - "<div> static void gen_lqarx(DisasContext *ctx)</div>\r\n" - "<div>@@ -3520,7 +3520,7 @@ static void gen_stqcx_(DisasContext *ctx)</div>\r\n" - "<div> </div>\r\n" - "<div> if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {</div>\r\n" - "<div> if (HAVE_CMPXCHG128) {</div>\r\n" - "<div>- TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);</div>\r\n" - "<div>+ TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_UQ) | MO_ALIGN_16);</div>\r\n" - "<div> if (ctx->le_mode) {</div>\r\n" - "<div> gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,</div>\r\n" - "<div> EA, lo, hi, oi);</div>\r\n" - "<div>@@ -7366,7 +7366,7 @@ GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)</div>\r\n" - "<div> GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)</div>\r\n" - "<div> GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)</div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>-GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)</div>\r\n" - "<div>+GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> #undef GEN_ST</div>\r\n" - "<div>@@ -7412,7 +7412,7 @@ GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)</div>\r\n" - "<div> GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)</div>\r\n" - "<div> GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)</div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div>-GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)</div>\r\n" - "<div>+GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04)</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> #undef GEN_CRLOGIC</div>\r\n" - "<div>diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c</div>\r\n" - "<div>index 9dcff94..3fd54ac 100644</div>\r\n" - "<div>--- a/target/ppc/translate/fp-impl.inc.c</div>\r\n" - "<div>+++ b/target/ppc/translate/fp-impl.inc.c</div>\r\n" - "<div>@@ -855,7 +855,7 @@ static void gen_lfdepx(DisasContext *ctx)</div>\r\n" - "<div> EA = tcg_temp_new();</div>\r\n" - "<div> t0 = tcg_temp_new_i64();</div>\r\n" - "<div> gen_addr_reg_index(ctx, EA);</div>\r\n" - "<div>- tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q));</div>\r\n" - "<div>+ tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UQ));</div>\r\n" - "<div> set_fpr(rD(ctx->opcode), t0);</div>\r\n" - "<div> tcg_temp_free(EA);</div>\r\n" - "<div> tcg_temp_free_i64(t0);</div>\r\n" - "<div>@@ -1091,7 +1091,7 @@ static void gen_stfdepx(DisasContext *ctx)</div>\r\n" - "<div> t0 = tcg_temp_new_i64();</div>\r\n" - "<div> gen_addr_reg_index(ctx, EA);</div>\r\n" - "<div> get_fpr(t0, rD(ctx->opcode));</div>\r\n" - "<div>- tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q));</div>\r\n" - "<div>+ tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_UQ));</div>\r\n" - "<div> tcg_temp_free(EA);</div>\r\n" - "<div> tcg_temp_free_i64(t0);</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>index 8aa767e..867dc52 100644</div>\r\n" - "<div>--- a/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>+++ b/target/ppc/translate/vmx-impl.inc.c</div>\r\n" - "<div>@@ -290,14 +290,14 @@ static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Logical operations */</div>\r\n" - "<div>-GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);</div>\r\n" - "<div>-GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);</div>\r\n" - "<div>-GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);</div>\r\n" - "<div>-GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);</div>\r\n" - "<div>-GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);</div>\r\n" - "<div>-GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);</div>\r\n" - "<div>-GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);</div>\r\n" - "<div>-GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);</div>\r\n" - "<div>+GEN_VXFORM_V(vand, MO_UQ, tcg_gen_gvec_and, 2, 16);</div>\r\n" - "<div>+GEN_VXFORM_V(vandc, MO_UQ, tcg_gen_gvec_andc, 2, 17);</div>\r\n" - "<div>+GEN_VXFORM_V(vor, MO_UQ, tcg_gen_gvec_or, 2, 18);</div>\r\n" - "<div>+GEN_VXFORM_V(vxor, MO_UQ, tcg_gen_gvec_xor, 2, 19);</div>\r\n" - "<div>+GEN_VXFORM_V(vnor, MO_UQ, tcg_gen_gvec_nor, 2, 20);</div>\r\n" - "<div>+GEN_VXFORM_V(veqv, MO_UQ, tcg_gen_gvec_eqv, 2, 26);</div>\r\n" - "<div>+GEN_VXFORM_V(vnand, MO_UQ, tcg_gen_gvec_nand, 2, 22);</div>\r\n" - "<div>+GEN_VXFORM_V(vorc, MO_UQ, tcg_gen_gvec_orc, 2, 21);</div>\r\n" - "<div> </div>\r\n" - "<div> #define GEN_VXFORM(name, opc2, opc3) \\</div>\r\n" - "<div> static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div>@@ -410,27 +410,27 @@ GEN_VXFORM_V(vadduhm, MO_UW, tcg_gen_gvec_add, 0, 1);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vmul10ecuq, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div> GEN_VXFORM_V(vadduwm, MO_UL, tcg_gen_gvec_add, 0, 2);</div>\r\n" - "<div>-GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);</div>\r\n" - "<div>+GEN_VXFORM_V(vaddudm, MO_UQ, tcg_gen_gvec_add, 0, 3);</div>\r\n" - "<div> GEN_VXFORM_V(vsububm, MO_UB, tcg_gen_gvec_sub, 0, 16);</div>\r\n" - "<div> GEN_VXFORM_V(vsubuhm, MO_UW, tcg_gen_gvec_sub, 0, 17);</div>\r\n" - "<div> GEN_VXFORM_V(vsubuwm, MO_UL, tcg_gen_gvec_sub, 0, 18);</div>\r\n" - "<div>-GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);</div>\r\n" - "<div>+GEN_VXFORM_V(vsubudm, MO_UQ, tcg_gen_gvec_sub, 0, 19);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxub, MO_UB, tcg_gen_gvec_umax, 1, 0);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxuh, MO_UW, tcg_gen_gvec_umax, 1, 1);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxuw, MO_UL, tcg_gen_gvec_umax, 1, 2);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxud, MO_UQ, tcg_gen_gvec_umax, 1, 3);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsb, MO_UB, tcg_gen_gvec_smax, 1, 4);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsh, MO_UW, tcg_gen_gvec_smax, 1, 5);</div>\r\n" - "<div> GEN_VXFORM_V(vmaxsw, MO_UL, tcg_gen_gvec_smax, 1, 6);</div>\r\n" - "<div>-GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);</div>\r\n" - "<div>+GEN_VXFORM_V(vmaxsd, MO_UQ, tcg_gen_gvec_smax, 1, 7);</div>\r\n" - "<div> GEN_VXFORM_V(vminub, MO_UB, tcg_gen_gvec_umin, 1, 8);</div>\r\n" - "<div> GEN_VXFORM_V(vminuh, MO_UW, tcg_gen_gvec_umin, 1, 9);</div>\r\n" - "<div> GEN_VXFORM_V(vminuw, MO_UL, tcg_gen_gvec_umin, 1, 10);</div>\r\n" - "<div>-GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);</div>\r\n" - "<div>+GEN_VXFORM_V(vminud, MO_UQ, tcg_gen_gvec_umin, 1, 11);</div>\r\n" - "<div> GEN_VXFORM_V(vminsb, MO_UB, tcg_gen_gvec_smin, 1, 12);</div>\r\n" - "<div> GEN_VXFORM_V(vminsh, MO_UW, tcg_gen_gvec_smin, 1, 13);</div>\r\n" - "<div> GEN_VXFORM_V(vminsw, MO_UL, tcg_gen_gvec_smin, 1, 14);</div>\r\n" - "<div>-GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);</div>\r\n" - "<div>+GEN_VXFORM_V(vminsd, MO_UQ, tcg_gen_gvec_smin, 1, 15);</div>\r\n" - "<div> GEN_VXFORM(vavgub, 1, 16);</div>\r\n" - "<div> GEN_VXFORM(vabsdub, 1, 16);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div>@@ -536,15 +536,15 @@ GEN_VXFORM_V(vslw, MO_UL, tcg_gen_gvec_shlv, 2, 6);</div>\r\n" - "<div> GEN_VXFORM(vrlwnm, 2, 6);</div>\r\n" - "<div> GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \\</div>\r\n" - "<div> vrlwnm, PPC_NONE, PPC2_ISA300)</div>\r\n" - "<div>-GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);</div>\r\n" - "<div>+GEN_VXFORM_V(vsld, MO_UQ, tcg_gen_gvec_shlv, 2, 23);</div>\r\n" - "<div> GEN_VXFORM_V(vsrb, MO_UB, tcg_gen_gvec_shrv, 2, 8);</div>\r\n" - "<div> GEN_VXFORM_V(vsrh, MO_UW, tcg_gen_gvec_shrv, 2, 9);</div>\r\n" - "<div> GEN_VXFORM_V(vsrw, MO_UL, tcg_gen_gvec_shrv, 2, 10);</div>\r\n" - "<div>-GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);</div>\r\n" - "<div>+GEN_VXFORM_V(vsrd, MO_UQ, tcg_gen_gvec_shrv, 2, 27);</div>\r\n" - "<div> GEN_VXFORM_V(vsrab, MO_UB, tcg_gen_gvec_sarv, 2, 12);</div>\r\n" - "<div> GEN_VXFORM_V(vsrah, MO_UW, tcg_gen_gvec_sarv, 2, 13);</div>\r\n" - "<div> GEN_VXFORM_V(vsraw, MO_UL, tcg_gen_gvec_sarv, 2, 14);</div>\r\n" - "<div>-GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);</div>\r\n" - "<div>+GEN_VXFORM_V(vsrad, MO_UQ, tcg_gen_gvec_sarv, 2, 15);</div>\r\n" - "<div> GEN_VXFORM(vsrv, 2, 28);</div>\r\n" - "<div> GEN_VXFORM(vslv, 2, 29);</div>\r\n" - "<div> GEN_VXFORM(vslo, 6, 16);</div>\r\n" - "<div>diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c</div>\r\n" - "<div>index 212817e..d607974 100644</div>\r\n" - "<div>--- a/target/ppc/translate/vsx-impl.inc.c</div>\r\n" - "<div>+++ b/target/ppc/translate/vsx-impl.inc.c</div>\r\n" - "<div>@@ -1475,14 +1475,14 @@ static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div> vsr_full_offset(xB(ctx->opcode)), 16, 16); \\</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)</div>\r\n" - "<div>-VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)</div>\r\n" - "<div>-VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)</div>\r\n" - "<div>-VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)</div>\r\n" - "<div>-VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)</div>\r\n" - "<div>-VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)</div>\r\n" - "<div>-VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)</div>\r\n" - "<div>-VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)</div>\r\n" - "<div>+VSX_LOGICAL(xxland, MO_UQ, tcg_gen_gvec_and)</div>\r\n" - "<div>+VSX_LOGICAL(xxlandc, MO_UQ, tcg_gen_gvec_andc)</div>\r\n" - "<div>+VSX_LOGICAL(xxlor, MO_UQ, tcg_gen_gvec_or)</div>\r\n" - "<div>+VSX_LOGICAL(xxlxor, MO_UQ, tcg_gen_gvec_xor)</div>\r\n" - "<div>+VSX_LOGICAL(xxlnor, MO_UQ, tcg_gen_gvec_nor)</div>\r\n" - "<div>+VSX_LOGICAL(xxleqv, MO_UQ, tcg_gen_gvec_eqv)</div>\r\n" - "<div>+VSX_LOGICAL(xxlnand, MO_UQ, tcg_gen_gvec_nand)</div>\r\n" - "<div>+VSX_LOGICAL(xxlorc, MO_UQ, tcg_gen_gvec_orc)</div>\r\n" - "<div> </div>\r\n" - "<div> #define VSX_XXMRG(name, high) \\</div>\r\n" - "<div> static void glue(gen_, name)(DisasContext *ctx) \\</div>\r\n" - "<div>@@ -1535,7 +1535,7 @@ static void gen_xxsel(DisasContext *ctx)</div>\r\n" - "<div> gen_exception(ctx, POWERPC_EXCP_VSXU);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>- tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc),</div>\r\n" - "<div>+ tcg_gen_gvec_bitsel(MO_UQ, vsr_full_offset(rt), vsr_full_offset(rc),</div>\r\n" - "<div> vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div>\r\n" - "<div>index 9e646f1..5c72db1 100644</div>\r\n" - "<div>--- a/target/s390x/translate.c</div>\r\n" - "<div>+++ b/target/s390x/translate.c</div>\r\n" - "<div>@@ -180,7 +180,7 @@ static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div>\r\n" - "<div> * the two 8 byte elements have to be loaded separately. Let's force all</div>\r\n" - "<div> * 16 byte operations to handle it in a special way.</div>\r\n" - "<div> */</div>\r\n" - "<div>- g_assert(es <= MO_64);</div>\r\n" - "<div>+ g_assert(es <= MO_UQ);</div>\r\n" - "<div> #ifndef HOST_WORDS_BIGENDIAN</div>\r\n" - "<div> offs ^= (8 - bytes);</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -190,7 +190,7 @@ static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div>\r\n" - "<div> static inline int freg64_offset(uint8_t reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> g_assert(reg < 16);</div>\r\n" - "<div>- return vec_reg_offset(reg, 0, MO_64);</div>\r\n" - "<div>+ return vec_reg_offset(reg, 0, MO_UQ);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static inline int freg32_offset(uint8_t reg)</div>\r\n" - "<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>index 75d788c..6252262 100644</div>\r\n" - "<div>--- a/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>+++ b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>@@ -30,8 +30,8 @@</div>\r\n" - "<div> * Sizes:</div>\r\n" - "<div> * On s390x, the operand size (oprsz) and the maximum size (maxsz) are</div>\r\n" - "<div> * always 16 (128 bit). What gvec code calls "vece", s390x calls "es",</div>\r\n" - "<div>- * a.k.a. "element size". These values nicely map to MO_UB ... MO_64. Only</div>\r\n" - "<div>- * 128 bit element size has to be treated in a special way (MO_64 + 1).</div>\r\n" - "<div>+ * a.k.a. "element size". These values nicely map to MO_UB ... MO_UQ. Only</div>\r\n" - "<div>+ * 128 bit element size has to be treated in a special way (MO_UQ + 1).</div>\r\n" - "<div> * We will use ES_* instead of MO_* for this reason in this file.</div>\r\n" - "<div> *</div>\r\n" - "<div> * CC handling:</div>\r\n" - "<div>@@ -49,7 +49,7 @@</div>\r\n" - "<div> #define ES_8 MO_UB</div>\r\n" - "<div> #define ES_16 MO_UW</div>\r\n" - "<div> #define ES_32 MO_UL</div>\r\n" - "<div>-#define ES_64 MO_64</div>\r\n" - "<div>+#define ES_64 MO_UQ</div>\r\n" - "<div> #define ES_128 4</div>\r\n" - "<div> </div>\r\n" - "<div> /* Floating-Point Format */</div>\r\n" - "<div>diff --git a/target/s390x/vec.h b/target/s390x/vec.h</div>\r\n" - "<div>index f67392c..b59da65 100644</div>\r\n" - "<div>--- a/target/s390x/vec.h</div>\r\n" - "<div>+++ b/target/s390x/vec.h</div>\r\n" - "<div>@@ -82,7 +82,7 @@ static inline uint64_t s390_vec_read_element(const S390Vector *v, uint8_t enr,</div>\r\n" - "<div> return s390_vec_read_element16(v, enr);</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> return s390_vec_read_element32(v, enr);</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> return s390_vec_read_element64(v, enr);</div>\r\n" - "<div> default:</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div>@@ -130,7 +130,7 @@ static inline void s390_vec_write_element(S390Vector *v, uint8_t enr,</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> s390_vec_write_element32(v, enr, data);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> s390_vec_write_element64(v, enr, data);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>diff --git a/target/sparc/translate.c b/target/sparc/translate.c</div>\r\n" - "<div>index 091bab5..499622b 100644</div>\r\n" - "<div>--- a/target/sparc/translate.c</div>\r\n" - "<div>+++ b/target/sparc/translate.c</div>\r\n" - "<div>@@ -2840,7 +2840,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)</div>\r\n" - "<div> default:</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 r_asi = tcg_const_i32(da.asi);</div>\r\n" - "<div>- TCGv_i32 r_mop = tcg_const_i32(MO_Q);</div>\r\n" - "<div>+ TCGv_i32 r_mop = tcg_const_i32(MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> save_state(dc);</div>\r\n" - "<div> gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);</div>\r\n" - "<div>@@ -2896,7 +2896,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,</div>\r\n" - "<div> default:</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 r_asi = tcg_const_i32(da.asi);</div>\r\n" - "<div>- TCGv_i32 r_mop = tcg_const_i32(MO_Q);</div>\r\n" - "<div>+ TCGv_i32 r_mop = tcg_const_i32(MO_UQ);</div>\r\n" - "<div> </div>\r\n" - "<div> save_state(dc);</div>\r\n" - "<div> gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);</div>\r\n" - "<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>index dc4fd21..d14afa9 100644</div>\r\n" - "<div>--- a/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>@@ -432,12 +432,12 @@ typedef enum {</div>\r\n" - "<div> I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_UW << 30,</div>\r\n" - "<div> I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_UL << 30,</div>\r\n" - "<div>- I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,</div>\r\n" - "<div>+ I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_UQ << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_UW << 30,</div>\r\n" - "<div> I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_UL << 30,</div>\r\n" - "<div>- I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,</div>\r\n" - "<div>+ I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_UQ << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_UB << 30,</div>\r\n" - "<div> I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_UW << 30,</div>\r\n" - "<div>@@ -449,8 +449,8 @@ typedef enum {</div>\r\n" - "<div> I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_UL << 30,</div>\r\n" - "<div> I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_UL << 30,</div>\r\n" - "<div> </div>\r\n" - "<div>- I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,</div>\r\n" - "<div>- I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,</div>\r\n" - "<div>+ I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_UQ << 30,</div>\r\n" - "<div>+ I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_UQ << 30,</div>\r\n" - "<div> </div>\r\n" - "<div> I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,</div>\r\n" - "<div> I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,</div>\r\n" - "<div>@@ -1595,7 +1595,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> if (opc & MO_SIGN) {</div>\r\n" - "<div> tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0);</div>\r\n" - "<div>+ tcg_out_mov(s, size == MO_UQ, lb->datalo_reg, TCG_REG_X0);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_out_goto(s, lb->raddr);</div>\r\n" - "<div>@@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);</div>\r\n" - "<div> tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);</div>\r\n" - "<div>- tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);</div>\r\n" - "<div>+ tcg_out_mov(s, size == MO_UQ, TCG_REG_X2, lb->datalo_reg);</div>\r\n" - "<div> tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi);</div>\r\n" - "<div> tcg_out_adr(s, TCG_REG_X4, lb->raddr);</div>\r\n" - "<div> tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);</div>\r\n" - "<div>@@ -1754,7 +1754,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_rev64(s, data_r, data_r);</div>\r\n" - "<div>@@ -1789,7 +1789,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (bswap && data_r != TCG_REG_XZR) {</div>\r\n" - "<div> tcg_out_rev64(s, TCG_REG_TMP, data_r);</div>\r\n" - "<div> data_r = TCG_REG_TMP;</div>\r\n" - "<div>@@ -1838,7 +1838,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div>\r\n" - "<div> tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);</div>\r\n" - "<div> tcg_out_qemu_st_direct(s, memop, data_reg,</div>\r\n" - "<div> TCG_REG_X1, otype, addr_reg);</div>\r\n" - "<div>- add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,</div>\r\n" - "<div>+ add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE) == MO_UQ,</div>\r\n" - "<div> data_reg, addr_reg, s->code_ptr, label_ptr);</div>\r\n" - "<div> #else /* !CONFIG_SOFTMMU */</div>\r\n" - "<div> if (USE_GUEST_BASE) {</div>\r\n" - "<div>@@ -2506,7 +2506,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> case INDEX_op_smin_vec:</div>\r\n" - "<div> case INDEX_op_umax_vec:</div>\r\n" - "<div> case INDEX_op_umin_vec:</div>\r\n" - "<div>- return vece < MO_64;</div>\r\n" - "<div>+ return vece < MO_UQ;</div>\r\n" - "<div> </div>\r\n" - "<div> default:</div>\r\n" - "<div> return 0;</div>\r\n" - "<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>index 05560a2..70eeb8a 100644</div>\r\n" - "<div>--- a/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>@@ -1389,7 +1389,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> default:</div>\r\n" - "<div> tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (datalo != TCG_REG_R1) {</div>\r\n" - "<div> tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);</div>\r\n" - "<div> tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);</div>\r\n" - "<div>@@ -1439,7 +1439,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> default:</div>\r\n" - "<div> argreg = tcg_out_arg_reg32(s, argreg, datalo);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi);</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -1487,7 +1487,7 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div> tcg_out_bswap32(s, COND_AL, datalo, datalo);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGReg dl = (bswap ? datahi : datalo);</div>\r\n" - "<div> TCGReg dh = (bswap ? datalo : datahi);</div>\r\n" - "<div>@@ -1548,7 +1548,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div> tcg_out_bswap32(s, COND_AL, datalo, datalo);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGReg dl = (bswap ? datahi : datalo);</div>\r\n" - "<div> TCGReg dh = (bswap ? datalo : datahi);</div>\r\n" - "<div>@@ -1641,7 +1641,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div>\r\n" - "<div> tcg_out_st32_r(s, cond, datalo, addrlo, addend);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> /* Avoid strd for user-only emulation, to handle unaligned. */</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_bswap32(s, cond, TCG_REG_R0, datahi);</div>\r\n" - "<div>@@ -1686,7 +1686,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div> tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> /* Avoid strd for user-only emulation, to handle unaligned. */</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi);</div>\r\n" - "<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>index 93e4c63..3a73334 100644</div>\r\n" - "<div>--- a/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>@@ -902,7 +902,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> /* imm8 operand: all output lanes selected from input lane 0. */</div>\r\n" - "<div> tcg_out8(s, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -921,7 +921,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,</div>\r\n" - "<div> r, 0, base, offset);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> switch (vece) {</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset);</div>\r\n" - "<div> break;</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div>@@ -1868,7 +1868,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);</div>\r\n" - "<div> } else if (data_reg == TCG_REG_EDX) {</div>\r\n" - "<div>@@ -1923,7 +1923,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs);</div>\r\n" - "<div> ofs += 4;</div>\r\n" - "<div> </div>\r\n" - "<div>- if (s_bits == MO_64) {</div>\r\n" - "<div>+ if (s_bits == MO_UQ) {</div>\r\n" - "<div> tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs);</div>\r\n" - "<div> ofs += 4;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -1937,7 +1937,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);</div>\r\n" - "<div> /* The second argument is already loaded with addrlo. */</div>\r\n" - "<div>- tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),</div>\r\n" - "<div>+ tcg_out_mov(s, (s_bits == MO_UQ ? TCG_TYPE_I64 : TCG_TYPE_I32),</div>\r\n" - "<div> tcg_target_call_iarg_regs[2], l->datalo_reg);</div>\r\n" - "<div> tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2060,7 +2060,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,</div>\r\n" - "<div> base, index, 0, ofs);</div>\r\n" - "<div>@@ -2181,7 +2181,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> if (bswap) {</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);</div>\r\n" - "<div>@@ -2755,7 +2755,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ</div>\r\n" - "<div> };</div>\r\n" - "<div> static int const sarv_insn[4] = {</div>\r\n" - "<div>- /* TODO: AVX512 adds support for MO_UW, MO_64. */</div>\r\n" - "<div>+ /* TODO: AVX512 adds support for MO_UW, MO_UQ. */</div>\r\n" - "<div> OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2</div>\r\n" - "<div> };</div>\r\n" - "<div> static int const shls_insn[4] = {</div>\r\n" - "<div>@@ -2768,7 +2768,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2</div>\r\n" - "<div> };</div>\r\n" - "<div> static int const abs_insn[4] = {</div>\r\n" - "<div>- /* TODO: AVX512 adds support for MO_64. */</div>\r\n" - "<div>+ /* TODO: AVX512 adds support for MO_UQ. */</div>\r\n" - "<div> OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2898,7 +2898,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,</div>\r\n" - "<div> sub = 2;</div>\r\n" - "<div> goto gen_shift;</div>\r\n" - "<div> case INDEX_op_sari_vec:</div>\r\n" - "<div>- tcg_debug_assert(vece != MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece != MO_UQ);</div>\r\n" - "<div> sub = 4;</div>\r\n" - "<div> gen_shift:</div>\r\n" - "<div> tcg_debug_assert(vece != MO_UB);</div>\r\n" - "<div>@@ -3281,9 +3281,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> if (vece == MO_UB) {</div>\r\n" - "<div> return -1;</div>\r\n" - "<div> }</div>\r\n" - "<div>- /* We can emulate this for MO_64, but it does not pay off</div>\r\n" - "<div>- unless we're producing at least 4 values. */</div>\r\n" - "<div>- if (vece == MO_64) {</div>\r\n" - "<div>+ /*</div>\r\n" - "<div>+ * We can emulate this for MO_UQ, but it does not pay off</div>\r\n" - "<div>+ * unless we're producing at least 4 values.</div>\r\n" - "<div>+ */</div>\r\n" - "<div>+ if (vece == MO_UQ) {</div>\r\n" - "<div> return type >= TCG_TYPE_V256 ? -1 : 0;</div>\r\n" - "<div> }</div>\r\n" - "<div> return 1;</div>\r\n" - "<div>@@ -3305,7 +3307,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)</div>\r\n" - "<div> /* We can expand the operation for MO_UB. */</div>\r\n" - "<div> return -1;</div>\r\n" - "<div> }</div>\r\n" - "<div>- if (vece == MO_64) {</div>\r\n" - "<div>+ if (vece == MO_UQ) {</div>\r\n" - "<div> return 0;</div>\r\n" - "<div> }</div>\r\n" - "<div> return 1;</div>\r\n" - "<div>@@ -3389,7 +3391,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div>\r\n" - "<div> tcg_temp_free_vec(t2);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (imm <= 32) {</div>\r\n" - "<div> /* We can emulate a small sign extend by performing an arithmetic</div>\r\n" - "<div> * 32-bit shift and overwriting the high half of a 64-bit logical</div>\r\n" - "<div>@@ -3397,7 +3399,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div>\r\n" - "<div> */</div>\r\n" - "<div> t1 = tcg_temp_new_vec(type);</div>\r\n" - "<div> tcg_gen_sari_vec(MO_UL, t1, v1, imm);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_64, v0, v1, imm);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UQ, v0, v1, imm);</div>\r\n" - "<div> vec_gen_4(INDEX_op_x86_blend_vec, type, MO_UL,</div>\r\n" - "<div> tcgv_vec_arg(v0), tcgv_vec_arg(v0),</div>\r\n" - "<div> tcgv_vec_arg(t1), 0xaa);</div>\r\n" - "<div>@@ -3407,10 +3409,10 @@ static void expand_vec_sari(TCGType type, unsigned vece,</div>\r\n" - "<div> * the sign-extend, shift and merge.</div>\r\n" - "<div> */</div>\r\n" - "<div> t1 = tcg_const_zeros_vec(type);</div>\r\n" - "<div>- tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);</div>\r\n" - "<div>- tcg_gen_shri_vec(MO_64, v0, v1, imm);</div>\r\n" - "<div>- tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);</div>\r\n" - "<div>- tcg_gen_or_vec(MO_64, v0, v0, t1);</div>\r\n" - "<div>+ tcg_gen_cmp_vec(TCG_COND_GT, MO_UQ, t1, t1, v1);</div>\r\n" - "<div>+ tcg_gen_shri_vec(MO_UQ, v0, v1, imm);</div>\r\n" - "<div>+ tcg_gen_shli_vec(MO_UQ, t1, t1, 64 - imm);</div>\r\n" - "<div>+ tcg_gen_or_vec(MO_UQ, v0, v0, t1);</div>\r\n" - "<div> tcg_temp_free_vec(t1);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>index a78fe87..ef31fc8 100644</div>\r\n" - "<div>--- a/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>@@ -1336,7 +1336,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);</div>\r\n" - "<div> </div>\r\n" - "<div> v0 = l->datalo_reg;</div>\r\n" - "<div>- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {</div>\r\n" - "<div>+ if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_UQ) {</div>\r\n" - "<div> /* We eliminated V0 from the possible output registers, so it</div>\r\n" - "<div> cannot be clobbered here. So we must move V1 first. */</div>\r\n" - "<div> if (MIPS_BE) {</div>\r\n" - "<div>@@ -1389,7 +1389,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 32) {</div>\r\n" - "<div> i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -1470,7 +1470,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> case MO_SL:</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_LW, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q | MO_BSWAP:</div>\r\n" - "<div>+ case MO_UQ | MO_BSWAP:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> if (use_mips32r2_instructions) {</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_LD, lo, base, 0);</div>\r\n" - "<div>@@ -1499,7 +1499,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> /* Prefer to load from offset 0 first, but allow for overlap. */</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_LD, lo, base, 0);</div>\r\n" - "<div>@@ -1587,7 +1587,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SW, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_64 | MO_BSWAP:</div>\r\n" - "<div>+ case MO_UQ | MO_BSWAP:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> tcg_out_bswap64(s, TCG_TMP3, lo);</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);</div>\r\n" - "<div>@@ -1605,7 +1605,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_SD, lo, base, 0);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>index 835336a..13a2437 100644</div>\r\n" - "<div>--- a/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>@@ -1445,24 +1445,24 @@ static const uint32_t qemu_ldx_opc[16] = {</div>\r\n" - "<div> [MO_UB] = LBZX,</div>\r\n" - "<div> [MO_UW] = LHZX,</div>\r\n" - "<div> [MO_UL] = LWZX,</div>\r\n" - "<div>- [MO_Q] = LDX,</div>\r\n" - "<div>+ [MO_UQ] = LDX,</div>\r\n" - "<div> [MO_SW] = LHAX,</div>\r\n" - "<div> [MO_SL] = LWAX,</div>\r\n" - "<div> [MO_BSWAP | MO_UB] = LBZX,</div>\r\n" - "<div> [MO_BSWAP | MO_UW] = LHBRX,</div>\r\n" - "<div> [MO_BSWAP | MO_UL] = LWBRX,</div>\r\n" - "<div>- [MO_BSWAP | MO_Q] = LDBRX,</div>\r\n" - "<div>+ [MO_BSWAP | MO_UQ] = LDBRX,</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static const uint32_t qemu_stx_opc[16] = {</div>\r\n" - "<div> [MO_UB] = STBX,</div>\r\n" - "<div> [MO_UW] = STHX,</div>\r\n" - "<div> [MO_UL] = STWX,</div>\r\n" - "<div>- [MO_Q] = STDX,</div>\r\n" - "<div>+ [MO_UQ] = STDX,</div>\r\n" - "<div> [MO_BSWAP | MO_UB] = STBX,</div>\r\n" - "<div> [MO_BSWAP | MO_UW] = STHBRX,</div>\r\n" - "<div> [MO_BSWAP | MO_UL] = STWBRX,</div>\r\n" - "<div>- [MO_BSWAP | MO_Q] = STDBRX,</div>\r\n" - "<div>+ [MO_BSWAP | MO_UQ] = STDBRX,</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> static const uint32_t qemu_exts_opc[4] = {</div>\r\n" - "<div>@@ -1663,7 +1663,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> </div>\r\n" - "<div> lo = lb->datalo_reg;</div>\r\n" - "<div> hi = lb->datahi_reg;</div>\r\n" - "<div>- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {</div>\r\n" - "<div>+ if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_UQ) {</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);</div>\r\n" - "<div> } else if (opc & MO_SIGN) {</div>\r\n" - "<div>@@ -1708,7 +1708,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> hi = lb->datahi_reg;</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 32) {</div>\r\n" - "<div> switch (s_bits) {</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> #ifdef TCG_TARGET_CALL_ALIGN_ARGS</div>\r\n" - "<div> arg |= 1;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -1722,7 +1722,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- if (s_bits == MO_64) {</div>\r\n" - "<div>+ if (s_bits == MO_UQ) {</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));</div>\r\n" - "<div>@@ -1775,7 +1775,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> }</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>- if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {</div>\r\n" - "<div>+ if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_UQ) {</div>\r\n" - "<div> if (opc & MO_BSWAP) {</div>\r\n" - "<div> tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));</div>\r\n" - "<div> tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));</div>\r\n" - "<div>@@ -1850,7 +1850,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> }</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>- if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {</div>\r\n" - "<div>+ if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_UQ) {</div>\r\n" - "<div> if (opc & MO_BSWAP) {</div>\r\n" - "<div> tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));</div>\r\n" - "<div> tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));</div>\r\n" - "<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>index 1905986..90363df 100644</div>\r\n" - "<div>--- a/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>@@ -1068,7 +1068,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);</div>\r\n" - "<div>- tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);</div>\r\n" - "<div>+ tcg_out_mov(s, (opc & MO_SIZE) == MO_UQ, l->datalo_reg, a0);</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_out_goto(s, l->raddr);</div>\r\n" - "<div> return true;</div>\r\n" - "<div>@@ -1150,7 +1150,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> case MO_SL:</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_LW, lo, base, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> /* Prefer to load from offset 0 first, but allow for overlap. */</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> tcg_out_opc_imm(s, OPC_LD, lo, base, 0);</div>\r\n" - "<div>@@ -1225,7 +1225,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tcg_out_opc_store(s, OPC_SW, base, lo, 0);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> tcg_out_opc_store(s, OPC_SD, base, lo, 0);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c</div>\r\n" - "<div>index fe42939..db1102e 100644</div>\r\n" - "<div>--- a/tcg/s390/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/s390/tcg-target.inc.c</div>\r\n" - "<div>@@ -1477,10 +1477,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div>\r\n" - "<div> tcg_out_insn(s, RXY, LGF, data, base, index, disp);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_Q | MO_BSWAP:</div>\r\n" - "<div>+ case MO_UQ | MO_BSWAP:</div>\r\n" - "<div> tcg_out_insn(s, RXY, LRVG, data, base, index, disp);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_out_insn(s, RXY, LG, data, base, index, disp);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1523,10 +1523,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>- case MO_Q | MO_BSWAP:</div>\r\n" - "<div>+ case MO_UQ | MO_BSWAP:</div>\r\n" - "<div> tcg_out_insn(s, RXY, STRVG, data, base, index, disp);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_out_insn(s, RXY, STG, data, base, index, disp);</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1660,7 +1660,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tgen_ext32u(s, TCG_REG_R4, data_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_Q:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>index ac0d3a3..7c50118 100644</div>\r\n" - "<div>--- a/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>@@ -894,7 +894,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)</div>\r\n" - "<div> tcg_out_arith(s, r, r, 0, SHIFT_SRL);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> break;</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -977,7 +977,7 @@ static void build_trampolines(TCGContext *s)</div>\r\n" - "<div> } else {</div>\r\n" - "<div> ra += 1;</div>\r\n" - "<div> }</div>\r\n" - "<div>- if ((i & MO_SIZE) == MO_64) {</div>\r\n" - "<div>+ if ((i & MO_SIZE) == MO_UQ) {</div>\r\n" - "<div> /* Install the high part of the data. */</div>\r\n" - "<div> tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);</div>\r\n" - "<div> ra += 2;</div>\r\n" - "<div>@@ -1217,7 +1217,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);</div>\r\n" - "<div> }</div>\r\n" - "<div> } else {</div>\r\n" - "<div>- if ((memop & MO_SIZE) == MO_64) {</div>\r\n" - "<div>+ if ((memop & MO_SIZE) == MO_UQ) {</div>\r\n" - "<div> tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);</div>\r\n" - "<div> tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);</div>\r\n" - "<div> tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);</div>\r\n" - "<div>@@ -1274,7 +1274,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,</div>\r\n" - "<div> param++;</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);</div>\r\n" - "<div>- if (!SPARC64 && (memop & MO_SIZE) == MO_64) {</div>\r\n" - "<div>+ if (!SPARC64 && (memop & MO_SIZE) == MO_UQ) {</div>\r\n" - "<div> /* Skip the high-part; we'll perform the extract in the trampoline. */</div>\r\n" - "<div> param++;</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>index e63622c..0c0eea5 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-gvec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-gvec.c</div>\r\n" - "<div>@@ -312,7 +312,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)</div>\r\n" - "<div> return 0x0001000100010001ull * (uint16_t)c;</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> return 0x0000000100000001ull * (uint32_t)c;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> return c;</div>\r\n" - "<div> default:</div>\r\n" - "<div> g_assert_not_reached();</div>\r\n" - "<div>@@ -352,7 +352,7 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)</div>\r\n" - "<div> case MO_UL:</div>\r\n" - "<div> tcg_gen_deposit_i64(out, in, in, 32, 32);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_mov_i64(out, in);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -443,7 +443,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> TCGv_ptr t_ptr;</div>\r\n" - "<div> uint32_t i;</div>\r\n" - "<div> </div>\r\n" - "<div>- assert(vece <= (in_32 ? MO_UL : MO_64));</div>\r\n" - "<div>+ assert(vece <= (in_32 ? MO_UL : MO_UQ));</div>\r\n" - "<div> assert(in_32 == NULL || in_64 == NULL);</div>\r\n" - "<div> </div>\r\n" - "<div> /* If we're storing 0, expand oprsz to maxsz. */</div>\r\n" - "<div>@@ -459,7 +459,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> */</div>\r\n" - "<div> type = choose_vector_type(NULL, vece, oprsz,</div>\r\n" - "<div> (TCG_TARGET_REG_BITS == 64 && in_32 == NULL</div>\r\n" - "<div>- && (in_64 == NULL || vece == MO_64)));</div>\r\n" - "<div>+ && (in_64 == NULL || vece == MO_UQ)));</div>\r\n" - "<div> if (type != 0) {</div>\r\n" - "<div> TCGv_vec t_vec = tcg_temp_new_vec(type);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -502,7 +502,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> /* For 64-bit hosts, use 64-bit constants for "simple" constants</div>\r\n" - "<div> or when we'd need too many 32-bit stores, or when a 64-bit</div>\r\n" - "<div> constant is really required. */</div>\r\n" - "<div>- if (vece == MO_64</div>\r\n" - "<div>+ if (vece == MO_UQ</div>\r\n" - "<div> || (TCG_TARGET_REG_BITS == 64</div>\r\n" - "<div> && (in_c == 0 || in_c == -1</div>\r\n" - "<div> || !check_size_impl(oprsz, 4)))) {</div>\r\n" - "<div>@@ -534,7 +534,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);</div>\r\n" - "<div> t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));</div>\r\n" - "<div> </div>\r\n" - "<div>- if (vece == MO_64) {</div>\r\n" - "<div>+ if (vece == MO_UQ) {</div>\r\n" - "<div> if (in_64) {</div>\r\n" - "<div> gen_helper_gvec_dup64(t_ptr, t_desc, in_64);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -1438,7 +1438,7 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> uint32_t maxsz, TCGv_i64 in)</div>\r\n" - "<div> {</div>\r\n" - "<div> check_size_align(oprsz, maxsz, dofs);</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1446,7 +1446,7 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> uint32_t oprsz, uint32_t maxsz)</div>\r\n" - "<div> {</div>\r\n" - "<div> check_size_align(oprsz, maxsz, dofs);</div>\r\n" - "<div>- if (vece <= MO_64) {</div>\r\n" - "<div>+ if (vece <= MO_UQ) {</div>\r\n" - "<div> TCGType type = choose_vector_type(NULL, vece, oprsz, 0);</div>\r\n" - "<div> if (type != 0) {</div>\r\n" - "<div> TCGv_vec t_vec = tcg_temp_new_vec(type);</div>\r\n" - "<div>@@ -1512,7 +1512,7 @@ void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div> uint32_t maxsz, uint64_t x)</div>\r\n" - "<div> {</div>\r\n" - "<div> check_size_align(oprsz, maxsz, dofs);</div>\r\n" - "<div>- do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div>+ do_dup(MO_UQ, dofs, oprsz, maxsz, NULL, NULL, x);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,</div>\r\n" - "<div>@@ -1624,10 +1624,10 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_add64,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1655,10 +1655,10 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_adds64,</div>\r\n" - "<div> .opt_opc = vecop_list_add,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1696,10 +1696,10 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_subs64,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1775,10 +1775,10 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_sub64,</div>\r\n" - "<div> .opt_opc = vecop_list_sub,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1806,10 +1806,10 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_mul64,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1835,10 +1835,10 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_muls64,</div>\r\n" - "<div> .opt_opc = vecop_list_mul,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1870,9 +1870,9 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_ssadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ssadd64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1896,9 +1896,9 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> { .fniv = tcg_gen_sssub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_sssub64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1940,9 +1940,9 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_usadd_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_usadd64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 }</div>\r\n" - "<div>+ .vece = MO_UQ }</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1984,9 +1984,9 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_ussub_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ussub64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 }</div>\r\n" - "<div>+ .vece = MO_UQ }</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2012,9 +2012,9 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_smin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smin64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 }</div>\r\n" - "<div>+ .vece = MO_UQ }</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2040,9 +2040,9 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_umin_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umin64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 }</div>\r\n" - "<div>+ .vece = MO_UQ }</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2068,9 +2068,9 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_smax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_smax64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 }</div>\r\n" - "<div>+ .vece = MO_UQ }</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2096,9 +2096,9 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fniv = tcg_gen_umax_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_umax64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div>- .vece = MO_64 }</div>\r\n" - "<div>+ .vece = MO_UQ }</div>\r\n" - "<div> };</div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2171,10 +2171,10 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_neg64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2234,10 +2234,10 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_abs64,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2382,7 +2382,7 @@ static const GVecGen2s gop_ands = {</div>\r\n" - "<div> .fniv = tcg_gen_and_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ands,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64</div>\r\n" - "<div>+ .vece = MO_UQ</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div>@@ -2407,7 +2407,7 @@ static const GVecGen2s gop_xors = {</div>\r\n" - "<div> .fniv = tcg_gen_xor_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_xors,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64</div>\r\n" - "<div>+ .vece = MO_UQ</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div>@@ -2432,7 +2432,7 @@ static const GVecGen2s gop_ors = {</div>\r\n" - "<div> .fniv = tcg_gen_or_vec,</div>\r\n" - "<div> .fno = gen_helper_gvec_ors,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64</div>\r\n" - "<div>+ .vece = MO_UQ</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div>@@ -2491,10 +2491,10 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl64i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_debug_assert(shift >= 0 && shift < (8 << vece));</div>\r\n" - "<div> if (shift == 0) {</div>\r\n" - "<div> tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);</div>\r\n" - "<div>@@ -2542,10 +2542,10 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr64i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_debug_assert(shift >= 0 && shift < (8 << vece));</div>\r\n" - "<div> if (shift == 0) {</div>\r\n" - "<div> tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);</div>\r\n" - "<div>@@ -2607,10 +2607,10 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar64i,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_debug_assert(shift >= 0 && shift < (8 << vece));</div>\r\n" - "<div> if (shift == 0) {</div>\r\n" - "<div> tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);</div>\r\n" - "<div>@@ -2660,7 +2660,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div>\r\n" - "<div> check_overlap_2(dofs, aofs, maxsz);</div>\r\n" - "<div> </div>\r\n" - "<div> /* If the backend has a scalar expansion, great. */</div>\r\n" - "<div>- type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64);</div>\r\n" - "<div>+ type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_UQ);</div>\r\n" - "<div> if (type) {</div>\r\n" - "<div> const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);</div>\r\n" - "<div> switch (type) {</div>\r\n" - "<div>@@ -2692,15 +2692,15 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* If the backend supports variable vector shifts, also cool. */</div>\r\n" - "<div>- type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64);</div>\r\n" - "<div>+ type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_UQ);</div>\r\n" - "<div> if (type) {</div>\r\n" - "<div> const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);</div>\r\n" - "<div> TCGv_vec v_shift = tcg_temp_new_vec(type);</div>\r\n" - "<div> </div>\r\n" - "<div>- if (vece == MO_64) {</div>\r\n" - "<div>+ if (vece == MO_UQ) {</div>\r\n" - "<div> TCGv_i64 sh64 = tcg_temp_new_i64();</div>\r\n" - "<div> tcg_gen_extu_i32_i64(sh64, shift);</div>\r\n" - "<div>- tcg_gen_dup_i64_vec(MO_64, v_shift, sh64);</div>\r\n" - "<div>+ tcg_gen_dup_i64_vec(MO_UQ, v_shift, sh64);</div>\r\n" - "<div> tcg_temp_free_i64(sh64);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_dup_i32_vec(vece, v_shift, shift);</div>\r\n" - "<div>@@ -2738,7 +2738,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,</div>\r\n" - "<div> /* Otherwise fall back to integral... */</div>\r\n" - "<div> if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div>\r\n" - "<div> expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4);</div>\r\n" - "<div>- } else if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div>\r\n" - "<div>+ } else if (vece == MO_UQ && check_size_impl(oprsz, 8)) {</div>\r\n" - "<div> TCGv_i64 sh64 = tcg_temp_new_i64();</div>\r\n" - "<div> tcg_gen_extu_i32_i64(sh64, shift);</div>\r\n" - "<div> expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8);</div>\r\n" - "<div>@@ -2785,7 +2785,7 @@ void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .v_list = { INDEX_op_shlv_vec, 0 },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2807,7 +2807,7 @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .v_list = { INDEX_op_shrv_vec, 0 },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2829,7 +2829,7 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .v_list = { INDEX_op_sarv_vec, 0 },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2895,10 +2895,10 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_shl64v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2958,10 +2958,10 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_shr64v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3021,10 +3021,10 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,</div>\r\n" - "<div> .fno = gen_helper_gvec_sar64v,</div>\r\n" - "<div> .opt_opc = vecop_list,</div>\r\n" - "<div> .prefer_i64 = TCG_TARGET_REG_BITS == 64,</div>\r\n" - "<div>- .vece = MO_64 },</div>\r\n" - "<div>+ .vece = MO_UQ },</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>- tcg_debug_assert(vece <= MO_64);</div>\r\n" - "<div>+ tcg_debug_assert(vece <= MO_UQ);</div>\r\n" - "<div> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3140,7 +3140,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div>\r\n" - "<div> */</div>\r\n" - "<div> hold_list = tcg_swap_vecop_list(cmp_list);</div>\r\n" - "<div> type = choose_vector_type(cmp_list, vece, oprsz,</div>\r\n" - "<div>- TCG_TARGET_REG_BITS == 64 && vece == MO_64);</div>\r\n" - "<div>+ TCG_TARGET_REG_BITS == 64 && vece == MO_UQ);</div>\r\n" - "<div> switch (type) {</div>\r\n" - "<div> case TCG_TYPE_V256:</div>\r\n" - "<div> /* Recall that ARM SVE allows vector sizes that are not a</div>\r\n" - "<div>@@ -3166,7 +3166,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,</div>\r\n" - "<div> break;</div>\r\n" - "<div> </div>\r\n" - "<div> case 0:</div>\r\n" - "<div>- if (vece == MO_64 && check_size_impl(oprsz, 8)) {</div>\r\n" - "<div>+ if (vece == MO_UQ && check_size_impl(oprsz, 8)) {</div>\r\n" - "<div> expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);</div>\r\n" - "<div> } else if (vece == MO_UL && check_size_impl(oprsz, 4)) {</div>\r\n" - "<div> expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);</div>\r\n" - "<div>diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c</div>\r\n" - "<div>index ff723ab..e8aea38 100644</div>\r\n" - "<div>--- a/tcg/tcg-op-vec.c</div>\r\n" - "<div>+++ b/tcg/tcg-op-vec.c</div>\r\n" - "<div>@@ -216,7 +216,7 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_UL)</div>\r\n" - "<div>+#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_UQ : MO_UL)</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -255,10 +255,10 @@ void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {</div>\r\n" - "<div> do_dupi_vec(r, MO_UL, a);</div>\r\n" - "<div> } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {</div>\r\n" - "<div>- do_dupi_vec(r, MO_64, a);</div>\r\n" - "<div>+ do_dupi_vec(r, MO_UQ, a);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> TCGv_i64 c = tcg_const_i64(a);</div>\r\n" - "<div>- tcg_gen_dup_i64_vec(MO_64, r, c);</div>\r\n" - "<div>+ tcg_gen_dup_i64_vec(MO_UQ, r, c);</div>\r\n" - "<div> tcg_temp_free_i64(c);</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -292,10 +292,10 @@ void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)</div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 64) {</div>\r\n" - "<div> TCGArg ai = tcgv_i64_arg(a);</div>\r\n" - "<div> vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);</div>\r\n" - "<div>- } else if (vece == MO_64) {</div>\r\n" - "<div>+ } else if (vece == MO_UQ) {</div>\r\n" - "<div> TCGArg al = tcgv_i32_arg(TCGV_LOW(a));</div>\r\n" - "<div> TCGArg ah = tcgv_i32_arg(TCGV_HIGH(a));</div>\r\n" - "<div>- vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah);</div>\r\n" - "<div>+ vec_gen_3(INDEX_op_dup2_vec, type, MO_UQ, ri, al, ah);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> TCGArg ai = tcgv_i32_arg(TCGV_LOW(a));</div>\r\n" - "<div> vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);</div>\r\n" - "<div>@@ -709,10 +709,10 @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,</div>\r\n" - "<div> } else {</div>\r\n" - "<div> TCGv_vec vec_s = tcg_temp_new_vec(type);</div>\r\n" - "<div> </div>\r\n" - "<div>- if (vece == MO_64) {</div>\r\n" - "<div>+ if (vece == MO_UQ) {</div>\r\n" - "<div> TCGv_i64 s64 = tcg_temp_new_i64();</div>\r\n" - "<div> tcg_gen_extu_i32_i64(s64, s);</div>\r\n" - "<div>- tcg_gen_dup_i64_vec(MO_64, vec_s, s64);</div>\r\n" - "<div>+ tcg_gen_dup_i64_vec(MO_UQ, vec_s, s64);</div>\r\n" - "<div> tcg_temp_free_i64(s64);</div>\r\n" - "<div> } else {</div>\r\n" - "<div> tcg_gen_dup_i32_vec(vece, vec_s, s);</div>\r\n" - "<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div>\r\n" - "<div>index 447683d..a9f3e13 100644</div>\r\n" - "<div>--- a/tcg/tcg-op.c</div>\r\n" - "<div>+++ b/tcg/tcg-op.c</div>\r\n" - "<div>@@ -2730,7 +2730,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div>\r\n" - "<div> op &= ~MO_SIGN;</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> if (!is64) {</div>\r\n" - "<div> tcg_abort();</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2862,7 +2862,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOp orig_memop;</div>\r\n" - "<div> </div>\r\n" - "<div>- if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {</div>\r\n" - "<div>+ if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_UQ) {</div>\r\n" - "<div> tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);</div>\r\n" - "<div> if (memop & MO_SIGN) {</div>\r\n" - "<div> tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);</div>\r\n" - "<div>@@ -2881,7 +2881,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {</div>\r\n" - "<div> memop &= ~MO_BSWAP;</div>\r\n" - "<div> /* The bswap primitive requires zero-extended input. */</div>\r\n" - "<div>- if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) {</div>\r\n" - "<div>+ if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_UQ) {</div>\r\n" - "<div> memop &= ~MO_SIGN;</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2902,7 +2902,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> tcg_gen_ext32s_i64(val, val);</div>\r\n" - "<div> }</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_bswap64_i64(val, val);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -2915,7 +2915,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 swap = NULL;</div>\r\n" - "<div> </div>\r\n" - "<div>- if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {</div>\r\n" - "<div>+ if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_UQ) {</div>\r\n" - "<div> tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2936,7 +2936,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> tcg_gen_ext32u_i64(swap, val);</div>\r\n" - "<div> tcg_gen_bswap32_i64(swap, swap);</div>\r\n" - "<div> break;</div>\r\n" - "<div>- case MO_64:</div>\r\n" - "<div>+ case MO_UQ:</div>\r\n" - "<div> tcg_gen_bswap64_i64(swap, val);</div>\r\n" - "<div> break;</div>\r\n" - "<div> default:</div>\r\n" - "<div>@@ -3029,8 +3029,8 @@ static void * const table_cmpxchg[16] = {</div>\r\n" - "<div> [MO_UW | MO_BE] = gen_helper_atomic_cmpxchgw_be,</div>\r\n" - "<div> [MO_UL | MO_LE] = gen_helper_atomic_cmpxchgl_le,</div>\r\n" - "<div> [MO_UL | MO_BE] = gen_helper_atomic_cmpxchgl_be,</div>\r\n" - "<div>- WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div>\r\n" - "<div>- WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be)</div>\r\n" - "<div>+ WITH_ATOMIC64([MO_UQ | MO_LE] = gen_helper_atomic_cmpxchgq_le)</div>\r\n" - "<div>+ WITH_ATOMIC64([MO_UQ | MO_BE] = gen_helper_atomic_cmpxchgq_be)</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,</div>\r\n" - "<div>@@ -3099,7 +3099,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,</div>\r\n" - "<div> tcg_gen_mov_i64(retv, t1);</div>\r\n" - "<div> }</div>\r\n" - "<div> tcg_temp_free_i64(t1);</div>\r\n" - "<div>- } else if ((memop & MO_SIZE) == MO_64) {</div>\r\n" - "<div>+ } else if ((memop & MO_SIZE) == MO_UQ) {</div>\r\n" - "<div> #ifdef CONFIG_ATOMIC64</div>\r\n" - "<div> gen_atomic_cx_i64 gen;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3207,7 +3207,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div>\r\n" - "<div> {</div>\r\n" - "<div> memop = tcg_canonicalize_memop(memop, 1, 0);</div>\r\n" - "<div> </div>\r\n" - "<div>- if ((memop & MO_SIZE) == MO_64) {</div>\r\n" - "<div>+ if ((memop & MO_SIZE) == MO_UQ) {</div>\r\n" - "<div> #ifdef CONFIG_ATOMIC64</div>\r\n" - "<div> gen_atomic_op_i64 gen;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3253,8 +3253,8 @@ static void * const table_##NAME[16] = { \\</div>\r\n" - "<div> [MO_UW | MO_BE] = gen_helper_atomic_##NAME##w_be, \\</div>\r\n" - "<div> [MO_UL | MO_LE] = gen_helper_atomic_##NAME##l_le, \\</div>\r\n" - "<div> [MO_UL | MO_BE] = gen_helper_atomic_##NAME##l_be, \\</div>\r\n" - "<div>- WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \\</div>\r\n" - "<div>- WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \\</div>\r\n" - "<div>+ WITH_ATOMIC64([MO_UQ | MO_LE] = gen_helper_atomic_##NAME##q_le) \\</div>\r\n" - "<div>+ WITH_ATOMIC64([MO_UQ | MO_BE] = gen_helper_atomic_##NAME##q_be) \\</div>\r\n" - "<div> }; \\</div>\r\n" - "<div> void tcg_gen_atomic_##NAME##_i32 \\</div>\r\n" - "<div> (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \\</div>\r\n" - "<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div>\r\n" - "<div>index 4b6ee89..63e9897 100644</div>\r\n" - "<div>--- a/tcg/tcg.h</div>\r\n" - "<div>+++ b/tcg/tcg.h</div>\r\n" - "<div>@@ -371,28 +371,29 @@ typedef enum TCGMemOp {</div>\r\n" - "<div> MO_UB = MO_8,</div>\r\n" - "<div> MO_UW = MO_16,</div>\r\n" - "<div> MO_UL = MO_32,</div>\r\n" - "<div>+ MO_UQ = MO_64,</div>\r\n" - "<div> MO_SB = MO_SIGN | MO_8,</div>\r\n" - "<div> MO_SW = MO_SIGN | MO_16,</div>\r\n" - "<div> MO_SL = MO_SIGN | MO_32,</div>\r\n" - "<div>- MO_Q = MO_64,</div>\r\n" - "<div>+ MO_SQ = MO_SIGN | MO_64,</div>\r\n" - "<div> </div>\r\n" - "<div> MO_LEUW = MO_LE | MO_UW,</div>\r\n" - "<div> MO_LEUL = MO_LE | MO_UL,</div>\r\n" - "<div> MO_LESW = MO_LE | MO_SW,</div>\r\n" - "<div> MO_LESL = MO_LE | MO_SL,</div>\r\n" - "<div>- MO_LEQ = MO_LE | MO_Q,</div>\r\n" - "<div>+ MO_LEQ = MO_LE | MO_UQ,</div>\r\n" - "<div> </div>\r\n" - "<div> MO_BEUW = MO_BE | MO_UW,</div>\r\n" - "<div> MO_BEUL = MO_BE | MO_UL,</div>\r\n" - "<div> MO_BESW = MO_BE | MO_SW,</div>\r\n" - "<div> MO_BESL = MO_BE | MO_SL,</div>\r\n" - "<div>- MO_BEQ = MO_BE | MO_Q,</div>\r\n" - "<div>+ MO_BEQ = MO_BE | MO_UQ,</div>\r\n" - "<div> </div>\r\n" - "<div> MO_TEUW = MO_TE | MO_UW,</div>\r\n" - "<div> MO_TEUL = MO_TE | MO_UL,</div>\r\n" - "<div> MO_TESW = MO_TE | MO_SW,</div>\r\n" - "<div> MO_TESL = MO_TE | MO_SL,</div>\r\n" - "<div>- MO_TEQ = MO_TE | MO_Q,</div>\r\n" - "<div>+ MO_TEQ = MO_TE | MO_UQ,</div>\r\n" - "<div> </div>\r\n" - "<div> MO_SSIZE = MO_SIZE | MO_SIGN,</div>\r\n" - "<div> } TCGMemOp;</div>\r\n" - "<div>-- </div>\r\n" - "<div>1.8.3.1</div>\r\n" - "<div><br>\r\n" - "<br>\r\n" - "</div>\r\n" - "<p><br>\r\n" - "</p>\r\n" - "</body>\r\n" - "</html>\r\n" -08e531a2e82e40ec503edfffb6f1f2344d1925ff54d4c332082fb8e6bc596cb1 +817cc31b73647c1cd7bf464c7739546c428839c523ac82e685a20e147af7a944
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